]>
Commit | Line | Data |
---|---|---|
33b9079b KG |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
33b9079b KG |
5 | */ |
6 | ||
7 | #include <common.h> | |
3e3262bd | 8 | #include <i2c.h> |
33b9079b | 9 | |
5614e71b YS |
10 | #include <fsl_ddr_sdram.h> |
11 | #include <fsl_ddr_dimm_params.h> | |
33b9079b | 12 | |
dfb49108 HW |
13 | void fsl_ddr_board_options(memctl_options_t *popts, |
14 | dimm_params_t *pdimm, | |
15 | unsigned int ctrl_num) | |
33b9079b KG |
16 | { |
17 | /* | |
18 | * Factors to consider for clock adjust: | |
19 | * - number of chips on bus | |
20 | * - position of slot | |
21 | * - DDR1 vs. DDR2? | |
22 | * - ??? | |
23 | * | |
24 | * This needs to be determined on a board-by-board basis. | |
25 | * 0110 3/4 cycle late | |
26 | * 0111 7/8 cycle late | |
27 | */ | |
28 | popts->clk_adjust = 7; | |
29 | ||
30 | /* | |
31 | * Factors to consider for CPO: | |
32 | * - frequency | |
33 | * - ddr1 vs. ddr2 | |
34 | */ | |
35 | popts->cpo_override = 10; | |
36 | ||
37 | /* | |
38 | * Factors to consider for write data delay: | |
39 | * - number of DIMMs | |
40 | * | |
41 | * 1 = 1/4 clock delay | |
42 | * 2 = 1/2 clock delay | |
43 | * 3 = 3/4 clock delay | |
44 | * 4 = 1 clock delay | |
45 | * 5 = 5/4 clock delay | |
46 | * 6 = 3/2 clock delay | |
47 | */ | |
48 | popts->write_data_delay = 3; | |
49 | ||
50 | /* | |
51 | * Factors to consider for half-strength driver enable: | |
52 | * - number of DIMMs installed | |
53 | */ | |
54 | popts->half_strength_driver_enable = 0; | |
55 | } | |
2a6b3b74 | 56 | |
3e3262bd PG |
57 | #ifdef CONFIG_SPD_EEPROM |
58 | /* | |
59 | * Workaround for hardware errata. An i2c address conflict | |
60 | * existed on earlier boards; the workaround moved the DDR | |
61 | * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and | |
62 | * if that fails, then fall back to reading at 0x51. | |
63 | */ | |
64 | void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) | |
65 | { | |
66 | int ret; | |
67 | ||
68 | #ifdef ALT_SPD_EEPROM_ADDRESS | |
69 | if (i2c_address == SPD_EEPROM_ADDRESS) { | |
70 | ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, | |
71 | sizeof(generic_spd_eeprom_t)); | |
72 | if (ret == 0) | |
73 | return; /* Good data at 0x53 */ | |
74 | memset(spd, 0, sizeof(generic_spd_eeprom_t)); | |
75 | } | |
76 | #endif | |
77 | ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, | |
78 | sizeof(generic_spd_eeprom_t)); | |
79 | if (ret) { | |
80 | printf("DDR: failed to read SPD from addr %u\n", i2c_address); | |
81 | memset(spd, 0, sizeof(generic_spd_eeprom_t)); | |
82 | } | |
83 | } | |
84 | ||
85 | #else | |
2a6b3b74 PG |
86 | /* |
87 | * fixed_sdram init -- doesn't use serial presence detect. | |
88 | * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. | |
89 | */ | |
90 | phys_size_t fixed_sdram(void) | |
91 | { | |
9a17eb5b YS |
92 | struct ccsr_ddr __iomem *ddr = |
93 | (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); | |
2a6b3b74 PG |
94 | |
95 | out_be32(&ddr->cs0_bnds, 0x0000007f); | |
96 | out_be32(&ddr->cs1_bnds, 0x008000ff); | |
97 | out_be32(&ddr->cs2_bnds, 0x00000000); | |
98 | out_be32(&ddr->cs3_bnds, 0x00000000); | |
99 | ||
100 | out_be32(&ddr->cs0_config, 0x80010101); | |
101 | out_be32(&ddr->cs1_config, 0x80010101); | |
102 | out_be32(&ddr->cs2_config, 0x00000000); | |
103 | out_be32(&ddr->cs3_config, 0x00000000); | |
104 | ||
105 | out_be32(&ddr->timing_cfg_3, 0x00000000); | |
106 | out_be32(&ddr->timing_cfg_0, 0x00220802); | |
107 | out_be32(&ddr->timing_cfg_1, 0x38377322); | |
108 | out_be32(&ddr->timing_cfg_2, 0x0fa044C7); | |
109 | ||
110 | out_be32(&ddr->sdram_cfg, 0x4300C000); | |
111 | out_be32(&ddr->sdram_cfg_2, 0x24401000); | |
112 | ||
113 | out_be32(&ddr->sdram_mode, 0x23C00542); | |
114 | out_be32(&ddr->sdram_mode_2, 0x00000000); | |
115 | ||
116 | out_be32(&ddr->sdram_interval, 0x05080100); | |
117 | out_be32(&ddr->sdram_md_cntl, 0x00000000); | |
118 | out_be32(&ddr->sdram_data_init, 0x00000000); | |
119 | out_be32(&ddr->sdram_clk_cntl, 0x03800000); | |
120 | asm("sync;isync;msync"); | |
121 | udelay(500); | |
122 | ||
123 | #ifdef CONFIG_DDR_ECC | |
124 | /* Enable ECC checking */ | |
125 | out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); | |
126 | #else | |
127 | out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); | |
128 | #endif | |
129 | ||
130 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; | |
131 | } | |
132 | #endif |