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11c45ebd | 1 | /* |
bd42bbb8 PG |
2 | * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> |
3 | * | |
11c45ebd JH |
4 | * Copyright 2007 Embedded Specialties, Inc. |
5 | * | |
6 | * Copyright 2004, 2007 Freescale Semiconductor. | |
7 | * | |
8 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/immap_85xx.h> | |
c8514622 | 33 | #include <asm/fsl_pci.h> |
33b9079b | 34 | #include <asm/fsl_ddr_sdram.h> |
5d27e02c | 35 | #include <asm/fsl_serdes.h> |
a30a549a | 36 | #include <spd_sdram.h> |
94ca0914 PG |
37 | #include <netdev.h> |
38 | #include <tsec.h> | |
11c45ebd JH |
39 | #include <miiphy.h> |
40 | #include <libfdt.h> | |
41 | #include <fdt_support.h> | |
42 | ||
11c45ebd JH |
43 | DECLARE_GLOBAL_DATA_PTR; |
44 | ||
11c45ebd | 45 | void local_bus_init(void); |
11c45ebd JH |
46 | |
47 | int board_early_init_f (void) | |
48 | { | |
49 | return 0; | |
50 | } | |
51 | ||
52 | int checkboard (void) | |
53 | { | |
6d0f6bcf JCPV |
54 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
55 | volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; | |
11c45ebd JH |
56 | |
57 | printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", | |
0c7e4d45 | 58 | in_8(rev) >> 4); |
11c45ebd JH |
59 | |
60 | /* | |
61 | * Initialize local bus. | |
62 | */ | |
63 | local_bus_init (); | |
64 | ||
0c7e4d45 PG |
65 | out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ |
66 | out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ | |
11c45ebd JH |
67 | return 0; |
68 | } | |
69 | ||
11c45ebd JH |
70 | /* |
71 | * Initialize Local Bus | |
72 | */ | |
73 | void | |
74 | local_bus_init(void) | |
75 | { | |
6d0f6bcf | 76 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
f51cdaf1 | 77 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
11c45ebd | 78 | |
e2b363ff | 79 | uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; |
11c45ebd JH |
80 | sys_info_t sysinfo; |
81 | ||
82 | get_sys_info(&sysinfo); | |
e2b363ff PG |
83 | |
84 | lbc_mhz = sysinfo.freqLocalBus / 1000000; | |
85 | clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus; | |
86 | ||
87 | debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); | |
11c45ebd | 88 | |
0c7e4d45 | 89 | out_be32(&gur->lbiuiplldcr1, 0x00078080); |
11c45ebd | 90 | if (clkdiv == 16) { |
0c7e4d45 | 91 | out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); |
11c45ebd | 92 | } else if (clkdiv == 8) { |
0c7e4d45 | 93 | out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); |
11c45ebd | 94 | } else if (clkdiv == 4) { |
0c7e4d45 | 95 | out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); |
11c45ebd JH |
96 | } |
97 | ||
e2b363ff PG |
98 | /* |
99 | * Local Bus Clock > 83.3 MHz. According to timing | |
100 | * specifications set LCRR[EADC] to 2 delay cycles. | |
101 | */ | |
102 | if (lbc_mhz > 83) { | |
103 | lcrr &= ~LCRR_EADC; | |
104 | lcrr |= LCRR_EADC_2; | |
105 | } | |
106 | ||
107 | /* | |
108 | * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 | |
109 | * disable PLL bypass for Local Bus Clock > 83 MHz. | |
110 | */ | |
111 | if (lbc_mhz >= 66) | |
112 | lcrr &= (~LCRR_DBYP); /* DLL Enabled */ | |
113 | ||
114 | else | |
115 | lcrr |= LCRR_DBYP; /* DLL Bypass */ | |
11c45ebd | 116 | |
e2b363ff | 117 | out_be32(&lbc->lcrr, lcrr); |
11c45ebd JH |
118 | asm("sync;isync;msync"); |
119 | ||
e2b363ff PG |
120 | /* |
121 | * According to MPC8548ERMAD Rev.1.3 read back LCRR | |
122 | * and terminate with isync | |
123 | */ | |
124 | lcrr = in_be32(&lbc->lcrr); | |
125 | asm ("isync;"); | |
126 | ||
127 | /* let DLL stabilize */ | |
128 | udelay(500); | |
129 | ||
0c7e4d45 PG |
130 | out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ |
131 | out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ | |
11c45ebd JH |
132 | } |
133 | ||
134 | /* | |
135 | * Initialize SDRAM memory on the Local Bus. | |
136 | */ | |
70961ba4 | 137 | void lbc_sdram_init(void) |
11c45ebd | 138 | { |
11d5a629 | 139 | #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) |
11c45ebd JH |
140 | |
141 | uint idx; | |
5f4c6f0d | 142 | const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; |
f51cdaf1 | 143 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
6d0f6bcf | 144 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
5f4c6f0d | 145 | uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2); |
11c45ebd JH |
146 | |
147 | puts(" SDRAM: "); | |
148 | ||
5f4c6f0d | 149 | print_size(size, "\n"); |
11c45ebd JH |
150 | |
151 | /* | |
152 | * Setup SDRAM Base and Option Registers | |
153 | */ | |
f51cdaf1 BB |
154 | set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); |
155 | set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); | |
156 | set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); | |
157 | set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); | |
11d5a629 | 158 | |
0c7e4d45 | 159 | out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); |
11c45ebd JH |
160 | asm("msync"); |
161 | ||
0c7e4d45 PG |
162 | out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); |
163 | out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); | |
11c45ebd JH |
164 | asm("msync"); |
165 | ||
11c45ebd JH |
166 | /* |
167 | * Issue PRECHARGE ALL command. | |
168 | */ | |
5f4c6f0d | 169 | out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL); |
11c45ebd JH |
170 | asm("sync;msync"); |
171 | *sdram_addr = 0xff; | |
172 | ppcDcbf((unsigned long) sdram_addr); | |
5f4c6f0d PG |
173 | *sdram_addr2 = 0xff; |
174 | ppcDcbf((unsigned long) sdram_addr2); | |
11c45ebd JH |
175 | udelay(100); |
176 | ||
177 | /* | |
178 | * Issue 8 AUTO REFRESH commands. | |
179 | */ | |
180 | for (idx = 0; idx < 8; idx++) { | |
5f4c6f0d | 181 | out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH); |
11c45ebd JH |
182 | asm("sync;msync"); |
183 | *sdram_addr = 0xff; | |
184 | ppcDcbf((unsigned long) sdram_addr); | |
5f4c6f0d PG |
185 | *sdram_addr2 = 0xff; |
186 | ppcDcbf((unsigned long) sdram_addr2); | |
11c45ebd JH |
187 | udelay(100); |
188 | } | |
189 | ||
190 | /* | |
191 | * Issue 8 MODE-set command. | |
192 | */ | |
5f4c6f0d | 193 | out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW); |
11c45ebd JH |
194 | asm("sync;msync"); |
195 | *sdram_addr = 0xff; | |
196 | ppcDcbf((unsigned long) sdram_addr); | |
5f4c6f0d PG |
197 | *sdram_addr2 = 0xff; |
198 | ppcDcbf((unsigned long) sdram_addr2); | |
11c45ebd JH |
199 | udelay(100); |
200 | ||
201 | /* | |
5f4c6f0d | 202 | * Issue RFEN command. |
11c45ebd | 203 | */ |
5f4c6f0d | 204 | out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN); |
11c45ebd JH |
205 | asm("sync;msync"); |
206 | *sdram_addr = 0xff; | |
207 | ppcDcbf((unsigned long) sdram_addr); | |
5f4c6f0d PG |
208 | *sdram_addr2 = 0xff; |
209 | ppcDcbf((unsigned long) sdram_addr2); | |
11c45ebd JH |
210 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
211 | ||
212 | #endif /* enable SDRAM init */ | |
213 | } | |
214 | ||
6d0f6bcf | 215 | #if defined(CONFIG_SYS_DRAM_TEST) |
11c45ebd JH |
216 | int |
217 | testdram(void) | |
218 | { | |
6d0f6bcf JCPV |
219 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
220 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; | |
11c45ebd JH |
221 | uint *p; |
222 | ||
223 | printf("Testing DRAM from 0x%08x to 0x%08x\n", | |
6d0f6bcf JCPV |
224 | CONFIG_SYS_MEMTEST_START, |
225 | CONFIG_SYS_MEMTEST_END); | |
11c45ebd JH |
226 | |
227 | printf("DRAM test phase 1:\n"); | |
228 | for (p = pstart; p < pend; p++) | |
229 | *p = 0xaaaaaaaa; | |
230 | ||
231 | for (p = pstart; p < pend; p++) { | |
232 | if (*p != 0xaaaaaaaa) { | |
233 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
234 | return 1; | |
235 | } | |
236 | } | |
237 | ||
238 | printf("DRAM test phase 2:\n"); | |
239 | for (p = pstart; p < pend; p++) | |
240 | *p = 0x55555555; | |
241 | ||
242 | for (p = pstart; p < pend; p++) { | |
243 | if (*p != 0x55555555) { | |
244 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
245 | return 1; | |
246 | } | |
247 | } | |
248 | ||
249 | printf("DRAM test passed.\n"); | |
250 | return 0; | |
251 | } | |
252 | #endif | |
253 | ||
7b1f1399 PG |
254 | #ifdef CONFIG_PCI1 |
255 | static struct pci_controller pci1_hose; | |
256 | #endif /* CONFIG_PCI1 */ | |
11c45ebd | 257 | |
fdc7eb90 | 258 | #ifdef CONFIG_PCI |
11c45ebd JH |
259 | void |
260 | pci_init_board(void) | |
261 | { | |
6d0f6bcf | 262 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
fdc7eb90 | 263 | int first_free_busno = 0; |
fdc7eb90 PG |
264 | |
265 | #ifdef CONFIG_PCI1 | |
2d0a054d KG |
266 | struct fsl_pci_info pci_info; |
267 | u32 devdisr = in_be32(&gur->devdisr); | |
268 | u32 pordevsr = in_be32(&gur->pordevsr); | |
269 | u32 porpllsr = in_be32(&gur->porpllsr); | |
270 | ||
fdc7eb90 PG |
271 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
272 | uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; | |
273 | uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; | |
274 | uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; | |
275 | uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ | |
11c45ebd | 276 | |
8ca78f2c | 277 | printf("PCI: Host, %d bit, %s MHz, %s, %s\n", |
11c45ebd | 278 | (pci_32) ? 32 : 64, |
2c40acd3 PG |
279 | (pci_speed == 33000000) ? "33" : |
280 | (pci_speed == 66000000) ? "66" : "unknown", | |
11c45ebd | 281 | pci_clk_sel ? "sync" : "async", |
fdc7eb90 PG |
282 | pci_arb ? "arbiter" : "external-arbiter"); |
283 | ||
2d0a054d KG |
284 | SET_STD_PCI_INFO(pci_info, 1); |
285 | set_next_law(pci_info.mem_phys, | |
286 | law_size_bits(pci_info.mem_size), pci_info.law); | |
287 | set_next_law(pci_info.io_phys, | |
288 | law_size_bits(pci_info.io_size), pci_info.law); | |
289 | ||
290 | first_free_busno = fsl_pci_init_port(&pci_info, | |
01471d53 | 291 | &pci1_hose, first_free_busno); |
11c45ebd | 292 | } else { |
8ca78f2c | 293 | printf("PCI: disabled\n"); |
11c45ebd | 294 | } |
fdc7eb90 PG |
295 | |
296 | puts("\n"); | |
11c45ebd | 297 | #else |
fdc7eb90 | 298 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ |
11c45ebd JH |
299 | #endif |
300 | ||
fdc7eb90 | 301 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ |
11c45ebd | 302 | |
2d0a054d | 303 | fsl_pcie_init_board(first_free_busno); |
11c45ebd | 304 | } |
fdc7eb90 | 305 | #endif |
11c45ebd | 306 | |
94ca0914 PG |
307 | int board_eth_init(bd_t *bis) |
308 | { | |
309 | tsec_standard_init(bis); | |
310 | pci_eth_init(bis); | |
311 | return 0; /* otherwise cpu_eth_init gets run */ | |
312 | } | |
313 | ||
11c45ebd JH |
314 | int last_stage_init(void) |
315 | { | |
316 | return 0; | |
317 | } | |
318 | ||
319 | #if defined(CONFIG_OF_BOARD_SETUP) | |
2dba0dea KG |
320 | void ft_board_setup(void *blob, bd_t *bd) |
321 | { | |
322 | ft_cpu_setup(blob, bd); | |
6525d51f KG |
323 | |
324 | #ifdef CONFIG_FSL_PCI_INIT | |
325 | FT_FSL_PCI_SETUP; | |
11c45ebd JH |
326 | #endif |
327 | } | |
328 | #endif |