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11c45ebd | 1 | /* |
bd42bbb8 PG |
2 | * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> |
3 | * | |
11c45ebd JH |
4 | * Copyright 2007 Embedded Specialties, Inc. |
5 | * | |
6 | * Copyright 2004, 2007 Freescale Semiconductor. | |
7 | * | |
8 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/immap_85xx.h> | |
c8514622 | 33 | #include <asm/fsl_pci.h> |
33b9079b | 34 | #include <asm/fsl_ddr_sdram.h> |
5d27e02c | 35 | #include <asm/fsl_serdes.h> |
a30a549a | 36 | #include <spd_sdram.h> |
94ca0914 PG |
37 | #include <netdev.h> |
38 | #include <tsec.h> | |
11c45ebd JH |
39 | #include <miiphy.h> |
40 | #include <libfdt.h> | |
41 | #include <fdt_support.h> | |
42 | ||
11c45ebd JH |
43 | DECLARE_GLOBAL_DATA_PTR; |
44 | ||
11c45ebd | 45 | void local_bus_init(void); |
11c45ebd JH |
46 | |
47 | int board_early_init_f (void) | |
48 | { | |
49 | return 0; | |
50 | } | |
51 | ||
52 | int checkboard (void) | |
53 | { | |
6d0f6bcf JCPV |
54 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
55 | volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; | |
11c45ebd JH |
56 | |
57 | printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", | |
0c7e4d45 | 58 | in_8(rev) >> 4); |
11c45ebd JH |
59 | |
60 | /* | |
61 | * Initialize local bus. | |
62 | */ | |
63 | local_bus_init (); | |
64 | ||
0c7e4d45 PG |
65 | out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ |
66 | out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ | |
11c45ebd JH |
67 | return 0; |
68 | } | |
69 | ||
11c45ebd JH |
70 | /* |
71 | * Initialize Local Bus | |
72 | */ | |
73 | void | |
74 | local_bus_init(void) | |
75 | { | |
6d0f6bcf | 76 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
f51cdaf1 | 77 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
11c45ebd JH |
78 | |
79 | uint clkdiv; | |
80 | uint lbc_hz; | |
81 | sys_info_t sysinfo; | |
82 | ||
83 | get_sys_info(&sysinfo); | |
0c7e4d45 | 84 | clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; |
11c45ebd JH |
85 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
86 | ||
0c7e4d45 | 87 | out_be32(&gur->lbiuiplldcr1, 0x00078080); |
11c45ebd | 88 | if (clkdiv == 16) { |
0c7e4d45 | 89 | out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); |
11c45ebd | 90 | } else if (clkdiv == 8) { |
0c7e4d45 | 91 | out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); |
11c45ebd | 92 | } else if (clkdiv == 4) { |
0c7e4d45 | 93 | out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); |
11c45ebd JH |
94 | } |
95 | ||
0c7e4d45 | 96 | setbits_be32(&lbc->lcrr, 0x00030000); |
11c45ebd JH |
97 | |
98 | asm("sync;isync;msync"); | |
99 | ||
0c7e4d45 PG |
100 | out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ |
101 | out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ | |
11c45ebd JH |
102 | } |
103 | ||
104 | /* | |
105 | * Initialize SDRAM memory on the Local Bus. | |
106 | */ | |
107 | void | |
108 | sdram_init(void) | |
109 | { | |
11d5a629 | 110 | #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) |
11c45ebd JH |
111 | |
112 | uint idx; | |
f51cdaf1 | 113 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
6d0f6bcf | 114 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
11c45ebd JH |
115 | uint lsdmr_common; |
116 | ||
117 | puts(" SDRAM: "); | |
118 | ||
6d0f6bcf | 119 | print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
11c45ebd JH |
120 | |
121 | /* | |
122 | * Setup SDRAM Base and Option Registers | |
123 | */ | |
f51cdaf1 BB |
124 | set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); |
125 | set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); | |
126 | set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); | |
127 | set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); | |
11d5a629 | 128 | |
0c7e4d45 | 129 | out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); |
11c45ebd JH |
130 | asm("msync"); |
131 | ||
0c7e4d45 PG |
132 | out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); |
133 | out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); | |
11c45ebd JH |
134 | asm("msync"); |
135 | ||
136 | /* | |
137 | * MPC8548 uses "new" 15-16 style addressing. | |
138 | */ | |
6d0f6bcf | 139 | lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; |
b0fe93ed | 140 | lsdmr_common |= LSDMR_BSMA1516; |
11c45ebd JH |
141 | |
142 | /* | |
143 | * Issue PRECHARGE ALL command. | |
144 | */ | |
0c7e4d45 | 145 | out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); |
11c45ebd JH |
146 | asm("sync;msync"); |
147 | *sdram_addr = 0xff; | |
148 | ppcDcbf((unsigned long) sdram_addr); | |
149 | udelay(100); | |
150 | ||
151 | /* | |
152 | * Issue 8 AUTO REFRESH commands. | |
153 | */ | |
154 | for (idx = 0; idx < 8; idx++) { | |
0c7e4d45 | 155 | out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); |
11c45ebd JH |
156 | asm("sync;msync"); |
157 | *sdram_addr = 0xff; | |
158 | ppcDcbf((unsigned long) sdram_addr); | |
159 | udelay(100); | |
160 | } | |
161 | ||
162 | /* | |
163 | * Issue 8 MODE-set command. | |
164 | */ | |
0c7e4d45 | 165 | out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); |
11c45ebd JH |
166 | asm("sync;msync"); |
167 | *sdram_addr = 0xff; | |
168 | ppcDcbf((unsigned long) sdram_addr); | |
169 | udelay(100); | |
170 | ||
171 | /* | |
172 | * Issue NORMAL OP command. | |
173 | */ | |
0c7e4d45 | 174 | out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); |
11c45ebd JH |
175 | asm("sync;msync"); |
176 | *sdram_addr = 0xff; | |
177 | ppcDcbf((unsigned long) sdram_addr); | |
178 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ | |
179 | ||
180 | #endif /* enable SDRAM init */ | |
181 | } | |
182 | ||
6d0f6bcf | 183 | #if defined(CONFIG_SYS_DRAM_TEST) |
11c45ebd JH |
184 | int |
185 | testdram(void) | |
186 | { | |
6d0f6bcf JCPV |
187 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
188 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; | |
11c45ebd JH |
189 | uint *p; |
190 | ||
191 | printf("Testing DRAM from 0x%08x to 0x%08x\n", | |
6d0f6bcf JCPV |
192 | CONFIG_SYS_MEMTEST_START, |
193 | CONFIG_SYS_MEMTEST_END); | |
11c45ebd JH |
194 | |
195 | printf("DRAM test phase 1:\n"); | |
196 | for (p = pstart; p < pend; p++) | |
197 | *p = 0xaaaaaaaa; | |
198 | ||
199 | for (p = pstart; p < pend; p++) { | |
200 | if (*p != 0xaaaaaaaa) { | |
201 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
202 | return 1; | |
203 | } | |
204 | } | |
205 | ||
206 | printf("DRAM test phase 2:\n"); | |
207 | for (p = pstart; p < pend; p++) | |
208 | *p = 0x55555555; | |
209 | ||
210 | for (p = pstart; p < pend; p++) { | |
211 | if (*p != 0x55555555) { | |
212 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
213 | return 1; | |
214 | } | |
215 | } | |
216 | ||
217 | printf("DRAM test passed.\n"); | |
218 | return 0; | |
219 | } | |
220 | #endif | |
221 | ||
0c7e4d45 PG |
222 | #if !defined(CONFIG_SPD_EEPROM) |
223 | #define CONFIG_SYS_DDR_CONTROL 0xc300c000 | |
11c45ebd JH |
224 | /************************************************************************* |
225 | * fixed_sdram init -- doesn't use serial presence detect. | |
226 | * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. | |
227 | ************************************************************************/ | |
38dba0c2 | 228 | phys_size_t fixed_sdram(void) |
11c45ebd | 229 | { |
6d0f6bcf | 230 | volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
11c45ebd | 231 | |
0c7e4d45 PG |
232 | out_be32(&ddr->cs0_bnds, 0x0000007f); |
233 | out_be32(&ddr->cs1_bnds, 0x008000ff); | |
234 | out_be32(&ddr->cs2_bnds, 0x00000000); | |
235 | out_be32(&ddr->cs3_bnds, 0x00000000); | |
236 | out_be32(&ddr->cs0_config, 0x80010101); | |
237 | out_be32(&ddr->cs1_config, 0x80010101); | |
238 | out_be32(&ddr->cs2_config, 0x00000000); | |
239 | out_be32(&ddr->cs3_config, 0x00000000); | |
240 | out_be32(&ddr->timing_cfg_3, 0x00000000); | |
241 | out_be32(&ddr->timing_cfg_0, 0x00220802); | |
242 | out_be32(&ddr->timing_cfg_1, 0x38377322); | |
243 | out_be32(&ddr->timing_cfg_2, 0x0fa044C7); | |
244 | out_be32(&ddr->sdram_cfg, 0x4300C000); | |
245 | out_be32(&ddr->sdram_cfg_2, 0x24401000); | |
246 | out_be32(&ddr->sdram_mode, 0x23C00542); | |
247 | out_be32(&ddr->sdram_mode_2, 0x00000000); | |
248 | out_be32(&ddr->sdram_interval, 0x05080100); | |
249 | out_be32(&ddr->sdram_md_cntl, 0x00000000); | |
250 | out_be32(&ddr->sdram_data_init, 0x00000000); | |
251 | out_be32(&ddr->sdram_clk_cntl, 0x03800000); | |
11c45ebd JH |
252 | asm("sync;isync;msync"); |
253 | udelay(500); | |
254 | ||
255 | #if defined (CONFIG_DDR_ECC) | |
256 | /* Enable ECC checking */ | |
0c7e4d45 | 257 | out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); |
11c45ebd | 258 | #else |
0c7e4d45 | 259 | out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); |
11c45ebd JH |
260 | #endif |
261 | ||
6d0f6bcf | 262 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
11c45ebd JH |
263 | } |
264 | #endif | |
265 | ||
7b1f1399 PG |
266 | #ifdef CONFIG_PCI1 |
267 | static struct pci_controller pci1_hose; | |
268 | #endif /* CONFIG_PCI1 */ | |
11c45ebd JH |
269 | |
270 | #ifdef CONFIG_PCIE1 | |
271 | static struct pci_controller pcie1_hose; | |
272 | #endif /* CONFIG_PCIE1 */ | |
273 | ||
11c45ebd | 274 | |
fdc7eb90 | 275 | #ifdef CONFIG_PCI |
11c45ebd JH |
276 | void |
277 | pci_init_board(void) | |
278 | { | |
6d0f6bcf | 279 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
fdc7eb90 PG |
280 | struct fsl_pci_info pci_info[2]; |
281 | u32 devdisr, pordevsr, porpllsr, io_sel; | |
282 | int first_free_busno = 0; | |
283 | int num = 0; | |
11c45ebd | 284 | |
fdc7eb90 PG |
285 | #ifdef CONFIG_PCIE1 |
286 | int pcie_configured; | |
287 | #endif | |
11c45ebd | 288 | |
fdc7eb90 PG |
289 | devdisr = in_be32(&gur->devdisr); |
290 | pordevsr = in_be32(&gur->pordevsr); | |
291 | porpllsr = in_be32(&gur->porpllsr); | |
292 | io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; | |
11c45ebd | 293 | |
fdc7eb90 PG |
294 | debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); |
295 | ||
296 | #ifdef CONFIG_PCI1 | |
297 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { | |
298 | uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; | |
299 | uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; | |
300 | uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; | |
301 | uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ | |
11c45ebd | 302 | |
8ca78f2c | 303 | printf("PCI: Host, %d bit, %s MHz, %s, %s\n", |
11c45ebd | 304 | (pci_32) ? 32 : 64, |
2c40acd3 PG |
305 | (pci_speed == 33000000) ? "33" : |
306 | (pci_speed == 66000000) ? "66" : "unknown", | |
11c45ebd | 307 | pci_clk_sel ? "sync" : "async", |
fdc7eb90 PG |
308 | pci_arb ? "arbiter" : "external-arbiter"); |
309 | ||
310 | SET_STD_PCI_INFO(pci_info[num], 1); | |
311 | first_free_busno = fsl_pci_init_port(&pci_info[num++], | |
01471d53 | 312 | &pci1_hose, first_free_busno); |
11c45ebd | 313 | } else { |
8ca78f2c | 314 | printf("PCI: disabled\n"); |
11c45ebd | 315 | } |
fdc7eb90 PG |
316 | |
317 | puts("\n"); | |
11c45ebd | 318 | #else |
fdc7eb90 | 319 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ |
11c45ebd JH |
320 | #endif |
321 | ||
fdc7eb90 | 322 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ |
11c45ebd JH |
323 | |
324 | #ifdef CONFIG_PCIE1 | |
5d27e02c | 325 | pcie_configured = is_serdes_configured(PCIE1); |
11c45ebd | 326 | |
fdc7eb90 PG |
327 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ |
328 | SET_STD_PCIE_INFO(pci_info[num], 1); | |
8ca78f2c | 329 | printf("PCIE: base address %lx\n", pci_info[num].regs); |
fdc7eb90 | 330 | first_free_busno = fsl_pci_init_port(&pci_info[num++], |
01471d53 | 331 | &pcie1_hose, first_free_busno); |
11c45ebd | 332 | } else { |
8ca78f2c | 333 | printf("PCIE: disabled\n"); |
11c45ebd | 334 | } |
fdc7eb90 PG |
335 | |
336 | puts("\n"); | |
11c45ebd | 337 | #else |
fdc7eb90 | 338 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ |
11c45ebd | 339 | #endif |
11c45ebd | 340 | } |
fdc7eb90 | 341 | #endif |
11c45ebd | 342 | |
94ca0914 PG |
343 | int board_eth_init(bd_t *bis) |
344 | { | |
345 | tsec_standard_init(bis); | |
346 | pci_eth_init(bis); | |
347 | return 0; /* otherwise cpu_eth_init gets run */ | |
348 | } | |
349 | ||
11c45ebd JH |
350 | int last_stage_init(void) |
351 | { | |
352 | return 0; | |
353 | } | |
354 | ||
355 | #if defined(CONFIG_OF_BOARD_SETUP) | |
2dba0dea KG |
356 | void ft_board_setup(void *blob, bd_t *bd) |
357 | { | |
358 | ft_cpu_setup(blob, bd); | |
6525d51f KG |
359 | |
360 | #ifdef CONFIG_FSL_PCI_INIT | |
361 | FT_FSL_PCI_SETUP; | |
11c45ebd JH |
362 | #endif |
363 | } | |
364 | #endif |