[thirdparty/u-boot.git] / board / sbc8548 / sbc8548.c

/*
 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
 *
 * Copyright 2007 Embedded Specialties, Inc.
 *
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>

void local_bus_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;

	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
			in_8(rev) >> 4);

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);

	lbc_mhz = sysinfo.freq_localbus / 1000000;
	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;

	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16) {
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	} else if (clkdiv == 8) {
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	} else if (clkdiv == 4) {
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	}

	/*
	 * Local Bus Clock > 83.3 MHz. According to timing
	 * specifications set LCRR[EADC] to 2 delay cycles.
	 */
	if (lbc_mhz > 83) {
		lcrr &= ~LCRR_EADC;
		lcrr |= LCRR_EADC_2;
	}

	/*
	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	 * disable PLL bypass for Local Bus Clock > 83 MHz.
	 */
	if (lbc_mhz >= 66)
		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */

	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32(&lbc->lcrr, lcrr);
	asm("sync;isync;msync");

	 /*
	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
	 * and terminate with isync
	 */
	lcrr = in_be32(&lbc->lcrr);
	asm ("isync;");

	/* let DLL stabilize */
	udelay(500);

	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)

	uint idx;
	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);

	puts("    SDRAM: ");

	print_size(size, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);

	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
	asm("msync");

	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
	asm("msync");

	/*
	 * Issue PRECHARGE ALL command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		*sdram_addr2 = 0xff;
		ppcDcbf((unsigned long) sdram_addr2);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue RFEN command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif	/* CONFIG_PCI1 */

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int first_free_busno = 0;

#ifdef CONFIG_PCI1
	struct fsl_pci_info pci_info;
	u32 devdisr = in_be32(&gur->devdisr);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 porpllsr = in_be32(&gur->porpllsr);

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */

		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33000000) ? "33" :
			(pci_speed == 66000000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_arb ? "arbiter" : "external-arbiter");

		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */

	fsl_pcie_init_board(first_free_busno);
}
#endif

int board_eth_init(bd_t *bis)
{
	tsec_standard_init(bis);
	pci_eth_init(bis);
	return 0;	/* otherwise cpu_eth_init gets run */
}

int last_stage_init(void)
{
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_FSL_PCI_INIT
	FT_FSL_PCI_SETUP;
#endif

	return 0;
}
#endif
Commit	Line	Data
11c45ebd	1	/*
bd42bbb8 PG	2	* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
bd42bbb8 PG	3	*
11c45ebd JH	4	* Copyright 2007 Embedded Specialties, Inc.
	5	*
	6	* Copyright 2004, 2007 Freescale Semiconductor.
	7	*
	8	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
11c45ebd JH	11	*/
	12
	13	#include <common.h>
	14	#include <pci.h>
	15	#include <asm/processor.h>
	16	#include <asm/immap_85xx.h>
c8514622	17	#include <asm/fsl_pci.h>
5614e71b	18	#include <fsl_ddr_sdram.h>
5d27e02c	19	#include <asm/fsl_serdes.h>
a30a549a	20	#include <spd_sdram.h>
94ca0914 PG	21	#include <netdev.h>
94ca0914 PG	22	#include <tsec.h>
11c45ebd	23	#include <miiphy.h>
b08c8c48	24	#include <linux/libfdt.h>
11c45ebd JH	25	#include <fdt_support.h>
11c45ebd JH	26
11c45ebd	27	void local_bus_init(void);
11c45ebd JH	28
	29	int board_early_init_f (void)
	30	{
	31	return 0;
	32	}
	33
	34	int checkboard (void)
	35	{
6d0f6bcf JCPV	36	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6d0f6bcf JCPV	37	volatile u_char rev= (void )CONFIG_SYS_BD_REV;
11c45ebd JH	38
11c45ebd JH	39	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
0c7e4d45	40	in_8(rev) >> 4);
11c45ebd JH	41
	42	/*
	43	* Initialize local bus.
	44	*/
	45	local_bus_init ();
	46
0c7e4d45 PG	47	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
0c7e4d45 PG	48	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
11c45ebd JH	49	return 0;
	50	}
	51
11c45ebd JH	52	/*
	53	* Initialize Local Bus
	54	*/
	55	void
	56	local_bus_init(void)
	57	{
6d0f6bcf	58	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	59	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
11c45ebd	60
e2b363ff	61	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
11c45ebd JH	62	sys_info_t sysinfo;
	63
	64	get_sys_info(&sysinfo);
e2b363ff	65
997399fa PK	66	lbc_mhz = sysinfo.freq_localbus / 1000000;
997399fa PK	67	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
e2b363ff PG	68
e2b363ff PG	69	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
11c45ebd	70
0c7e4d45	71	out_be32(&gur->lbiuiplldcr1, 0x00078080);
11c45ebd	72	if (clkdiv == 16) {
0c7e4d45	73	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
11c45ebd	74	} else if (clkdiv == 8) {
0c7e4d45	75	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
11c45ebd	76	} else if (clkdiv == 4) {
0c7e4d45	77	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
11c45ebd JH	78	}
11c45ebd JH	79
e2b363ff PG	80	/*
	81	* Local Bus Clock > 83.3 MHz. According to timing
	82	* specifications set LCRR[EADC] to 2 delay cycles.
	83	*/
	84	if (lbc_mhz > 83) {
	85	lcrr &= ~LCRR_EADC;
	86	lcrr \|= LCRR_EADC_2;
	87	}
	88
	89	/*
	90	* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	91	* disable PLL bypass for Local Bus Clock > 83 MHz.
	92	*/
	93	if (lbc_mhz >= 66)
	94	lcrr &= (~LCRR_DBYP); /* DLL Enabled */
	95
	96	else
	97	lcrr \|= LCRR_DBYP; /* DLL Bypass */
11c45ebd	98
e2b363ff	99	out_be32(&lbc->lcrr, lcrr);
11c45ebd JH	100	asm("sync;isync;msync");
11c45ebd JH	101
e2b363ff PG	102	/*
	103	* According to MPC8548ERMAD Rev.1.3 read back LCRR
	104	* and terminate with isync
	105	*/
	106	lcrr = in_be32(&lbc->lcrr);
	107	asm ("isync;");
	108
	109	/* let DLL stabilize */
	110	udelay(500);
	111
0c7e4d45 PG	112	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
0c7e4d45 PG	113	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
11c45ebd JH	114	}
	115
	116	/*
	117	* Initialize SDRAM memory on the Local Bus.
	118	*/
70961ba4	119	void lbc_sdram_init(void)
11c45ebd	120	{
11d5a629	121	#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
11c45ebd JH	122
11c45ebd JH	123	uint idx;
5f4c6f0d	124	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
f51cdaf1	125	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	126	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
5f4c6f0d	127	uint sdram_addr2 = (uint )(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
11c45ebd JH	128
	129	puts(" SDRAM: ");
	130
5f4c6f0d	131	print_size(size, "\n");
11c45ebd JH	132
	133	/*
	134	* Setup SDRAM Base and Option Registers
	135	*/
f51cdaf1 BB	136	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	137	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	138	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	139	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
11d5a629	140
0c7e4d45	141	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
11c45ebd JH	142	asm("msync");
11c45ebd JH	143
0c7e4d45 PG	144	out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
0c7e4d45 PG	145	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
11c45ebd JH	146	asm("msync");
11c45ebd JH	147
11c45ebd JH	148	/*
	149	* Issue PRECHARGE ALL command.
	150	*/
5f4c6f0d	151	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
11c45ebd JH	152	asm("sync;msync");
	153	*sdram_addr = 0xff;
	154	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	155	*sdram_addr2 = 0xff;
5f4c6f0d PG	156	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	157	udelay(100);
	158
	159	/*
	160	* Issue 8 AUTO REFRESH commands.
	161	*/
	162	for (idx = 0; idx < 8; idx++) {
5f4c6f0d	163	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
11c45ebd JH	164	asm("sync;msync");
	165	*sdram_addr = 0xff;
	166	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	167	*sdram_addr2 = 0xff;
5f4c6f0d PG	168	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	169	udelay(100);
	170	}
	171
	172	/*
	173	* Issue 8 MODE-set command.
	174	*/
5f4c6f0d	175	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
11c45ebd JH	176	asm("sync;msync");
	177	*sdram_addr = 0xff;
	178	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	179	*sdram_addr2 = 0xff;
5f4c6f0d PG	180	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	181	udelay(100);
	182
	183	/*
5f4c6f0d	184	* Issue RFEN command.
11c45ebd	185	*/
5f4c6f0d	186	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
11c45ebd JH	187	asm("sync;msync");
	188	*sdram_addr = 0xff;
	189	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	190	*sdram_addr2 = 0xff;
5f4c6f0d PG	191	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	192	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	193
	194	#endif /* enable SDRAM init */
	195	}
	196
6d0f6bcf	197	#if defined(CONFIG_SYS_DRAM_TEST)
11c45ebd JH	198	int
	199	testdram(void)
	200	{
6d0f6bcf JCPV	201	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	202	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
11c45ebd JH	203	uint *p;
	204
	205	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	206	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	207	CONFIG_SYS_MEMTEST_END);
11c45ebd JH	208
	209	printf("DRAM test phase 1:\n");
	210	for (p = pstart; p < pend; p++)
	211	*p = 0xaaaaaaaa;
	212
	213	for (p = pstart; p < pend; p++) {
	214	if (*p != 0xaaaaaaaa) {
	215	printf ("DRAM test fails at: %08x\n", (uint) p);
	216	return 1;
	217	}
	218	}
	219
	220	printf("DRAM test phase 2:\n");
	221	for (p = pstart; p < pend; p++)
	222	*p = 0x55555555;
	223
	224	for (p = pstart; p < pend; p++) {
	225	if (*p != 0x55555555) {
	226	printf ("DRAM test fails at: %08x\n", (uint) p);
	227	return 1;
	228	}
	229	}
	230
	231	printf("DRAM test passed.\n");
	232	return 0;
	233	}
	234	#endif
	235
7b1f1399 PG	236	#ifdef CONFIG_PCI1
	237	static struct pci_controller pci1_hose;
	238	#endif /* CONFIG_PCI1 */
11c45ebd	239
fdc7eb90	240	#ifdef CONFIG_PCI
11c45ebd JH	241	void
	242	pci_init_board(void)
	243	{
6d0f6bcf	244	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
fdc7eb90	245	int first_free_busno = 0;
fdc7eb90 PG	246
fdc7eb90 PG	247	#ifdef CONFIG_PCI1
2d0a054d KG	248	struct fsl_pci_info pci_info;
	249	u32 devdisr = in_be32(&gur->devdisr);
	250	u32 pordevsr = in_be32(&gur->pordevsr);
	251	u32 porpllsr = in_be32(&gur->porpllsr);
	252
fdc7eb90 PG	253	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	254	uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
	255	uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	256	uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	257	uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
11c45ebd	258
8ca78f2c	259	printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
11c45ebd	260	(pci_32) ? 32 : 64,
2c40acd3 PG	261	(pci_speed == 33000000) ? "33" :
2c40acd3 PG	262	(pci_speed == 66000000) ? "66" : "unknown",
11c45ebd	263	pci_clk_sel ? "sync" : "async",
fdc7eb90 PG	264	pci_arb ? "arbiter" : "external-arbiter");
fdc7eb90 PG	265
2d0a054d KG	266	SET_STD_PCI_INFO(pci_info, 1);
	267	set_next_law(pci_info.mem_phys,
	268	law_size_bits(pci_info.mem_size), pci_info.law);
	269	set_next_law(pci_info.io_phys,
	270	law_size_bits(pci_info.io_size), pci_info.law);
	271
	272	first_free_busno = fsl_pci_init_port(&pci_info,
01471d53	273	&pci1_hose, first_free_busno);
11c45ebd	274	} else {
8ca78f2c	275	printf("PCI: disabled\n");
11c45ebd	276	}
fdc7eb90 PG	277
fdc7eb90 PG	278	puts("\n");
11c45ebd	279	#else
fdc7eb90	280	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
11c45ebd JH	281	#endif
11c45ebd JH	282
fdc7eb90	283	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
11c45ebd	284
2d0a054d	285	fsl_pcie_init_board(first_free_busno);
11c45ebd	286	}
fdc7eb90	287	#endif
11c45ebd	288
94ca0914 PG	289	int board_eth_init(bd_t *bis)
	290	{
	291	tsec_standard_init(bis);
	292	pci_eth_init(bis);
	293	return 0; /* otherwise cpu_eth_init gets run */
	294	}
	295
11c45ebd JH	296	int last_stage_init(void)
	297	{
	298	return 0;
	299	}
	300
	301	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	302	int ft_board_setup(void blob, bd_t bd)
2dba0dea KG	303	{
2dba0dea KG	304	ft_cpu_setup(blob, bd);
6525d51f KG	305
	306	#ifdef CONFIG_FSL_PCI_INIT
	307	FT_FSL_PCI_SETUP;
11c45ebd	308	#endif
e895a4b0 SG	309
e895a4b0 SG	310	return 0;
11c45ebd JH	311	}
11c45ebd JH	312	#endif