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11c45ebd JH |
1 | /* |
2 | * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> | |
3 | * Copyright 2007 Embedded Specialties, Inc. | |
4 | * | |
5 | * Copyright 2004, 2007 Freescale Semiconductor. | |
6 | * | |
7 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <pci.h> | |
30 | #include <asm/processor.h> | |
31 | #include <asm/immap_85xx.h> | |
32 | #include <asm/immap_fsl_pci.h> | |
a30a549a | 33 | #include <spd_sdram.h> |
11c45ebd JH |
34 | #include <miiphy.h> |
35 | #include <libfdt.h> | |
36 | #include <fdt_support.h> | |
37 | ||
38 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
39 | extern void ddr_enable_ecc(unsigned int dram_size); | |
40 | #endif | |
41 | ||
42 | DECLARE_GLOBAL_DATA_PTR; | |
43 | ||
11c45ebd JH |
44 | void local_bus_init(void); |
45 | void sdram_init(void); | |
46 | long int fixed_sdram (void); | |
47 | ||
48 | int board_early_init_f (void) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | int checkboard (void) | |
54 | { | |
55 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
56 | volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); | |
347b7938 | 57 | volatile u_char *rev= (void *)CFG_BD_REV; |
11c45ebd JH |
58 | |
59 | printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", | |
347b7938 | 60 | (*rev) >> 4); |
11c45ebd JH |
61 | |
62 | /* | |
63 | * Initialize local bus. | |
64 | */ | |
65 | local_bus_init (); | |
66 | ||
67 | /* | |
68 | * Fix CPU2 errata: A core hang possible while executing a | |
69 | * msync instruction and a snoopable transaction from an I/O | |
70 | * master tagged to make quick forward progress is present. | |
71 | */ | |
72 | ecm->eebpcr |= (1 << 16); | |
73 | ||
74 | /* | |
75 | * Hack TSEC 3 and 4 IO voltages. | |
76 | */ | |
77 | gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ | |
78 | ||
79 | ecm->eedr = 0xffffffff; /* clear ecm errors */ | |
80 | ecm->eeer = 0xffffffff; /* enable ecm errors */ | |
81 | return 0; | |
82 | } | |
83 | ||
9973e3c6 | 84 | phys_size_t |
11c45ebd JH |
85 | initdram(int board_type) |
86 | { | |
87 | long dram_size = 0; | |
88 | ||
89 | puts("Initializing\n"); | |
90 | ||
91 | #if defined(CONFIG_DDR_DLL) | |
92 | { | |
93 | /* | |
94 | * Work around to stabilize DDR DLL MSYNC_IN. | |
95 | * Errata DDR9 seems to have been fixed. | |
96 | * This is now the workaround for Errata DDR11: | |
97 | * Override DLL = 1, Course Adj = 1, Tap Select = 0 | |
98 | */ | |
99 | ||
100 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
101 | ||
102 | gur->ddrdllcr = 0x81000000; | |
103 | asm("sync;isync;msync"); | |
104 | udelay(200); | |
105 | } | |
106 | #endif | |
107 | ||
108 | #if defined(CONFIG_SPD_EEPROM) | |
109 | dram_size = spd_sdram (); | |
110 | #else | |
111 | dram_size = fixed_sdram (); | |
112 | #endif | |
113 | ||
114 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
115 | /* | |
116 | * Initialize and enable DDR ECC. | |
117 | */ | |
118 | ddr_enable_ecc(dram_size); | |
119 | #endif | |
120 | /* | |
121 | * SDRAM Initialization | |
122 | */ | |
123 | sdram_init(); | |
124 | ||
125 | puts(" DDR: "); | |
126 | return dram_size; | |
127 | } | |
128 | ||
129 | /* | |
130 | * Initialize Local Bus | |
131 | */ | |
132 | void | |
133 | local_bus_init(void) | |
134 | { | |
135 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
136 | volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); | |
137 | ||
138 | uint clkdiv; | |
139 | uint lbc_hz; | |
140 | sys_info_t sysinfo; | |
141 | ||
142 | get_sys_info(&sysinfo); | |
143 | clkdiv = (lbc->lcrr & 0x0f) * 2; | |
144 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; | |
145 | ||
146 | gur->lbiuiplldcr1 = 0x00078080; | |
147 | if (clkdiv == 16) { | |
148 | gur->lbiuiplldcr0 = 0x7c0f1bf0; | |
149 | } else if (clkdiv == 8) { | |
150 | gur->lbiuiplldcr0 = 0x6c0f1bf0; | |
151 | } else if (clkdiv == 4) { | |
152 | gur->lbiuiplldcr0 = 0x5c0f1bf0; | |
153 | } | |
154 | ||
155 | lbc->lcrr |= 0x00030000; | |
156 | ||
157 | asm("sync;isync;msync"); | |
158 | ||
159 | lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ | |
160 | lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ | |
161 | } | |
162 | ||
163 | /* | |
164 | * Initialize SDRAM memory on the Local Bus. | |
165 | */ | |
166 | void | |
167 | sdram_init(void) | |
168 | { | |
169 | #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) | |
170 | ||
171 | uint idx; | |
172 | volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); | |
173 | uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; | |
174 | uint lsdmr_common; | |
175 | ||
176 | puts(" SDRAM: "); | |
177 | ||
178 | print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); | |
179 | ||
180 | /* | |
181 | * Setup SDRAM Base and Option Registers | |
182 | */ | |
183 | lbc->or3 = CFG_OR3_PRELIM; | |
184 | asm("msync"); | |
185 | ||
186 | lbc->br3 = CFG_BR3_PRELIM; | |
187 | asm("msync"); | |
188 | ||
189 | lbc->lbcr = CFG_LBC_LBCR; | |
190 | asm("msync"); | |
191 | ||
192 | ||
193 | lbc->lsrt = CFG_LBC_LSRT; | |
194 | lbc->mrtpr = CFG_LBC_MRTPR; | |
195 | asm("msync"); | |
196 | ||
197 | /* | |
198 | * MPC8548 uses "new" 15-16 style addressing. | |
199 | */ | |
200 | lsdmr_common = CFG_LBC_LSDMR_COMMON; | |
201 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; | |
202 | ||
203 | /* | |
204 | * Issue PRECHARGE ALL command. | |
205 | */ | |
206 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; | |
207 | asm("sync;msync"); | |
208 | *sdram_addr = 0xff; | |
209 | ppcDcbf((unsigned long) sdram_addr); | |
210 | udelay(100); | |
211 | ||
212 | /* | |
213 | * Issue 8 AUTO REFRESH commands. | |
214 | */ | |
215 | for (idx = 0; idx < 8; idx++) { | |
216 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; | |
217 | asm("sync;msync"); | |
218 | *sdram_addr = 0xff; | |
219 | ppcDcbf((unsigned long) sdram_addr); | |
220 | udelay(100); | |
221 | } | |
222 | ||
223 | /* | |
224 | * Issue 8 MODE-set command. | |
225 | */ | |
226 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; | |
227 | asm("sync;msync"); | |
228 | *sdram_addr = 0xff; | |
229 | ppcDcbf((unsigned long) sdram_addr); | |
230 | udelay(100); | |
231 | ||
232 | /* | |
233 | * Issue NORMAL OP command. | |
234 | */ | |
235 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; | |
236 | asm("sync;msync"); | |
237 | *sdram_addr = 0xff; | |
238 | ppcDcbf((unsigned long) sdram_addr); | |
239 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ | |
240 | ||
241 | #endif /* enable SDRAM init */ | |
242 | } | |
243 | ||
244 | #if defined(CFG_DRAM_TEST) | |
245 | int | |
246 | testdram(void) | |
247 | { | |
248 | uint *pstart = (uint *) CFG_MEMTEST_START; | |
249 | uint *pend = (uint *) CFG_MEMTEST_END; | |
250 | uint *p; | |
251 | ||
252 | printf("Testing DRAM from 0x%08x to 0x%08x\n", | |
253 | CFG_MEMTEST_START, | |
254 | CFG_MEMTEST_END); | |
255 | ||
256 | printf("DRAM test phase 1:\n"); | |
257 | for (p = pstart; p < pend; p++) | |
258 | *p = 0xaaaaaaaa; | |
259 | ||
260 | for (p = pstart; p < pend; p++) { | |
261 | if (*p != 0xaaaaaaaa) { | |
262 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
263 | return 1; | |
264 | } | |
265 | } | |
266 | ||
267 | printf("DRAM test phase 2:\n"); | |
268 | for (p = pstart; p < pend; p++) | |
269 | *p = 0x55555555; | |
270 | ||
271 | for (p = pstart; p < pend; p++) { | |
272 | if (*p != 0x55555555) { | |
273 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
274 | return 1; | |
275 | } | |
276 | } | |
277 | ||
278 | printf("DRAM test passed.\n"); | |
279 | return 0; | |
280 | } | |
281 | #endif | |
282 | ||
283 | #if !defined(CONFIG_SPD_EEPROM) | |
284 | /************************************************************************* | |
285 | * fixed_sdram init -- doesn't use serial presence detect. | |
286 | * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. | |
287 | ************************************************************************/ | |
288 | long int fixed_sdram (void) | |
289 | { | |
290 | #define CFG_DDR_CONTROL 0xc300c000 | |
291 | ||
292 | volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); | |
293 | ||
294 | ddr->cs0_bnds = 0x0000007f; | |
295 | ddr->cs1_bnds = 0x008000ff; | |
296 | ddr->cs2_bnds = 0x00000000; | |
297 | ddr->cs3_bnds = 0x00000000; | |
298 | ddr->cs0_config = 0x80010101; | |
299 | ddr->cs1_config = 0x80010101; | |
300 | ddr->cs2_config = 0x00000000; | |
301 | ddr->cs3_config = 0x00000000; | |
45239cf4 | 302 | ddr->timing_cfg_3 = 0x00000000; |
11c45ebd JH |
303 | ddr->timing_cfg_0 = 0x00220802; |
304 | ddr->timing_cfg_1 = 0x38377322; | |
305 | ddr->timing_cfg_2 = 0x0fa044C7; | |
306 | ddr->sdram_cfg = 0x4300C000; | |
307 | ddr->sdram_cfg_2 = 0x24401000; | |
308 | ddr->sdram_mode = 0x23C00542; | |
309 | ddr->sdram_mode_2 = 0x00000000; | |
310 | ddr->sdram_interval = 0x05080100; | |
311 | ddr->sdram_md_cntl = 0x00000000; | |
312 | ddr->sdram_data_init = 0x00000000; | |
53677ef1 | 313 | ddr->sdram_clk_cntl = 0x03800000; |
11c45ebd JH |
314 | asm("sync;isync;msync"); |
315 | udelay(500); | |
316 | ||
317 | #if defined (CONFIG_DDR_ECC) | |
318 | /* Enable ECC checking */ | |
319 | ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); | |
320 | #else | |
321 | ddr->sdram_cfg = CFG_DDR_CONTROL; | |
322 | #endif | |
323 | ||
324 | return CFG_SDRAM_SIZE * 1024 * 1024; | |
325 | } | |
326 | #endif | |
327 | ||
328 | #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) | |
329 | /* For some reason the Tundra PCI bridge shows up on itself as a | |
330 | * different device. Work around that by refusing to configure it. | |
331 | */ | |
332 | void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } | |
333 | ||
334 | static struct pci_config_table pci_sbc8548_config_table[] = { | |
335 | {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, | |
336 | {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, | |
337 | {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, | |
338 | mpc85xx_config_via_usbide, {0,0,0}}, | |
339 | {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, | |
340 | mpc85xx_config_via_usb, {0,0,0}}, | |
341 | {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, | |
342 | mpc85xx_config_via_usb2, {0,0,0}}, | |
343 | {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, | |
344 | mpc85xx_config_via_power, {0,0,0}}, | |
345 | {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, | |
346 | mpc85xx_config_via_ac97, {0,0,0}}, | |
347 | {}, | |
348 | }; | |
349 | ||
350 | static struct pci_controller pci1_hose = { | |
351 | config_table: pci_sbc8548_config_table}; | |
352 | #endif /* CONFIG_PCI */ | |
353 | ||
354 | #ifdef CONFIG_PCI2 | |
355 | static struct pci_controller pci2_hose; | |
356 | #endif /* CONFIG_PCI2 */ | |
357 | ||
358 | #ifdef CONFIG_PCIE1 | |
359 | static struct pci_controller pcie1_hose; | |
360 | #endif /* CONFIG_PCIE1 */ | |
361 | ||
362 | int first_free_busno=0; | |
363 | ||
364 | void | |
365 | pci_init_board(void) | |
366 | { | |
367 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
368 | ||
369 | #ifdef CONFIG_PCI1 | |
370 | { | |
371 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; | |
372 | extern void fsl_pci_init(struct pci_controller *hose); | |
373 | struct pci_controller *hose = &pci1_hose; | |
374 | struct pci_config_table *table; | |
375 | ||
376 | uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ | |
377 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ | |
378 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ | |
379 | ||
380 | uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); | |
381 | ||
382 | uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ | |
383 | ||
384 | if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { | |
385 | printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", | |
386 | (pci_32) ? 32 : 64, | |
387 | (pci_speed == 33333000) ? "33" : | |
388 | (pci_speed == 66666000) ? "66" : "unknown", | |
389 | pci_clk_sel ? "sync" : "async", | |
390 | pci_agent ? "agent" : "host", | |
391 | pci_arb ? "arbiter" : "external-arbiter" | |
392 | ); | |
393 | ||
394 | ||
395 | /* inbound */ | |
396 | pci_set_region(hose->regions + 0, | |
397 | CFG_PCI_MEMORY_BUS, | |
398 | CFG_PCI_MEMORY_PHYS, | |
399 | CFG_PCI_MEMORY_SIZE, | |
400 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
401 | ||
402 | ||
403 | /* outbound memory */ | |
404 | pci_set_region(hose->regions + 1, | |
405 | CFG_PCI1_MEM_BASE, | |
406 | CFG_PCI1_MEM_PHYS, | |
407 | CFG_PCI1_MEM_SIZE, | |
408 | PCI_REGION_MEM); | |
409 | ||
410 | /* outbound io */ | |
411 | pci_set_region(hose->regions + 2, | |
412 | CFG_PCI1_IO_BASE, | |
413 | CFG_PCI1_IO_PHYS, | |
414 | CFG_PCI1_IO_SIZE, | |
415 | PCI_REGION_IO); | |
416 | hose->region_count = 3; | |
417 | ||
418 | /* relocate config table pointers */ | |
419 | hose->config_table = \ | |
420 | (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); | |
421 | for (table = hose->config_table; table && table->vendor; table++) | |
422 | table->config_device += gd->reloc_off; | |
423 | ||
424 | hose->first_busno=first_free_busno; | |
425 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
426 | ||
427 | fsl_pci_init(hose); | |
428 | first_free_busno=hose->last_busno+1; | |
429 | printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); | |
430 | #ifdef CONFIG_PCIX_CHECK | |
431 | if (!(gur->pordevsr & PORDEVSR_PCI)) { | |
432 | /* PCI-X init */ | |
433 | if (CONFIG_SYS_CLK_FREQ < 66000000) | |
434 | printf("PCI-X will only work at 66 MHz\n"); | |
435 | ||
436 | reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
437 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
438 | pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); | |
439 | } | |
440 | #endif | |
441 | } else { | |
442 | printf (" PCI: disabled\n"); | |
443 | } | |
444 | } | |
445 | #else | |
446 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ | |
447 | #endif | |
448 | ||
449 | #ifdef CONFIG_PCI2 | |
450 | { | |
451 | uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ | |
452 | uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ | |
453 | if (pci_dual) { | |
454 | printf (" PCI2: 32 bit, 66 MHz, %s\n", | |
455 | pci2_clk_sel ? "sync" : "async"); | |
456 | } else { | |
457 | printf (" PCI2: disabled\n"); | |
458 | } | |
459 | } | |
460 | #else | |
461 | gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ | |
462 | #endif /* CONFIG_PCI2 */ | |
463 | ||
464 | #ifdef CONFIG_PCIE1 | |
465 | { | |
466 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; | |
467 | extern void fsl_pci_init(struct pci_controller *hose); | |
468 | struct pci_controller *hose = &pcie1_hose; | |
469 | int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); | |
470 | ||
471 | int pcie_configured = io_sel >= 1; | |
472 | ||
473 | if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ | |
474 | printf ("\n PCIE connected to slot as %s (base address %x)", | |
475 | pcie_ep ? "End Point" : "Root Complex", | |
476 | (uint)pci); | |
477 | ||
478 | if (pci->pme_msg_det) { | |
479 | pci->pme_msg_det = 0xffffffff; | |
480 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
481 | } | |
482 | printf ("\n"); | |
483 | ||
484 | /* inbound */ | |
485 | pci_set_region(hose->regions + 0, | |
486 | CFG_PCI_MEMORY_BUS, | |
487 | CFG_PCI_MEMORY_PHYS, | |
488 | CFG_PCI_MEMORY_SIZE, | |
489 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
490 | ||
491 | /* outbound memory */ | |
492 | pci_set_region(hose->regions + 1, | |
493 | CFG_PCIE1_MEM_BASE, | |
494 | CFG_PCIE1_MEM_PHYS, | |
495 | CFG_PCIE1_MEM_SIZE, | |
496 | PCI_REGION_MEM); | |
497 | ||
498 | /* outbound io */ | |
499 | pci_set_region(hose->regions + 2, | |
500 | CFG_PCIE1_IO_BASE, | |
501 | CFG_PCIE1_IO_PHYS, | |
502 | CFG_PCIE1_IO_SIZE, | |
503 | PCI_REGION_IO); | |
504 | ||
505 | hose->region_count = 3; | |
506 | ||
507 | hose->first_busno=first_free_busno; | |
508 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
509 | ||
510 | fsl_pci_init(hose); | |
511 | printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); | |
512 | ||
513 | first_free_busno=hose->last_busno+1; | |
514 | ||
515 | } else { | |
516 | printf (" PCIE: disabled\n"); | |
517 | } | |
518 | } | |
519 | #else | |
520 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ | |
521 | #endif | |
522 | ||
523 | } | |
524 | ||
525 | int last_stage_init(void) | |
526 | { | |
527 | return 0; | |
528 | } | |
529 | ||
530 | #if defined(CONFIG_OF_BOARD_SETUP) | |
531 | void | |
532 | ft_pci_setup(void *blob, bd_t *bd) | |
533 | { | |
534 | int node, tmp[2]; | |
11c45ebd JH |
535 | |
536 | node = fdt_path_offset(blob, "/aliases"); | |
537 | tmp[0] = 0; | |
538 | if (node >= 0) { | |
539 | #ifdef CONFIG_PCI1 | |
347b7938 | 540 | const char *path; |
11c45ebd JH |
541 | path = fdt_getprop(blob, node, "pci0", NULL); |
542 | if (path) { | |
543 | tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; | |
544 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
545 | } | |
546 | #endif | |
547 | #ifdef CONFIG_PCIE1 | |
347b7938 | 548 | const char *path; |
11c45ebd JH |
549 | path = fdt_getprop(blob, node, "pci1", NULL); |
550 | if (path) { | |
551 | tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; | |
552 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
553 | } | |
554 | #endif | |
555 | } | |
556 | } | |
557 | #endif | |
558 | ||
559 | #if defined(CONFIG_OF_BOARD_SETUP) | |
560 | void | |
561 | ft_board_setup(void *blob, bd_t *bd) | |
562 | { | |
563 | ft_cpu_setup(blob, bd); | |
564 | #ifdef CONFIG_PCI | |
565 | ft_pci_setup(blob, bd); | |
566 | #endif | |
567 | } | |
568 | #endif |