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143b518d KG |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * (C) Copyright 2000 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
143b518d KG |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/mmu.h> | |
12 | ||
13 | struct fsl_e_tlb_entry tlb_table[] = { | |
14 | /* TLB 0 - for temp stack in cache */ | |
6d0f6bcf | 15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
143b518d KG |
16 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
17 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
ded58f41 PG |
18 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
19 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
143b518d KG |
20 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
21 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
ded58f41 PG |
22 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
23 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
143b518d KG |
24 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
25 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
ded58f41 PG |
26 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
27 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
143b518d KG |
28 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
29 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
30 | ||
31 | /* | |
9b3ba24f | 32 | * TLB 0: 64M Non-cacheable, guarded |
3fd673cf | 33 | * 0xfc000000 56M unused |
9b3ba24f | 34 | * 0xff800000 8M boot FLASH |
3fd673cf PG |
35 | * .... or .... |
36 | * 0xfc000000 64M user flash | |
37 | * | |
143b518d KG |
38 | * Out of reset this entry is only 4K. |
39 | */ | |
3fd673cf | 40 | SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, |
143b518d | 41 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
9b3ba24f | 42 | 0, 0, BOOKE_PAGESZ_64M, 1), |
143b518d KG |
43 | |
44 | /* | |
fdc7eb90 PG |
45 | * TLB 1: 1G Non-cacheable, guarded |
46 | * 0x80000000 512M PCI1 MEM | |
47 | * 0xa0000000 512M PCIe MEM | |
143b518d | 48 | */ |
fdc7eb90 | 49 | SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, |
143b518d | 50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
fdc7eb90 | 51 | 0, 1, BOOKE_PAGESZ_1G, 1), |
143b518d KG |
52 | |
53 | /* | |
38dba0c2 | 54 | * TLB 2: 64M Non-cacheable, guarded |
143b518d | 55 | * 0xe0000000 1M CCSRBAR |
fdc7eb90 PG |
56 | * 0xe2000000 8M PCI1 IO |
57 | * 0xe2800000 8M PCIe IO | |
143b518d | 58 | */ |
6d0f6bcf | 59 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
143b518d | 60 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
38dba0c2 | 61 | 0, 2, BOOKE_PAGESZ_64M, 1), |
143b518d | 62 | |
7e44f2b7 | 63 | #ifdef CONFIG_SYS_LBC_SDRAM_BASE |
143b518d | 64 | /* |
38dba0c2 | 65 | * TLB 3: 64M Cacheable, non-guarded |
11d5a629 | 66 | * 0xf0000000 64M LBC SDRAM First half |
143b518d | 67 | */ |
6d0f6bcf | 68 | SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
143b518d | 69 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
38dba0c2 | 70 | 0, 3, BOOKE_PAGESZ_64M, 1), |
143b518d KG |
71 | |
72 | /* | |
38dba0c2 | 73 | * TLB 4: 64M Cacheable, non-guarded |
11d5a629 PG |
74 | * 0xf4000000 64M LBC SDRAM Second half |
75 | */ | |
76 | SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, | |
77 | CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, | |
78 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
38dba0c2 | 79 | 0, 4, BOOKE_PAGESZ_64M, 1), |
7e44f2b7 | 80 | #endif |
11d5a629 PG |
81 | |
82 | /* | |
38dba0c2 | 83 | * TLB 5: 16M Cacheable, non-guarded |
143b518d KG |
84 | * 0xf8000000 1M 7-segment LED display |
85 | * 0xf8100000 1M User switches | |
86 | * 0xf8300000 1M Board revision | |
87 | * 0xf8b00000 1M EEPROM | |
88 | */ | |
6d0f6bcf | 89 | SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, |
143b518d | 90 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
38dba0c2 | 91 | 0, 5, BOOKE_PAGESZ_16M, 1), |
9b3ba24f | 92 | |
f0aec4ea | 93 | #ifndef CONFIG_SYS_ALT_BOOT |
9b3ba24f | 94 | /* |
3fd673cf PG |
95 | * TLB 6: 64M Non-cacheable, guarded |
96 | * 0xec000000 64M 64MB user FLASH | |
9b3ba24f PG |
97 | */ |
98 | SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, | |
99 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
3fd673cf | 100 | 0, 6, BOOKE_PAGESZ_64M, 1), |
f0aec4ea PG |
101 | #else |
102 | /* | |
103 | * TLB 6: 4M Non-cacheable, guarded | |
104 | * 0xef800000 4M 1st 1/2 8MB soldered FLASH | |
105 | */ | |
106 | SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, | |
107 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
108 | 0, 6, BOOKE_PAGESZ_4M, 1), | |
109 | ||
110 | /* | |
111 | * TLB 7: 4M Non-cacheable, guarded | |
112 | * 0xefc00000 4M 2nd half 8MB soldered FLASH | |
113 | */ | |
114 | SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, | |
115 | CONFIG_SYS_ALT_FLASH + 0x400000, | |
116 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
117 | 0, 7, BOOKE_PAGESZ_4M, 1), | |
118 | #endif | |
9b3ba24f | 119 | |
143b518d KG |
120 | }; |
121 | ||
122 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |