[people/ms/u-boot.git] / board / sbc8560 / sbc8560.c

/*
 * (C) Copyright 2003,Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
 * Added support for Wind River SBC8560 board
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>

long int fixed_sdram (void);

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
	/* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};

int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);

    pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
	return 0;
}

void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
#endif
	/* reset Giga bit Ethernet port if needed here */

	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr[0] &= ~0x20;
	udelay(2);
	bcsr[0] |= 0x20;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr[0] &= ~0x10;
	udelay(2);
	bcsr[0] |= 0x10;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1 ETHERNET", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}

int checkboard (void)
{
	sys_info_t sysinfo;

	get_sys_info (&sysinfo);

#ifdef CONFIG_SBC8560
	printf ("Board: Wind River SBC8560 Board\n");
#else
	printf ("Board: Wind River SBC8540 Board\n");
#endif
	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
		|| (CFG_LBC_LCRR & 0x0f) == 8) {
		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
	} else {
		printf("\tLBC: unknown\n");
	}
	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	return (0);
}


phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
	sys_info_t sysinfo;
	uint temp_lbcdll = 0;
#endif
#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
	uint temp_ddrdll = 0;

	/* Work around to stabilize DDR DLL */
	temp_ddrdll = gur->ddrdllcr;
	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if 0
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
	get_sys_info(&sysinfo);
	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
	} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
		udelay(200);
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
		asm("sync;isync;msync");
	}
	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
	lbc->br2 = CFG_BR2_PRELIM;
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->lsdmr = CFG_LBC_LSDMR_1;
	asm("sync");
	(unsigned int) * (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_2;
	asm("sync");
	(unsigned int) * (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_3;
	asm("sync");
	(unsigned int) * (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	(unsigned int) * (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_5;
	asm("sync");
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("sync");
#endif
#endif

#if defined(CONFIG_DDR_ECC)
	{
		/* Initialize all of memory for ECC, then
		 * enable errors */
		uint *p = 0;
		uint i = 0;
		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
		dma_init();
		for (*p = 0; p < (uint *)(8 * 1024); p++) {
			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
			*p = (unsigned int)0xdeadbeef;
			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
		}

		/* 8K */
		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
		/* 16K */
		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
		/* 32K */
		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
		/* 64K */
		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
		/* 128k */
		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
		/* 256k */
		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
		/* 512k */
		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
		/* 1M */
		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
		/* 2M */
		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
		/* 4M */
		dma_xfer((uint *)0x400000,0x400000,(uint *)0);

		for (i = 1; i < dram_size / 0x800000; i++) {
			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
		}

		/* Enable errors for ECC */
		ddr->err_disable = 0x00000000;
		asm("sync;isync;msync");
	}
#endif

	return dram_size;
}


#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{

#define CFG_DDR_CONTROL 0xc2000000

  #ifndef CFG_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds		= 0x00000007;
	ddr->cs1_bnds		= 0x0010001f;
	ddr->cs2_bnds		= 0x00000000;
	ddr->cs3_bnds		= 0x00000000;
	ddr->cs0_config		= 0x80000102;
	ddr->cs1_config		= 0x80000102;
	ddr->cs2_config		= 0x00000000;
	ddr->cs3_config		= 0x00000000;
	ddr->timing_cfg_1	= 0x37334321;
	ddr->timing_cfg_2	= 0x00000800;
	ddr->sdram_cfg		= 0x42000000;
	ddr->sdram_mode		= 0x00000022;
	ddr->sdram_interval	= 0x05200100;
	ddr->err_sbe		= 0x00ff0000;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CFG_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */
Commit	Line	Data
8b07a110 WD	1	/*
	2	* (C) Copyright 2003,Motorola Inc.
	3	* Xianghua Xiao, (X.Xiao@motorola.com)
	4	*
	5	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	6	*
	7	* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
	8	* Added support for Wind River SBC8560 board
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29
8b07a110 WD	30	#include <common.h>
	31	#include <asm/processor.h>
	32	#include <asm/immap_85xx.h>
	33	#include <ioports.h>
a30a549a	34	#include <spd_sdram.h>
8b07a110 WD	35	#include <miiphy.h>
	36
	37	long int fixed_sdram (void);
	38
	39	/*
	40	* I/O Port configuration table
	41	*
	42	* if conf is 1, then that port pin will be configured at boot time
	43	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	44	*/
	45
	46	const iop_conf_t iop_conf_tab[4][32] = {
	47
	48	/* Port A configuration */
	49	{ /* conf ppar psor pdir podr pdat */
	50	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	51	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	52	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	53	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	54	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	55	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	56	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	57	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	58	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	59	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
	60	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
	61	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
	62	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
	63	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
	64	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
	65	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
	66	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
	67	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
	68	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	69	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	70	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	71	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	72	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	73	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	74	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	75	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	76	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	77	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	78	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	79	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	80	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FREERUN */
	81	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	82	},
	83
	84	/* Port B configuration */
	85	{ /* conf ppar psor pdir podr pdat */
	86	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	87	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	88	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	89	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	90	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	91	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	92	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	93	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	94	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	95	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	96	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	97	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	98	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
99	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
100	/* PB17 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
101	/* PB16 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
102	/* PB15 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
103	/* PB14 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
104	/* PB13 / { 0, 1, 0, 0, 0, 0 }, / FCC3:COL */
105	/* PB12 / { 0, 1, 0, 0, 0, 0 }, / FCC3:CRS */
106	/* PB11 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
107	/* PB10 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
108	/* PB9 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
109	/* PB8 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
110	/* PB7 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
111	/* PB6 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
112	/* PB5 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
113	/* PB4 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
114	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
115	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
116	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
117	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
118	},
119
120	/* Port C */
121	{ /* conf ppar psor pdir podr pdat */
122	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
123	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
124	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
125	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
126	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
127	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
128	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
129	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
130	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
131	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
132	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
133	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
134	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
135	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
136	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
137	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
138	/* PC15 / { 1, 1, 0, 0, 0, 0 }, / PC15 */
139	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
140	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
141	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
142	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
143	/* PC10 / { 1, 0, 0, 1, 0, 0 }, / FETHMDC */
144	/* PC9 / { 1, 0, 0, 0, 0, 0 }, / FETHMDIO */
145	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
146	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
147	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
148	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
149	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
150	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
151	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
152	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
153	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
154	},
155
156	/* Port D */
157	{ /* conf ppar psor pdir podr pdat */
158	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
159	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
160	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 RTS */
161	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / SCC2 RxD */
162	/* PD27 / { 1, 1, 1, 1, 0, 0 }, / SCC2 TxD */
163	/* PD26 / { 1, 1, 0, 1, 0, 0 }, / SCC2 RTS */
164	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
165	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
166	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
167	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
168	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
169	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
170	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
171	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
172	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
173	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
174	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
175	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
176	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
177	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
178	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
179	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
180	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
181	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
182	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
183	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
184	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
185	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
186	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
187	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
188	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
189	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
190	}
191	};
192
193	int board_early_init_f (void)
194	{
195	#if defined(CONFIG_PCI)
04db4008	196	volatile ccsr_pcix_t pci = (void )(CFG_MPC85xx_PCIX_ADDR);
8b07a110 WD	197
	198	pci->peer &= 0xfffffffdf; /* disable master abort */
	199	#endif
	200	return 0;
	201	}
	202
	203	void reset_phy (void)
	204	{
	205	#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	206	volatile unsigned char bcsr = (unsigned char ) CFG_BCSR;
	207	#endif
	208	/* reset Giga bit Ethernet port if needed here */
	209
	210	/* reset the CPM FEC port */
	211	#if (CONFIG_ETHER_INDEX == 2)
	212	bcsr[0] &= ~0x20;
	213	udelay(2);
	214	bcsr[0] \|= 0x20;
	215	udelay(1000);
	216	#elif (CONFIG_ETHER_INDEX == 3)
	217	bcsr[0] &= ~0x10;
	218	udelay(2);
	219	bcsr[0] \|= 0x10;
	220	udelay(1000);
	221	#endif
	222	#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
63ff004c MB	223	/* reset PHY */
	224	miiphy_reset("FCC1 ETHERNET", 0x0);
	225
	226	/* change PHY address to 0x02 */
	227	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
	228
	229	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
	230	PHY_BMCR_AUTON \| PHY_BMCR_RST_NEG);
8b07a110 WD	231	#endif /* CONFIG_MII */
	232	}
	233
	234	int checkboard (void)
	235	{
	236	sys_info_t sysinfo;
	237
	238	get_sys_info (&sysinfo);
	239
c15f3120	240	#ifdef CONFIG_SBC8560
8b07a110	241	printf ("Board: Wind River SBC8560 Board\n");
c15f3120 WD	242	#else
	243	printf ("Board: Wind River SBC8540 Board\n");
	244	#endif
8b07a110 WD	245	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	246	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	247	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
	248	if((CFG_LBC_LCRR & 0x0f) == 2 \|\| (CFG_LBC_LCRR & 0x0f) == 4 \
	249	\|\| (CFG_LBC_LCRR & 0x0f) == 8) {
	250	printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
	251	} else {
	252	printf("\tLBC: unknown\n");
	253	}
	254	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
	255	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	256	return (0);
	257	}
	258
	259
9973e3c6	260	phys_size_t initdram (int board_type)
8b07a110 WD	261	{
8b07a110 WD	262	long dram_size = 0;
a30a549a	263
281e00a3	264	#if 0
8b07a110	265	#if !defined(CONFIG_RAM_AS_FLASH)
04db4008	266	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
8b07a110 WD	267	sys_info_t sysinfo;
	268	uint temp_lbcdll = 0;
	269	#endif
281e00a3	270	#endif /* 0 */
8b07a110	271	#if !defined(CONFIG_RAM_AS_FLASH) \|\| defined(CONFIG_DDR_DLL)
f59b55a5	272	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
8b07a110 WD	273	#endif
	274	#if defined(CONFIG_DDR_DLL)
	275	uint temp_ddrdll = 0;
	276
	277	/* Work around to stabilize DDR DLL */
	278	temp_ddrdll = gur->ddrdllcr;
	279	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
	280	asm("sync;isync;msync");
	281	#endif
	282
	283	#if defined(CONFIG_SPD_EEPROM)
	284	dram_size = spd_sdram ();
	285	#else
	286	dram_size = fixed_sdram ();
	287	#endif
	288
281e00a3	289	#if 0
8b07a110 WD	290	#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
	291	get_sys_info(&sysinfo);
	292	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
	293	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
	294	lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)\| 0x80000000;
	295	} else {
	296	#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
	297	lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
	298	#endif
	299	lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
	300	udelay(200);
	301	temp_lbcdll = gur->lbcdllcr;
	302	gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) \| 0x80000000;
	303	asm("sync;isync;msync");
	304	}
	305	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
	306	lbc->br2 = CFG_BR2_PRELIM;
	307	lbc->lbcr = CFG_LBC_LBCR;
	308	lbc->lsdmr = CFG_LBC_LSDMR_1;
	309	asm("sync");
	310	(unsigned int) * (ulong *)0 = 0x000000ff;
	311	lbc->lsdmr = CFG_LBC_LSDMR_2;
	312	asm("sync");
	313	(unsigned int) * (ulong *)0 = 0x000000ff;
	314	lbc->lsdmr = CFG_LBC_LSDMR_3;
	315	asm("sync");
	316	(unsigned int) * (ulong *)0 = 0x000000ff;
	317	lbc->lsdmr = CFG_LBC_LSDMR_4;
	318	asm("sync");
	319	(unsigned int) * (ulong *)0 = 0x000000ff;
	320	lbc->lsdmr = CFG_LBC_LSDMR_5;
	321	asm("sync");
	322	lbc->lsrt = CFG_LBC_LSRT;
	323	asm("sync");
	324	lbc->mrtpr = CFG_LBC_MRTPR;
	325	asm("sync");
	326	#endif
	327	#endif
	328
	329	#if defined(CONFIG_DDR_ECC)
	330	{
	331	/* Initialize all of memory for ECC, then
	332	* enable errors */
	333	uint *p = 0;
	334	uint i = 0;
04db4008	335	volatile ccsr_ddr_t ddr= (void )(CFG_MPC85xx_DDR_ADDR);
8b07a110 WD	336	dma_init();
	337	for (p = 0; p < (uint )(8 * 1024); p++) {
	338	if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
	339	*p = (unsigned int)0xdeadbeef;
	340	if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
	341	}
	342
	343	/* 8K */
	344	dma_xfer((uint )0x2000,0x2000,(uint )0);
	345	/* 16K */
	346	dma_xfer((uint )0x4000,0x4000,(uint )0);
	347	/* 32K */
	348	dma_xfer((uint )0x8000,0x8000,(uint )0);
	349	/* 64K */
	350	dma_xfer((uint )0x10000,0x10000,(uint )0);
	351	/* 128k */
	352	dma_xfer((uint )0x20000,0x20000,(uint )0);
	353	/* 256k */
	354	dma_xfer((uint )0x40000,0x40000,(uint )0);
	355	/* 512k */
	356	dma_xfer((uint )0x80000,0x80000,(uint )0);
	357	/* 1M */
	358	dma_xfer((uint )0x100000,0x100000,(uint )0);
	359	/* 2M */
	360	dma_xfer((uint )0x200000,0x200000,(uint )0);
	361	/* 4M */
	362	dma_xfer((uint )0x400000,0x400000,(uint )0);
	363
	364	for (i = 1; i < dram_size / 0x800000; i++) {
	365	dma_xfer((uint )(0x800000i),0x800000,(uint *)0);
	366	}
	367
	368	/* Enable errors for ECC */
	369	ddr->err_disable = 0x00000000;
	370	asm("sync;isync;msync");
	371	}
	372	#endif
	373
	374	return dram_size;
	375	}
	376
	377
	378	#if defined(CFG_DRAM_TEST)
	379	int testdram (void)
	380	{
	381	uint pstart = (uint ) CFG_MEMTEST_START;
	382	uint pend = (uint ) CFG_MEMTEST_END;
	383	uint *p;
	384
	385	printf("SDRAM test phase 1:\n");
	386	for (p = pstart; p < pend; p++)
	387	*p = 0xaaaaaaaa;
	388
	389	for (p = pstart; p < pend; p++) {
	390	if (*p != 0xaaaaaaaa) {
	391	printf ("SDRAM test fails at: %08x\n", (uint) p);
	392	return 1;
	393	}
	394	}
	395
	396	printf("SDRAM test phase 2:\n");
	397	for (p = pstart; p < pend; p++)
	398	*p = 0x55555555;
	399
400	for (p = pstart; p < pend; p++) {
401	if (*p != 0x55555555) {
402	printf ("SDRAM test fails at: %08x\n", (uint) p);
403	return 1;
404	}
405	}
406
407	printf("SDRAM test passed.\n");
408	return 0;
409	}
410	#endif
411
412	#if !defined(CONFIG_SPD_EEPROM)
413	/*************************************************************************
414	* fixed sdram init -- doesn't use serial presence detect.
415	************************************************************************/
416	long int fixed_sdram (void)
417	{
418
419	#define CFG_DDR_CONTROL 0xc2000000
420
421	#ifndef CFG_RAMBOOT
04db4008	422	volatile ccsr_ddr_t ddr= (void )(CFG_MPC85xx_DDR_ADDR);
8b07a110 WD	423
	424	ddr->cs0_bnds = 0x00000007;
	425	ddr->cs1_bnds = 0x0010001f;
	426	ddr->cs2_bnds = 0x00000000;
	427	ddr->cs3_bnds = 0x00000000;
	428	ddr->cs0_config = 0x80000102;
	429	ddr->cs1_config = 0x80000102;
	430	ddr->cs2_config = 0x00000000;
	431	ddr->cs3_config = 0x00000000;
	432	ddr->timing_cfg_1 = 0x37334321;
	433	ddr->timing_cfg_2 = 0x00000800;
	434	ddr->sdram_cfg = 0x42000000;
	435	ddr->sdram_mode = 0x00000022;
	436	ddr->sdram_interval = 0x05200100;
	437	ddr->err_sbe = 0x00ff0000;
	438	#if defined (CONFIG_DDR_ECC)
	439	ddr->err_disable = 0x0000000D;
	440	#endif
	441	asm("sync;isync;msync");
	442	udelay(500);
	443	#if defined (CONFIG_DDR_ECC)
	444	/* Enable ECC checking */
	445	ddr->sdram_cfg = (CFG_DDR_CONTROL \| 0x20000000);
	446	#else
	447	ddr->sdram_cfg = CFG_DDR_CONTROL;
	448	#endif
	449	asm("sync; isync; msync");
	450	udelay(500);
	451	#endif
	452	return CFG_SDRAM_SIZE * 1024 * 1024;
	453	}
	454	#endif /* !defined(CONFIG_SPD_EEPROM) */