[people/ms/u-boot.git] / board / sbc8641d / sbc8641d.c

/*
 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
 * Copyright 2007 Embedded Specialties, Inc.
 * Joe Hamman joe.hamman@embeddedspecialties.com
 *
 * Copyright 2004 Freescale Semiconductor.
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>

long int fixed_sdram (void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	puts ("Board: Wind River SBC8641D\n");

	return 0;
}

phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram ();
#endif

	puts ("    DDR: ");
	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	puts ("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
	asm ("sync; isync");

	udelay (500);
	ddr = &immap->im_ddr2;

	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
	asm ("sync; isync");

	udelay (500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif				/* !defined(CONFIG_SPD_EEPROM) */

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
	{}
};
#endif

static struct pci_controller pcie1_hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif	/* CONFIG_PCIE2 */

int first_free_busno = 0;

void pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;

#ifdef CONFIG_PCIE1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	struct pci_region *r = hose->regions;
#ifdef DEBUG
	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
		>> MPC8641_PORBMSR_HA_SHIFT;
	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
			      pci->pme_msg_det);
		}
		debug("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BUS,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_IO_BUS,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno=hose->last_busno+1;
		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

	} else {
		puts("PCI-EXPRESS 1: Disabled\n");
	}
}
#else
	puts("PCI-EXPRESS1: Disabled\n");
#endif /* CONFIG_PCIE1 */

#ifdef CONFIG_PCIE2
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	struct pci_controller *hose = &pcie2_hose;
	struct pci_region *r = hose->regions;

	/* outbound memory */
	pci_set_region(r++,
		       CONFIG_SYS_PCIE2_MEM_BUS,
		       CONFIG_SYS_PCIE2_MEM_PHYS,
		       CONFIG_SYS_PCIE2_MEM_SIZE,
		       PCI_REGION_MEM);

	/* outbound io */
	pci_set_region(r++,
		       CONFIG_SYS_PCIE2_IO_BUS,
		       CONFIG_SYS_PCIE2_IO_PHYS,
		       CONFIG_SYS_PCIE2_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = r - hose->regions;

	hose->first_busno=first_free_busno;

	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

	first_free_busno=hose->last_busno+1;
	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
		hose->first_busno,hose->last_busno);
}
#else
	puts("PCI-EXPRESS 2: Disabled\n");
#endif /* CONFIG_PCIE2 */

}


#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup (void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;
}
#endif

void sbc8641d_reset_board (void)
{
	puts ("Resetting board....\n");
}

/*
 * get_board_sys_clk
 *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 */

unsigned long get_board_sys_clk (ulong dummy)
{
	int i;
	ulong val = 0;

	i = 5;
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33000000;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66000000;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 134000000;
		break;
	case 7:
		val = 166000000;
		break;
	}

	return val;
}

void board_reset(void)
{
#ifdef CONFIG_SYS_RESET_ADDRESS
	ulong addr = CONFIG_SYS_RESET_ADDRESS;

	/* flush and disable I/D cache */
	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 4");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 5");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");

	/*
	 * SRR0 has system reset vector, SRR1 has default MSR value
	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	 */
	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
	__asm__ __volatile__ ("mtspr	27, 4");
	__asm__ __volatile__ ("rfi");
#endif
}

#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
8ac27327 JH	1	/*
	2	* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
	3	* Copyright 2007 Embedded Specialties, Inc.
	4	* Joe Hamman joe.hamman@embeddedspecialties.com
	5	*
	6	* Copyright 2004 Freescale Semiconductor.
	7	* Jeff Brown
	8	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	9	*
	10	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#include <common.h>
	32	#include <command.h>
	33	#include <pci.h>
	34	#include <asm/processor.h>
	35	#include <asm/immap_86xx.h>
c8514622	36	#include <asm/fsl_pci.h>
9bd4e591	37	#include <asm/fsl_ddr_sdram.h>
13f5433f JL	38	#include <libfdt.h>
13f5433f JL	39	#include <fdt_support.h>
8ac27327	40
8ac27327 JH	41	long int fixed_sdram (void);
	42
	43	int board_early_init_f (void)
	44	{
	45	return 0;
	46	}
	47
	48	int checkboard (void)
	49	{
	50	puts ("Board: Wind River SBC8641D\n");
	51
8ac27327 JH	52	return 0;
	53	}
	54
9973e3c6	55	phys_size_t initdram (int board_type)
8ac27327 JH	56	{
	57	long dram_size = 0;
	58
	59	#if defined(CONFIG_SPD_EEPROM)
9bd4e591	60	dram_size = fsl_ddr_sdram();
8ac27327 JH	61	#else
	62	dram_size = fixed_sdram ();
	63	#endif
	64
8ac27327 JH	65	puts (" DDR: ");
	66	return dram_size;
	67	}
	68
6d0f6bcf	69	#if defined(CONFIG_SYS_DRAM_TEST)
8ac27327 JH	70	int testdram (void)
8ac27327 JH	71	{
6d0f6bcf JCPV	72	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	73	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
8ac27327 JH	74	uint *p;
	75
	76	puts ("SDRAM test phase 1:\n");
	77	for (p = pstart; p < pend; p++)
	78	*p = 0xaaaaaaaa;
	79
	80	for (p = pstart; p < pend; p++) {
	81	if (*p != 0xaaaaaaaa) {
	82	printf ("SDRAM test fails at: %08x\n", (uint) p);
	83	return 1;
	84	}
	85	}
	86
	87	puts ("SDRAM test phase 2:\n");
	88	for (p = pstart; p < pend; p++)
	89	*p = 0x55555555;
	90
	91	for (p = pstart; p < pend; p++) {
	92	if (*p != 0x55555555) {
	93	printf ("SDRAM test fails at: %08x\n", (uint) p);
	94	return 1;
	95	}
	96	}
	97
	98	puts ("SDRAM test passed.\n");
	99	return 0;
	100	}
	101	#endif
	102
	103	#if !defined(CONFIG_SPD_EEPROM)
	104	/*
	105	* Fixed sdram init -- doesn't use serial presence detect.
	106	*/
	107	long int fixed_sdram (void)
	108	{
6d0f6bcf JCPV	109	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	110	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
8ac27327 JH	111	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
8ac27327 JH	112
6d0f6bcf JCPV	113	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	114	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	115	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	116	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	117	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	118	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	119	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	120	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	121	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	122	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	123	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	124	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
e7ee23ec	125	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
6d0f6bcf	126	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
e7ee23ec	127	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
6d0f6bcf JCPV	128	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	129	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
	130	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	131	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	132	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
8ac27327 JH	133
	134	asm ("sync;isync");
	135
	136	udelay (500);
	137
e7ee23ec	138	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
8ac27327 JH	139	asm ("sync; isync");
	140
	141	udelay (500);
	142	ddr = &immap->im_ddr2;
	143
6d0f6bcf JCPV	144	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	145	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	146	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	147	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	148	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	149	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	150	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	151	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	152	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	153	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	154	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	155	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
e7ee23ec	156	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
6d0f6bcf	157	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
e7ee23ec	158	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
6d0f6bcf JCPV	159	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
	160	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
	161	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	162	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	163	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
8ac27327 JH	164
	165	asm ("sync;isync");
	166
	167	udelay (500);
	168
e7ee23ec	169	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
8ac27327 JH	170	asm ("sync; isync");
	171
	172	udelay (500);
	173	#endif
6d0f6bcf	174	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
8ac27327 JH	175	}
	176	#endif /* !defined(CONFIG_SPD_EEPROM) */
	177
	178	#if defined(CONFIG_PCI)
	179	/*
	180	* Initialize PCI Devices, report devices found.
	181	*/
	182
	183	#ifndef CONFIG_PCI_PNP
	184	static struct pci_config_table pci_fsl86xxads_config_table[] = {
	185	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	186	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	187	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	188	PCI_ENET0_MEMADDR,
	189	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER}},
	190	{}
	191	};
	192	#endif
	193
46f3e385	194	static struct pci_controller pcie1_hose = {
8ac27327	195	#ifndef CONFIG_PCI_PNP
cca34967	196	config_table:pci_mpc86xxcts_config_table
8ac27327 JH	197	#endif
8ac27327 JH	198	};
cca34967	199	#endif /* CONFIG_PCI */
8ac27327	200
46f3e385 KG	201	#ifdef CONFIG_PCIE2
	202	static struct pci_controller pcie2_hose;
	203	#endif /* CONFIG_PCIE2 */
8ac27327	204
cca34967 JH	205	int first_free_busno = 0;
	206
	207	void pci_init_board(void)
8ac27327	208	{
6d0f6bcf	209	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
cca34967 JH	210	volatile ccsr_gur_t *gur = &immap->im_gur;
cca34967 JH	211	uint devdisr = gur->devdisr;
33fa5c0b JL	212	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
33fa5c0b JL	213	>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
cca34967	214
46f3e385	215	#ifdef CONFIG_PCIE1
cca34967	216	{
dd2cda3d	217	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
46f3e385	218	struct pci_controller *hose = &pcie1_hose;
c2083e0e	219	struct pci_region *r = hose->regions;
cca34967	220	#ifdef DEBUG
33fa5c0b JL	221	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
33fa5c0b JL	222	>> MPC8641_PORBMSR_HA_SHIFT;
cca34967 JH	223	uint pex1_agent = (host1_agent == 0) \|\| (host1_agent == 1);
	224	#endif
	225	if ((io_sel == 2 \|\| io_sel == 3 \|\| io_sel == 5
	226	\|\| io_sel == 6 \|\| io_sel == 7 \|\| io_sel == 0xF)
	227	&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
	228	debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
	229	debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
	230	if (pci->pme_msg_det) {
	231	pci->pme_msg_det = 0xffffffff;
	232	debug(" with errors. Clearing. Now 0x%08x",
	233	pci->pme_msg_det);
	234	}
	235	debug("\n");
	236
cca34967	237	/* outbound memory */
c2083e0e	238	pci_set_region(r++,
46f3e385 KG	239	CONFIG_SYS_PCIE1_MEM_BUS,
	240	CONFIG_SYS_PCIE1_MEM_PHYS,
	241	CONFIG_SYS_PCIE1_MEM_SIZE,
cca34967 JH	242	PCI_REGION_MEM);
	243
	244	/* outbound io */
c2083e0e	245	pci_set_region(r++,
46f3e385 KG	246	CONFIG_SYS_PCIE1_IO_BUS,
	247	CONFIG_SYS_PCIE1_IO_PHYS,
	248	CONFIG_SYS_PCIE1_IO_SIZE,
cca34967 JH	249	PCI_REGION_IO);
cca34967 JH	250
c2083e0e	251	hose->region_count = r - hose->regions;
cca34967 JH	252
cca34967 JH	253	hose->first_busno=first_free_busno;
cca34967	254
fb3143b3	255	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
cca34967 JH	256
	257	first_free_busno=hose->last_busno+1;
	258	printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
	259	hose->first_busno,hose->last_busno);
	260
	261	} else {
	262	puts("PCI-EXPRESS 1: Disabled\n");
	263	}
	264	}
	265	#else
	266	puts("PCI-EXPRESS1: Disabled\n");
46f3e385	267	#endif /* CONFIG_PCIE1 */
cca34967	268
46f3e385	269	#ifdef CONFIG_PCIE2
cca34967	270	{
dd2cda3d	271	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
46f3e385	272	struct pci_controller *hose = &pcie2_hose;
c2083e0e	273	struct pci_region *r = hose->regions;
cca34967	274
cca34967	275	/* outbound memory */
c2083e0e	276	pci_set_region(r++,
46f3e385 KG	277	CONFIG_SYS_PCIE2_MEM_BUS,
	278	CONFIG_SYS_PCIE2_MEM_PHYS,
	279	CONFIG_SYS_PCIE2_MEM_SIZE,
cca34967 JH	280	PCI_REGION_MEM);
	281
	282	/* outbound io */
c2083e0e	283	pci_set_region(r++,
46f3e385 KG	284	CONFIG_SYS_PCIE2_IO_BUS,
	285	CONFIG_SYS_PCIE2_IO_PHYS,
	286	CONFIG_SYS_PCIE2_IO_SIZE,
cca34967 JH	287	PCI_REGION_IO);
cca34967 JH	288
c2083e0e	289	hose->region_count = r - hose->regions;
cca34967 JH	290
cca34967 JH	291	hose->first_busno=first_free_busno;
cca34967	292
fb3143b3	293	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
cca34967 JH	294
	295	first_free_busno=hose->last_busno+1;
	296	printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
	297	hose->first_busno,hose->last_busno);
	298	}
	299	#else
	300	puts("PCI-EXPRESS 2: Disabled\n");
46f3e385	301	#endif /* CONFIG_PCIE2 */
8ac27327	302
8ac27327 JH	303	}
8ac27327 JH	304
13f5433f JL	305
13f5433f JL	306	#if defined(CONFIG_OF_BOARD_SETUP)
c2083e0e	307	void ft_board_setup (void blob, bd_t bd)
8ac27327	308	{
13f5433f	309	ft_cpu_setup(blob, bd);
8ac27327	310
6525d51f	311	FT_FSL_PCI_SETUP;
8ac27327 JH	312	}
	313	#endif
	314
	315	void sbc8641d_reset_board (void)
	316	{
	317	puts ("Resetting board....\n");
	318	}
	319
	320	/*
	321	* get_board_sys_clk
	322	* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
	323	*/
	324
	325	unsigned long get_board_sys_clk (ulong dummy)
	326	{
	327	int i;
	328	ulong val = 0;
	329
	330	i = 5;
	331	i &= 0x07;
	332
	333	switch (i) {
	334	case 0:
	335	val = 33000000;
	336	break;
	337	case 1:
	338	val = 40000000;
	339	break;
	340	case 2:
	341	val = 50000000;
	342	break;
	343	case 3:
	344	val = 66000000;
	345	break;
	346	case 4:
	347	val = 83000000;
	348	break;
	349	case 5:
	350	val = 100000000;
	351	break;
	352	case 6:
	353	val = 134000000;
	354	break;
	355	case 7:
	356	val = 166000000;
	357	break;
	358	}
	359
	360	return val;
	361	}
4ef630df PT	362
	363	void board_reset(void)
	364	{
	365	#ifdef CONFIG_SYS_RESET_ADDRESS
	366	ulong addr = CONFIG_SYS_RESET_ADDRESS;
	367
	368	/* flush and disable I/D cache */
	369	__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
	370	__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
	371	__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
	372	__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
	373	__asm__ __volatile__ ("sync");
	374	__asm__ __volatile__ ("mtspr 1008, 4");
	375	__asm__ __volatile__ ("isync");
	376	__asm__ __volatile__ ("sync");
	377	__asm__ __volatile__ ("mtspr 1008, 5");
	378	__asm__ __volatile__ ("isync");
	379	__asm__ __volatile__ ("sync");
	380
	381	/*
	382	* SRR0 has system reset vector, SRR1 has default MSR value
	383	* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	384	*/
	385	__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
	386	__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
	387	__asm__ __volatile__ ("mtspr 27, 4");
	388	__asm__ __volatile__ ("rfi");
	389	#endif
	390	}
f6ef8b7a	391
7649a590	392	#ifdef CONFIG_MP
f6ef8b7a BB	393	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	394
	395	void board_lmb_reserve(struct lmb *lmb)
	396	{
	397	cpu_mp_lmb_reserve(lmb);
	398	}
	399	#endif