[people/ms/u-boot.git] / board / sbc8641d / sbc8641d.c

/*
 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
 * Copyright 2007 Embedded Specialties, Inc.
 * Joe Hamman joe.hamman@embeddedspecialties.com
 *
 * Copyright 2004 Freescale Semiconductor.
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>

long int fixed_sdram (void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	puts ("Board: Wind River SBC8641D\n");

	return 0;
}

phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram ();
#endif

	puts ("    DDR: ");
	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	puts ("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
	asm ("sync; isync");

	udelay (500);
	ddr = &immap->im_ddr2;

	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
	asm ("sync; isync");

	udelay (500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif				/* !defined(CONFIG_SPD_EEPROM) */

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
	{}
};
#endif

static struct pci_controller pcie1_hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif	/* CONFIG_PCIE2 */

int first_free_busno = 0;

void pci_init_board(void)
{
	struct fsl_pci_info pci_info[2];
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = in_be32(&gur->devdisr);
	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
	int pcie_ep;
	int num = 0;

#ifdef CONFIG_PCIE1
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
		printf("    PCIE1 connected as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		puts("    PCIE1: disabled\n");
	}
#else
	puts("    PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */

#ifdef CONFIG_PCIE2

	SET_STD_PCIE_INFO(pci_info[num], 2);
	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
	printf("    PCIE2 connected as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);
	first_free_busno = fsl_pci_init_port(&pci_info[num++],
				&pcie2_hose, first_free_busno);
#else
	puts("    PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup (void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;
}
#endif

void sbc8641d_reset_board (void)
{
	puts ("Resetting board....\n");
}

/*
 * get_board_sys_clk
 *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 */

unsigned long get_board_sys_clk (ulong dummy)
{
	int i;
	ulong val = 0;

	i = 5;
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33000000;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66000000;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 134000000;
		break;
	case 7:
		val = 166000000;
		break;
	}

	return val;
}

void board_reset(void)
{
#ifdef CONFIG_SYS_RESET_ADDRESS
	ulong addr = CONFIG_SYS_RESET_ADDRESS;

	/* flush and disable I/D cache */
	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 4");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 5");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");

	/*
	 * SRR0 has system reset vector, SRR1 has default MSR value
	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	 */
	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
	__asm__ __volatile__ ("mtspr	27, 4");
	__asm__ __volatile__ ("rfi");
#endif
}

#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
8ac27327 JH	1	/*
	2	* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
	3	* Copyright 2007 Embedded Specialties, Inc.
	4	* Joe Hamman joe.hamman@embeddedspecialties.com
	5	*
	6	* Copyright 2004 Freescale Semiconductor.
	7	* Jeff Brown
	8	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	9	*
	10	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#include <common.h>
	32	#include <command.h>
	33	#include <pci.h>
	34	#include <asm/processor.h>
	35	#include <asm/immap_86xx.h>
c8514622	36	#include <asm/fsl_pci.h>
9bd4e591	37	#include <asm/fsl_ddr_sdram.h>
13f5433f JL	38	#include <libfdt.h>
13f5433f JL	39	#include <fdt_support.h>
8ac27327	40
8ac27327 JH	41	long int fixed_sdram (void);
	42
	43	int board_early_init_f (void)
	44	{
	45	return 0;
	46	}
	47
	48	int checkboard (void)
	49	{
	50	puts ("Board: Wind River SBC8641D\n");
	51
8ac27327 JH	52	return 0;
	53	}
	54
9973e3c6	55	phys_size_t initdram (int board_type)
8ac27327 JH	56	{
	57	long dram_size = 0;
	58
	59	#if defined(CONFIG_SPD_EEPROM)
9bd4e591	60	dram_size = fsl_ddr_sdram();
8ac27327 JH	61	#else
	62	dram_size = fixed_sdram ();
	63	#endif
	64
8ac27327 JH	65	puts (" DDR: ");
	66	return dram_size;
	67	}
	68
6d0f6bcf	69	#if defined(CONFIG_SYS_DRAM_TEST)
8ac27327 JH	70	int testdram (void)
8ac27327 JH	71	{
6d0f6bcf JCPV	72	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	73	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
8ac27327 JH	74	uint *p;
	75
	76	puts ("SDRAM test phase 1:\n");
	77	for (p = pstart; p < pend; p++)
	78	*p = 0xaaaaaaaa;
	79
	80	for (p = pstart; p < pend; p++) {
	81	if (*p != 0xaaaaaaaa) {
	82	printf ("SDRAM test fails at: %08x\n", (uint) p);
	83	return 1;
	84	}
	85	}
	86
	87	puts ("SDRAM test phase 2:\n");
	88	for (p = pstart; p < pend; p++)
	89	*p = 0x55555555;
	90
	91	for (p = pstart; p < pend; p++) {
	92	if (*p != 0x55555555) {
	93	printf ("SDRAM test fails at: %08x\n", (uint) p);
	94	return 1;
	95	}
	96	}
	97
	98	puts ("SDRAM test passed.\n");
	99	return 0;
	100	}
	101	#endif
	102
	103	#if !defined(CONFIG_SPD_EEPROM)
	104	/*
	105	* Fixed sdram init -- doesn't use serial presence detect.
	106	*/
	107	long int fixed_sdram (void)
	108	{
6d0f6bcf JCPV	109	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	110	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
8ac27327 JH	111	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
8ac27327 JH	112
6d0f6bcf JCPV	113	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	114	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	115	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	116	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	117	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	118	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	119	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	120	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	121	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	122	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	123	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	124	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
e7ee23ec	125	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
6d0f6bcf	126	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
e7ee23ec	127	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
6d0f6bcf JCPV	128	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	129	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
	130	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	131	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	132	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
8ac27327 JH	133
	134	asm ("sync;isync");
	135
	136	udelay (500);
	137
e7ee23ec	138	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
8ac27327 JH	139	asm ("sync; isync");
	140
	141	udelay (500);
	142	ddr = &immap->im_ddr2;
	143
6d0f6bcf JCPV	144	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	145	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	146	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	147	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	148	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	149	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	150	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	151	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	152	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	153	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	154	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	155	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
e7ee23ec	156	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
6d0f6bcf	157	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
e7ee23ec	158	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
6d0f6bcf JCPV	159	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
	160	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
	161	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	162	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	163	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
8ac27327 JH	164
	165	asm ("sync;isync");
	166
	167	udelay (500);
	168
e7ee23ec	169	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
8ac27327 JH	170	asm ("sync; isync");
	171
	172	udelay (500);
	173	#endif
6d0f6bcf	174	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
8ac27327 JH	175	}
	176	#endif /* !defined(CONFIG_SPD_EEPROM) */
	177
	178	#if defined(CONFIG_PCI)
	179	/*
	180	* Initialize PCI Devices, report devices found.
	181	*/
	182
	183	#ifndef CONFIG_PCI_PNP
	184	static struct pci_config_table pci_fsl86xxads_config_table[] = {
	185	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	186	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	187	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	188	PCI_ENET0_MEMADDR,
	189	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER}},
	190	{}
	191	};
	192	#endif
	193
46f3e385	194	static struct pci_controller pcie1_hose = {
8ac27327	195	#ifndef CONFIG_PCI_PNP
cca34967	196	config_table:pci_mpc86xxcts_config_table
8ac27327 JH	197	#endif
8ac27327 JH	198	};
cca34967	199	#endif /* CONFIG_PCI */
8ac27327	200
46f3e385 KG	201	#ifdef CONFIG_PCIE2
	202	static struct pci_controller pcie2_hose;
	203	#endif /* CONFIG_PCIE2 */
8ac27327	204
cca34967 JH	205	int first_free_busno = 0;
	206
	207	void pci_init_board(void)
8ac27327	208	{
4e339b83	209	struct fsl_pci_info pci_info[2];
6d0f6bcf	210	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
cca34967	211	volatile ccsr_gur_t *gur = &immap->im_gur;
4e339b83	212	uint devdisr = in_be32(&gur->devdisr);
33fa5c0b JL	213	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
33fa5c0b JL	214	>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
4e339b83 PT	215	int pcie_ep;
4e339b83 PT	216	int num = 0;
cca34967	217
46f3e385	218	#ifdef CONFIG_PCIE1
4e339b83 PT	219	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
	220
	221	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
	222	SET_STD_PCIE_INFO(pci_info[num], 1);
	223	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
	224	printf(" PCIE1 connected as %s (base addr %lx)\n",
	225	pcie_ep ? "Endpoint" : "Root Complex",
	226	pci_info[num].regs);
	227	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	228	&pcie1_hose, first_free_busno);
cca34967	229	} else {
4e339b83	230	puts(" PCIE1: disabled\n");
cca34967	231	}
cca34967	232	#else
4e339b83	233	puts(" PCIE1: disabled\n");
46f3e385	234	#endif /* CONFIG_PCIE1 */
cca34967	235
46f3e385	236	#ifdef CONFIG_PCIE2
cca34967	237
4e339b83 PT	238	SET_STD_PCIE_INFO(pci_info[num], 2);
	239	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
	240	printf(" PCIE2 connected as %s (base addr %lx)\n",
	241	pcie_ep ? "Endpoint" : "Root Complex",
	242	pci_info[num].regs);
	243	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	244	&pcie2_hose, first_free_busno);
cca34967	245	#else
4e339b83	246	puts(" PCIE2: disabled\n");
46f3e385	247	#endif /* CONFIG_PCIE2 */
8ac27327 JH	248	}
8ac27327 JH	249
13f5433f JL	250
13f5433f JL	251	#if defined(CONFIG_OF_BOARD_SETUP)
c2083e0e	252	void ft_board_setup (void blob, bd_t bd)
8ac27327	253	{
13f5433f	254	ft_cpu_setup(blob, bd);
8ac27327	255
6525d51f	256	FT_FSL_PCI_SETUP;
8ac27327 JH	257	}
	258	#endif
	259
	260	void sbc8641d_reset_board (void)
	261	{
	262	puts ("Resetting board....\n");
	263	}
	264
	265	/*
	266	* get_board_sys_clk
	267	* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
	268	*/
	269
	270	unsigned long get_board_sys_clk (ulong dummy)
	271	{
	272	int i;
	273	ulong val = 0;
	274
	275	i = 5;
	276	i &= 0x07;
	277
	278	switch (i) {
	279	case 0:
	280	val = 33000000;
	281	break;
	282	case 1:
	283	val = 40000000;
	284	break;
	285	case 2:
	286	val = 50000000;
	287	break;
	288	case 3:
	289	val = 66000000;
	290	break;
	291	case 4:
	292	val = 83000000;
	293	break;
	294	case 5:
	295	val = 100000000;
	296	break;
	297	case 6:
	298	val = 134000000;
	299	break;
	300	case 7:
	301	val = 166000000;
	302	break;
	303	}
	304
	305	return val;
	306	}
4ef630df PT	307
	308	void board_reset(void)
	309	{
	310	#ifdef CONFIG_SYS_RESET_ADDRESS
	311	ulong addr = CONFIG_SYS_RESET_ADDRESS;
	312
	313	/* flush and disable I/D cache */
	314	__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
	315	__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
	316	__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
	317	__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
	318	__asm__ __volatile__ ("sync");
	319	__asm__ __volatile__ ("mtspr 1008, 4");
	320	__asm__ __volatile__ ("isync");
	321	__asm__ __volatile__ ("sync");
	322	__asm__ __volatile__ ("mtspr 1008, 5");
	323	__asm__ __volatile__ ("isync");
	324	__asm__ __volatile__ ("sync");
	325
	326	/*
	327	* SRR0 has system reset vector, SRR1 has default MSR value
	328	* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	329	*/
	330	__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
	331	__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
	332	__asm__ __volatile__ ("mtspr 27, 4");
	333	__asm__ __volatile__ ("rfi");
	334	#endif
	335	}
f6ef8b7a	336
7649a590	337	#ifdef CONFIG_MP
f6ef8b7a BB	338	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	339
	340	void board_lmb_reserve(struct lmb *lmb)
	341	{
	342	cpu_mp_lmb_reserve(lmb);
	343	}
	344	#endif