[people/ms/u-boot.git] / board / sc3 / init.S

/*------------------------------------------------------------------------------+
 *
 *	 This souce code has been made available to you by EuroDesign
 *	 (www.eurodsn.de). It's based on the original IBM source code, so
 *	 this follows:
 *
 *   This source code is dual-licensed.  You may use it under the terms of the
 *   GNU General Public License version 2, or under the license below.
 *
 *	 This source code has been made available to you by IBM on an AS-IS
 *	 basis.  Anyone receiving this source is licensed under IBM
 *	 copyrights to use it in any way he or she deems fit, including
 *	 copying it, modifying it, compiling it, and redistributing it either
 *	 with or without modifications.  No license under IBM patents or
 *	 patent applications is to be implied by the copyright license.
 *
 *	 Any user of this software should understand that IBM cannot provide
 *	 technical support for this software and will not be responsible for
 *	 any consequences resulting from the use of this software.
 *
 *	 Any person who transfers this source code or any derivative work
 *	 must include the IBM copyright notice, this paragraph, and the
 *	 preceding two paragraphs in the transferred software.
 *
 *	 COPYRIGHT   I B M   CORPORATION 1995
 *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *------------------------------------------------------------------------------- */

#include <config.h>
#include <asm/ppc4xx.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/**
 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
 *
 * IMPORTANT: For pass1 this code must run from cache since you can not
 * reliably change a peripheral banks timing register (pbxap) while running
 * code from that bank. For ex., since we are running from ROM on bank 0, we
 * can NOT execute the code that modifies bank 0 timings from ROM, so
 * we run it from cache.
 *
 * Bank 0 - Boot-Flash
 * Bank 1 - NAND-Flash
 * Bank 2 - ISA bus
 * Bank 3 - Second Flash
 * Bank 4 - USB controller
 */
	.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
 * We need the current boot up configuration to set correct
 * timings into internal flash and external flash
 */
		mfdcr r24,CPC0_PSR		/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
						   0 0 -> 8 bit external ROM
						   0 1 -> 16 bit internal ROM */
		addi r4,0,2
		srw r24,r24,r4				/* shift right r24 two positions */
		andi. r24,r24,0x06000
/*
 * All calculations are based on 33MHz EBC clock.
 *
 * First, create a "very slow" timing (~250ns) with burst mode enabled
 * This is need for the external flash access
 */
		lis r25,0x0800
		/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
		ori r25,r25,0x0280
/*
 * Second, create a fast timing:
 * 90ns first cycle - 3 clock access
 * and 90ns burst cycle, plus 1 clock after the last access
 * This is used for the internal access
 */
		lis r26,0x8900
		/* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
		ori r26,r26,0x0280
/*
 * We can't change settings on CS# if we currently use them.
 * -> load a few instructions into cache and run this code from cache
 */
		mflr r4					/* save link register */
		bl ..getAddr
..getAddr:
		mflr r3					/* get address of ..getAddr */
		mtlr r4					/* restore link register */
		addi r4,0,14				/* set ctr to 10; used to prefetch */
		mtctr r4				/* 10 cache lines to fit this function
							in cache (gives us 8x10=80 instructions) */
..ebcloop:
		icbt r0,r3				/* prefetch cache line for addr in r3 */
		addi r3,r3,32				/* move to next cache line */
		bdnz ..ebcloop				/* continue for 10 cache lines */
/*
 * Delay to ensure all accesses to ROM are complete before changing
 * bank 0 timings. 200usec should be enough.
 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 */
		lis r3,0x0
		ori r3,r3,0xA000			/* ensure 200usec have passed since reset */
		mtctr r3
..spinlp:
		bdnz ..spinlp				/* spin loop */

/*-----------------------------------------------------------------------
 * Memory Bank 0 (BOOT-ROM) initialization
 * 0xFFEF00000....0xFFFFFFF
 * We only have to change the timing. Mapping is ok by boot-strapping
 *----------------------------------------------------------------------- */

		li r4,PB1AP				/* PB0AP=Peripheral Bank 0 Access Parameters */
		mtdcr EBC0_CFGADDR,r4

		mr r4,r26				/* assume internal fast flash is boot flash */
		cmpwi r24,0x2000			/* assumption true? ... */
		beq 1f					/* ...yes! */
		mr r4,r25				/* ...no, use the slow variant */
		mr r25,r26				/* use this for the other flash */
1:
		mtdcr EBC0_CFGDATA,r4			/* change timing now */

		li r4,PB0CR				/* PB0CR=Peripheral Bank 0 Control Register */
		mtdcr EBC0_CFGADDR,r4
		mfdcr r4,EBC0_CFGDATA
		lis r3,0x0001
		ori r3,r3,0x8000			/* allow reads and writes */
		or r4,r4,r3
		mtdcr EBC0_CFGDATA,r4

/*-----------------------------------------------------------------------
 * Memory Bank 3 (Second-Flash) initialization
 * 0xF0000000...0xF01FFFFF -> 2MB
 *----------------------------------------------------------------------- */

		li r4,PB3AP				/* Peripheral Bank 1 Access Parameter */
		mtdcr EBC0_CFGADDR,r4
		mtdcr EBC0_CFGDATA,r2			/* change timing */

		li r4,PB3CR				/* Peripheral Bank 1 Configuration Registers */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0xF003
		ori r4,r4,0x8000
/*
 * Consider boot configuration
 */
		xori r24,r24,0x2000			/* invert current bus width */
		or r4,r4,r24
		mtdcr EBC0_CFGDATA,r4

/*-----------------------------------------------------------------------
 * Memory Bank 1 (NAND-Flash) initialization
 * 0x77D00000...0x77DFFFFF -> 1MB
 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
 * - the setup time is 0ns
 * - the hold time is 15ns
 * ->
 *   - TWT = 0
 *   - CSN = 0
 *   - OEN = 0
 *   - WBN = 0
 *   - WBF = 0
 *   - TH  = 1
 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
 *----------------------------------------------------------------------- */

		li r4,PB1AP				/* Peripheral Bank 1 Access Parameter */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x0000
		ori r4,r4,0x0200
		mtdcr EBC0_CFGDATA,r4

		li r4,PB1CR				/* Peripheral Bank 1 Configuration Registers */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x77D1
		ori r4,r4,0x8000
		mtdcr EBC0_CFGDATA,r4


/* USB init (without acceleration) */
#ifndef CONFIG_ISP1161_PRESENT
		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
		mtdcr EBC0_CFGADDR,r4
		lis r4,0x0180
		ori r4,r4,0x5940
		mtdcr EBC0_CFGDATA,r4
#endif

/*-----------------------------------------------------------------------
 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
 * 0x78000000...0x7BFFFFFF -> 64 MB
 * Wir arbeiten bei 33 MHz -> 30ns
 *-----------------------------------------------------------------------

 A7 (ppc notation) or A24 (standard notation) decides about
 the type of access:
 A7/A24=0 -> memory cycle
 A7/ /A24=1 -> I/O cycle
*/
		li r4,PB2AP				/* PB2AP=Peripheral Bank 2 Access Parameters */
		mtdcr EBC0_CFGADDR,r4
/*
 We emulate an ISA access

 1. Address active
 2. wait 0 EBC clocks -> CSN=0
 3. set CS#
 4. wait 0 EBC clock -> OEN/WBN=0
 5. set OE#/WE#
 6. wait 4 clocks (ca. 90ns) and for Ready signal
 7. hold for 4 clocks -> TH=4
*/

#if 1
/* faster access to isa-bus */
		lis r4,0x0180
		ori r4,r4,0x5940
#else
		lis r4,0x0100
		ori r4,r4,0x0340
#endif
		mtdcr EBC0_CFGDATA,r4

#ifdef IDE_USES_ISA_EMULATION
		li r25,PB5AP				/* PB5AP=Peripheral Bank 5 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4
#endif

		li r25,PB6AP				/* PB6AP=Peripheral Bank 6 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4
		li r25,PB7AP				/* PB7AP=Peripheral Bank 7 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4

		li r25,PB2CR				/* PB2CR=Peripheral Bank 2 Configuration Register */
		mtdcr EBC0_CFGADDR,r25

		lis r4,0x780B
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
/*
 * the other areas are only 1MiB in size
 */
		lis r4,0x7401
		ori r4,r4,0xA000

		li r25,PB6CR				/* PB6CR=Peripheral Bank 6 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7401
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

		li r25,PB7CR				/* PB7CR=Peripheral Bank 7 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7411
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

#ifndef CONFIG_ISP1161_PRESENT
		li r25,PB4CR				/* PB4CR=Peripheral Bank 4 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7421
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
#endif
#ifdef IDE_USES_ISA_EMULATION
		li r25,PB5CR				/* PB5CR=Peripheral Bank 5 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x0000
		ori r4,r4,0x0000
		mtdcr EBC0_CFGDATA,r4
#endif

/*-----------------------------------------------------------------------
 * Memory bank 4: USB controller Philips ISP6111
 * 0x77C00000 ... 0x77CFFFFF
 *
 * The chip is connected to:
 * - CPU CS#4
 * - CPU IRQ#2
 * - CPU DMA 3
 *
 * Timing:
 * - command to first data: 300ns. Software must ensure this timing!
 * - Write pulse: 26ns
 * - Read pulse: 33ns
 * - read cycle time: 150ns
 * - write cycle time: 140ns
 *
 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
 *
 *			  |- 300ns --|
 *		  |---- 420ns ---|---- 420ns ---| cycle
 * CS ############:###____#######:###____#######
 * OE ############:####___#######:####___#######
 * WE ############:####__########:####__########
 *
 * ----> 2 clocks RD/WR pulses: 60ns
 * ----> CSN: 3 clock, 90ns
 * ----> OEN: 1 clocks (read cycle)
 * ----> WBN: 1 clocks (write cycle)
 * ----> WBE: 2 clocks
 * ----> TH: 7 clock, 210ns
 * ----> TWT: 7 clocks
 *----------------------------------------------------------------------- */

#ifdef CONFIG_ISP1161_PRESENT

		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x030D
		ori r4,r4,0x5E80
		mtdcr EBC0_CFGDATA,r4

		li r4,PB4CR				/* PB2CR=Peripheral Bank 4 Configuration Register */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x77C1
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

#endif

#ifndef IDE_USES_ISA_EMULATION

/*-----------------------------------------------------------------------
 * Memory Bank 5 used for IDE access
 *
 * Timings for IDE Interface
 *
 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
 *  70		165		30		PIO-Mode 0, [ns]
 *   3		  6		 1		[Cycles] ----> AP=0x040C0200
 *  50		125		20	   PIO-Mode 1, [ns]
 *   2		  5		 1		[Cycles] ----> AP=0x03080200
 *  30		100		15	   PIO-Mode 2, [ns]
 *   1		  4		 1		[Cycles] ----> AP=0x02040200
 *  30		 80		10	   PIO-Mode 3, [ns]
 *   1		  3		 1		[Cycles] ----> AP=0x01840200
 *  25		 70		10	   PIO-Mode 4, [ns]
 *   1		  3		 1		[Cycles] ----> AP=0x01840200
 *
 *----------------------------------------------------------------------- */

		li r4,PB5AP
		mtdcr EBC0_CFGADDR,r4
		lis r4,0x040C
		ori r4,r4,0x0200
		mtdcr EBC0_CFGDATA,r4

		li r4,PB5CR			/* PB2CR=Peripheral Bank 2 Configuration Register */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x7A01
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
#endif
/*
 * External Peripheral Control Register
 */
		li r4,EBC0_CFG
		mtdcr EBC0_CFGADDR,r4

		lis r4,0xB84E
		ori r4,r4,0xF000
		mtdcr EBC0_CFGDATA,r4
/*
 * drive POST code
 */
		lis r4,0x7900
		ori r4,r4,0x0080
		li r3,0x0001
		stb r3,0(r4)			/* 01 -> external bus controller is initialized */
		nop				/* pass2 DCR errata #8 */
		blr
Commit	Line	Data
ca43ba18 HS	1	/*------------------------------------------------------------------------------+
ca43ba18 HS	2	*
f11033e7 WD	3	* This souce code has been made available to you by EuroDesign
	4	* (www.eurodsn.de). It's based on the original IBM source code, so
	5	* this follows:
ca43ba18	6	*
31773496 JB	7	* This source code is dual-licensed. You may use it under the terms of the
	8	* GNU General Public License version 2, or under the license below.
	9	*
f11033e7 WD	10	* This source code has been made available to you by IBM on an AS-IS
	11	* basis. Anyone receiving this source is licensed under IBM
	12	* copyrights to use it in any way he or she deems fit, including
	13	* copying it, modifying it, compiling it, and redistributing it either
	14	* with or without modifications. No license under IBM patents or
	15	* patent applications is to be implied by the copyright license.
ca43ba18	16	*
f11033e7 WD	17	* Any user of this software should understand that IBM cannot provide
	18	* technical support for this software and will not be responsible for
	19	* any consequences resulting from the use of this software.
ca43ba18	20	*
f11033e7 WD	21	* Any person who transfers this source code or any derivative work
	22	* must include the IBM copyright notice, this paragraph, and the
	23	* preceding two paragraphs in the transferred software.
ca43ba18	24	*
f11033e7 WD	25	* COPYRIGHT I B M CORPORATION 1995
f11033e7 WD	26	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
ca43ba18 HS	27	------------------------------------------------------------------------------- /
	28
	29	#include <config.h>
b36df561	30	#include <asm/ppc4xx.h>
ca43ba18 HS	31
	32	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	33
	34	#include <ppc_asm.tmpl>
	35	#include <ppc_defs.h>
	36
	37	#include <asm/cache.h>
	38	#include <asm/mmu.h>
	39
	40	/**
	41	* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
	42	*
	43	* IMPORTANT: For pass1 this code must run from cache since you can not
	44	* reliably change a peripheral banks timing register (pbxap) while running
	45	* code from that bank. For ex., since we are running from ROM on bank 0, we
	46	* can NOT execute the code that modifies bank 0 timings from ROM, so
	47	* we run it from cache.
	48	*
	49	* Bank 0 - Boot-Flash
	50	* Bank 1 - NAND-Flash
	51	* Bank 2 - ISA bus
	52	* Bank 3 - Second Flash
	53	* Bank 4 - USB controller
	54	*/
	55	.globl ext_bus_cntlr_init
	56	ext_bus_cntlr_init:
	57	/*
	58	* We need the current boot up configuration to set correct
	59	* timings into internal flash and external flash
	60	*/
d1c3b275	61	mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
f11033e7 WD	62	0 0 -> 8 bit external ROM
f11033e7 WD	63	0 1 -> 16 bit internal ROM */
ca43ba18 HS	64	addi r4,0,2
	65	srw r24,r24,r4 /* shift right r24 two positions */
	66	andi. r24,r24,0x06000
f11033e7	67	/*
ca43ba18 HS	68	* All calculations are based on 33MHz EBC clock.
	69	*
	70	* First, create a "very slow" timing (~250ns) with burst mode enabled
	71	* This is need for the external flash access
	72	*/
	73	lis r25,0x0800
3fd1e85a JH	74	/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
3fd1e85a JH	75	ori r25,r25,0x0280
ca43ba18 HS	76	/*
	77	* Second, create a fast timing:
	78	* 90ns first cycle - 3 clock access
	79	* and 90ns burst cycle, plus 1 clock after the last access
	80	* This is used for the internal access
	81	*/
	82	lis r26,0x8900
3fd1e85a JH	83	/* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
3fd1e85a JH	84	ori r26,r26,0x0280
ca43ba18 HS	85	/*
	86	* We can't change settings on CS# if we currently use them.
	87	* -> load a few instructions into cache and run this code from cache
	88	*/
	89	mflr r4 /* save link register */
	90	bl ..getAddr
	91	..getAddr:
	92	mflr r3 /* get address of ..getAddr */
	93	mtlr r4 /* restore link register */
	94	addi r4,0,14 /* set ctr to 10; used to prefetch */
	95	mtctr r4 /* 10 cache lines to fit this function
	96	in cache (gives us 8x10=80 instructions) */
	97	..ebcloop:
	98	icbt r0,r3 /* prefetch cache line for addr in r3 */
	99	addi r3,r3,32 /* move to next cache line */
	100	bdnz ..ebcloop /* continue for 10 cache lines */
	101	/*
	102	* Delay to ensure all accesses to ROM are complete before changing
	103	* bank 0 timings. 200usec should be enough.
	104	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	105	*/
	106	lis r3,0x0
	107	ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
	108	mtctr r3
	109	..spinlp:
	110	bdnz ..spinlp /* spin loop */
	111
	112	/*-----------------------------------------------------------------------
	113	* Memory Bank 0 (BOOT-ROM) initialization
	114	* 0xFFEF00000....0xFFFFFFF
	115	* We only have to change the timing. Mapping is ok by boot-strapping
	116	----------------------------------------------------------------------- /
	117
d1c3b275 SR	118	li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
d1c3b275 SR	119	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	120
	121	mr r4,r26 /* assume internal fast flash is boot flash */
	122	cmpwi r24,0x2000 /* assumption true? ... */
	123	beq 1f /* ...yes! */
	124	mr r4,r25 /* ...no, use the slow variant */
	125	mr r25,r26 /* use this for the other flash */
	126	1:
d1c3b275	127	mtdcr EBC0_CFGDATA,r4 /* change timing now */
ca43ba18	128
d1c3b275 SR	129	li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
	130	mtdcr EBC0_CFGADDR,r4
	131	mfdcr r4,EBC0_CFGDATA
ca43ba18 HS	132	lis r3,0x0001
	133	ori r3,r3,0x8000 /* allow reads and writes */
	134	or r4,r4,r3
d1c3b275	135	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	136
ca43ba18 HS	137	/*-----------------------------------------------------------------------
f11033e7	138	* Memory Bank 3 (Second-Flash) initialization
ca43ba18 HS	139	* 0xF0000000...0xF01FFFFF -> 2MB
	140	----------------------------------------------------------------------- /
	141
d1c3b275 SR	142	li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
	143	mtdcr EBC0_CFGADDR,r4
	144	mtdcr EBC0_CFGDATA,r2 /* change timing */
ca43ba18	145
d1c3b275 SR	146	li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
d1c3b275 SR	147	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	148
	149	lis r4,0xF003
	150	ori r4,r4,0x8000
	151	/*
	152	* Consider boot configuration
	153	*/
	154	xori r24,r24,0x2000 /* invert current bus width */
	155	or r4,r4,r24
d1c3b275	156	mtdcr EBC0_CFGDATA,r4
f11033e7	157
ca43ba18 HS	158	/*-----------------------------------------------------------------------
	159	* Memory Bank 1 (NAND-Flash) initialization
	160	* 0x77D00000...0x77DFFFFF -> 1MB
	161	* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
	162	* - the setup time is 0ns
	163	* - the hold time is 15ns
	164	* ->
	165	* - TWT = 0
	166	* - CSN = 0
	167	* - OEN = 0
	168	* - WBN = 0
	169	* - WBF = 0
	170	* - TH = 1
	171	* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
	172	----------------------------------------------------------------------- /
	173
d1c3b275 SR	174	li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
d1c3b275 SR	175	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	176
	177	lis r4,0x0000
	178	ori r4,r4,0x0200
d1c3b275	179	mtdcr EBC0_CFGDATA,r4
ca43ba18	180
d1c3b275 SR	181	li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
d1c3b275 SR	182	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	183
	184	lis r4,0x77D1
	185	ori r4,r4,0x8000
d1c3b275	186	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	187
	188
	189	/* USB init (without acceleration) */
	190	#ifndef CONFIG_ISP1161_PRESENT
d1c3b275 SR	191	li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
d1c3b275 SR	192	mtdcr EBC0_CFGADDR,r4
ca43ba18	193	lis r4,0x0180
f11033e7	194	ori r4,r4,0x5940
d1c3b275	195	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	196	#endif
	197
	198	/*-----------------------------------------------------------------------
	199	* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
	200	* 0x78000000...0x7BFFFFFF -> 64 MB
	201	* Wir arbeiten bei 33 MHz -> 30ns
	202	*-----------------------------------------------------------------------
	203
	204	A7 (ppc notation) or A24 (standard notation) decides about
	205	the type of access:
	206	A7/A24=0 -> memory cycle
f11033e7	207	A7/ /A24=1 -> I/O cycle
ca43ba18	208	*/
d1c3b275 SR	209	li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
d1c3b275 SR	210	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	211	/*
	212	We emulate an ISA access
	213
	214	1. Address active
	215	2. wait 0 EBC clocks -> CSN=0
	216	3. set CS#
	217	4. wait 0 EBC clock -> OEN/WBN=0
	218	5. set OE#/WE#
	219	6. wait 4 clocks (ca. 90ns) and for Ready signal
	220	7. hold for 4 clocks -> TH=4
	221	*/
	222
	223	#if 1
	224	/* faster access to isa-bus */
	225	lis r4,0x0180
	226	ori r4,r4,0x5940
	227	#else
	228	lis r4,0x0100
	229	ori r4,r4,0x0340
	230	#endif
d1c3b275	231	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	232
ca43ba18 HS	233	#ifdef IDE_USES_ISA_EMULATION
d1c3b275 SR	234	li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
	235	mtdcr EBC0_CFGADDR,r25
	236	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	237	#endif
ca43ba18 HS	238
d1c3b275 SR	239	li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
	240	mtdcr EBC0_CFGADDR,r25
	241	mtdcr EBC0_CFGDATA,r4
	242	li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
	243	mtdcr EBC0_CFGADDR,r25
	244	mtdcr EBC0_CFGDATA,r4
ca43ba18	245
d1c3b275 SR	246	li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
d1c3b275 SR	247	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	248
	249	lis r4,0x780B
	250	ori r4,r4,0xA000
d1c3b275	251	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	252	/*
	253	* the other areas are only 1MiB in size
	254	*/
	255	lis r4,0x7401
	256	ori r4,r4,0xA000
	257
d1c3b275 SR	258	li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
d1c3b275 SR	259	mtdcr EBC0_CFGADDR,r25
ca43ba18	260	lis r4,0x7401
f11033e7	261	ori r4,r4,0xA000
d1c3b275	262	mtdcr EBC0_CFGDATA,r4
ca43ba18	263
d1c3b275 SR	264	li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
d1c3b275 SR	265	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	266	lis r4,0x7411
ca43ba18 HS	267	ori r4,r4,0xA000
d1c3b275	268	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	269
ca43ba18 HS	270	#ifndef CONFIG_ISP1161_PRESENT
d1c3b275 SR	271	li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
d1c3b275 SR	272	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	273	lis r4,0x7421
ca43ba18 HS	274	ori r4,r4,0xA000
d1c3b275	275	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	276	#endif
ca43ba18 HS	277	#ifdef IDE_USES_ISA_EMULATION
d1c3b275 SR	278	li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
d1c3b275 SR	279	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	280	lis r4,0x0000
ca43ba18 HS	281	ori r4,r4,0x0000
d1c3b275	282	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	283	#endif
	284
	285	/*-----------------------------------------------------------------------
	286	* Memory bank 4: USB controller Philips ISP6111
	287	* 0x77C00000 ... 0x77CFFFFF
	288	*
	289	* The chip is connected to:
	290	* - CPU CS#4
	291	* - CPU IRQ#2
	292	* - CPU DMA 3
	293	*
	294	* Timing:
	295	* - command to first data: 300ns. Software must ensure this timing!
	296	* - Write pulse: 26ns
	297	* - Read pulse: 33ns
	298	* - read cycle time: 150ns
	299	* - write cycle time: 140ns
	300	*
	301	* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
	302	*
f11033e7 WD	303	* \|- 300ns --\|
f11033e7 WD	304	* \|---- 420ns ---\|---- 420ns ---\| cycle
ca43ba18 HS	305	* CS ############:###____#######:###____#######
	306	* OE ############:####___#######:####___#######
	307	* WE ############:####__########:####__########
	308	*
	309	* ----> 2 clocks RD/WR pulses: 60ns
	310	* ----> CSN: 3 clock, 90ns
	311	* ----> OEN: 1 clocks (read cycle)
	312	* ----> WBN: 1 clocks (write cycle)
	313	* ----> WBE: 2 clocks
	314	* ----> TH: 7 clock, 210ns
	315	* ----> TWT: 7 clocks
	316	----------------------------------------------------------------------- /
	317
	318	#ifdef CONFIG_ISP1161_PRESENT
	319
d1c3b275 SR	320	li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
d1c3b275 SR	321	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	322
	323	lis r4,0x030D
	324	ori r4,r4,0x5E80
d1c3b275	325	mtdcr EBC0_CFGDATA,r4
ca43ba18	326
d1c3b275 SR	327	li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
d1c3b275 SR	328	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	329
	330	lis r4,0x77C1
	331	ori r4,r4,0xA000
d1c3b275	332	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	333
	334	#endif
	335
	336	#ifndef IDE_USES_ISA_EMULATION
	337
	338	/*-----------------------------------------------------------------------
	339	* Memory Bank 5 used for IDE access
	340	*
	341	* Timings for IDE Interface
	342	*
	343	* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
	344	* 70 165 30 PIO-Mode 0, [ns]
	345	* 3 6 1 [Cycles] ----> AP=0x040C0200
	346	* 50 125 20 PIO-Mode 1, [ns]
	347	* 2 5 1 [Cycles] ----> AP=0x03080200
	348	* 30 100 15 PIO-Mode 2, [ns]
	349	* 1 4 1 [Cycles] ----> AP=0x02040200
	350	* 30 80 10 PIO-Mode 3, [ns]
	351	* 1 3 1 [Cycles] ----> AP=0x01840200
	352	* 25 70 10 PIO-Mode 4, [ns]
	353	* 1 3 1 [Cycles] ----> AP=0x01840200
	354	*
	355	----------------------------------------------------------------------- /
	356
d1c3b275 SR	357	li r4,PB5AP
d1c3b275 SR	358	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	359	lis r4,0x040C
ca43ba18 HS	360	ori r4,r4,0x0200
d1c3b275	361	mtdcr EBC0_CFGDATA,r4
ca43ba18	362
d1c3b275 SR	363	li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
d1c3b275 SR	364	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	365
	366	lis r4,0x7A01
	367	ori r4,r4,0xA000
d1c3b275	368	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	369	#endif
	370	/*
	371	* External Peripheral Control Register
	372	*/
d1c3b275 SR	373	li r4,EBC0_CFG
d1c3b275 SR	374	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	375
	376	lis r4,0xB84E
	377	ori r4,r4,0xF000
d1c3b275	378	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	379	/*
	380	* drive POST code
	381	*/
	382	lis r4,0x7900
	383	ori r4,r4,0x0080
	384	li r3,0x0001
	385	stb r3,0(r4) /* 01 -> external bus controller is initialized */
	386	nop /* pass2 DCR errata #8 */
	387	blr