[people/ms/u-boot.git] / board / sc3 / init.S

/*------------------------------------------------------------------------------+
 *
 *	 This souce code has been made available to you by EuroDesign
 *	 (www.eurodsn.de). It's based on the original IBM source code, so
 *	 this follows:
 *
 *   This source code is dual-licensed.  You may use it under the terms of the
 *   GNU General Public License version 2, or under the license below.
 *
 *	 This source code has been made available to you by IBM on an AS-IS
 *	 basis.  Anyone receiving this source is licensed under IBM
 *	 copyrights to use it in any way he or she deems fit, including
 *	 copying it, modifying it, compiling it, and redistributing it either
 *	 with or without modifications.  No license under IBM patents or
 *	 patent applications is to be implied by the copyright license.
 *
 *	 Any user of this software should understand that IBM cannot provide
 *	 technical support for this software and will not be responsible for
 *	 any consequences resulting from the use of this software.
 *
 *	 Any person who transfers this source code or any derivative work
 *	 must include the IBM copyright notice, this paragraph, and the
 *	 preceding two paragraphs in the transferred software.
 *
 *	 COPYRIGHT   I B M   CORPORATION 1995
 *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *------------------------------------------------------------------------------- */

#include <config.h>
#include <asm/ppc4xx.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/**
 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
 *
 * IMPORTANT: For pass1 this code must run from cache since you can not
 * reliably change a peripheral banks timing register (pbxap) while running
 * code from that bank. For ex., since we are running from ROM on bank 0, we
 * can NOT execute the code that modifies bank 0 timings from ROM, so
 * we run it from cache.
 *
 * Bank 0 - Boot-Flash
 * Bank 1 - NAND-Flash
 * Bank 2 - ISA bus
 * Bank 3 - Second Flash
 * Bank 4 - USB controller
 */
	.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
 * We need the current boot up configuration to set correct
 * timings into internal flash and external flash
 */
		mfdcr r24,CPC0_PSR		/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
						   0 0 -> 8 bit external ROM
						   0 1 -> 16 bit internal ROM */
		addi r4,0,2
		srw r24,r24,r4				/* shift right r24 two positions */
		andi. r24,r24,0x06000
/*
 * All calculations are based on 33MHz EBC clock.
 *
 * First, create a "very slow" timing (~250ns) with burst mode enabled
 * This is need for the external flash access
 */
		lis r25,0x0800
		ori r25,r25,0x0280			/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
/*
 * Second, create a fast timing:
 * 90ns first cycle - 3 clock access
 * and 90ns burst cycle, plus 1 clock after the last access
 * This is used for the internal access
 */
		lis r26,0x8900
		ori r26,r26,0x0280			/* 1000 1001 0xxx 0000 0000 0010 100x xxxx
/*
 * We can't change settings on CS# if we currently use them.
 * -> load a few instructions into cache and run this code from cache
 */
		mflr r4					/* save link register */
		bl ..getAddr
..getAddr:
		mflr r3					/* get address of ..getAddr */
		mtlr r4					/* restore link register */
		addi r4,0,14				/* set ctr to 10; used to prefetch */
		mtctr r4				/* 10 cache lines to fit this function
							in cache (gives us 8x10=80 instructions) */
..ebcloop:
		icbt r0,r3				/* prefetch cache line for addr in r3 */
		addi r3,r3,32				/* move to next cache line */
		bdnz ..ebcloop				/* continue for 10 cache lines */
/*
 * Delay to ensure all accesses to ROM are complete before changing
 * bank 0 timings. 200usec should be enough.
 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 */
		lis r3,0x0
		ori r3,r3,0xA000			/* ensure 200usec have passed since reset */
		mtctr r3
..spinlp:
		bdnz ..spinlp				/* spin loop */

/*-----------------------------------------------------------------------
 * Memory Bank 0 (BOOT-ROM) initialization
 * 0xFFEF00000....0xFFFFFFF
 * We only have to change the timing. Mapping is ok by boot-strapping
 *----------------------------------------------------------------------- */

		li r4,PB1AP				/* PB0AP=Peripheral Bank 0 Access Parameters */
		mtdcr EBC0_CFGADDR,r4

		mr r4,r26				/* assume internal fast flash is boot flash */
		cmpwi r24,0x2000			/* assumption true? ... */
		beq 1f					/* ...yes! */
		mr r4,r25				/* ...no, use the slow variant */
		mr r25,r26				/* use this for the other flash */
1:
		mtdcr EBC0_CFGDATA,r4			/* change timing now */

		li r4,PB0CR				/* PB0CR=Peripheral Bank 0 Control Register */
		mtdcr EBC0_CFGADDR,r4
		mfdcr r4,EBC0_CFGDATA
		lis r3,0x0001
		ori r3,r3,0x8000			/* allow reads and writes */
		or r4,r4,r3
		mtdcr EBC0_CFGDATA,r4

/*-----------------------------------------------------------------------
 * Memory Bank 3 (Second-Flash) initialization
 * 0xF0000000...0xF01FFFFF -> 2MB
 *----------------------------------------------------------------------- */

		li r4,PB3AP				/* Peripheral Bank 1 Access Parameter */
		mtdcr EBC0_CFGADDR,r4
		mtdcr EBC0_CFGDATA,r2			/* change timing */

		li r4,PB3CR				/* Peripheral Bank 1 Configuration Registers */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0xF003
		ori r4,r4,0x8000
/*
 * Consider boot configuration
 */
		xori r24,r24,0x2000			/* invert current bus width */
		or r4,r4,r24
		mtdcr EBC0_CFGDATA,r4

/*-----------------------------------------------------------------------
 * Memory Bank 1 (NAND-Flash) initialization
 * 0x77D00000...0x77DFFFFF -> 1MB
 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
 * - the setup time is 0ns
 * - the hold time is 15ns
 * ->
 *   - TWT = 0
 *   - CSN = 0
 *   - OEN = 0
 *   - WBN = 0
 *   - WBF = 0
 *   - TH  = 1
 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
 *----------------------------------------------------------------------- */

		li r4,PB1AP				/* Peripheral Bank 1 Access Parameter */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x0000
		ori r4,r4,0x0200
		mtdcr EBC0_CFGDATA,r4

		li r4,PB1CR				/* Peripheral Bank 1 Configuration Registers */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x77D1
		ori r4,r4,0x8000
		mtdcr EBC0_CFGDATA,r4


/* USB init (without acceleration) */
#ifndef CONFIG_ISP1161_PRESENT
		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
		mtdcr EBC0_CFGADDR,r4
		lis r4,0x0180
		ori r4,r4,0x5940
		mtdcr EBC0_CFGDATA,r4
#endif

/*-----------------------------------------------------------------------
 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
 * 0x78000000...0x7BFFFFFF -> 64 MB
 * Wir arbeiten bei 33 MHz -> 30ns
 *-----------------------------------------------------------------------

 A7 (ppc notation) or A24 (standard notation) decides about
 the type of access:
 A7/A24=0 -> memory cycle
 A7/ /A24=1 -> I/O cycle
*/
		li r4,PB2AP				/* PB2AP=Peripheral Bank 2 Access Parameters */
		mtdcr EBC0_CFGADDR,r4
/*
 We emulate an ISA access

 1. Address active
 2. wait 0 EBC clocks -> CSN=0
 3. set CS#
 4. wait 0 EBC clock -> OEN/WBN=0
 5. set OE#/WE#
 6. wait 4 clocks (ca. 90ns) and for Ready signal
 7. hold for 4 clocks -> TH=4
*/

#if 1
/* faster access to isa-bus */
		lis r4,0x0180
		ori r4,r4,0x5940
#else
		lis r4,0x0100
		ori r4,r4,0x0340
#endif
		mtdcr EBC0_CFGDATA,r4

#ifdef IDE_USES_ISA_EMULATION
		li r25,PB5AP				/* PB5AP=Peripheral Bank 5 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4
#endif

		li r25,PB6AP				/* PB6AP=Peripheral Bank 6 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4
		li r25,PB7AP				/* PB7AP=Peripheral Bank 7 Access Parameters */
		mtdcr EBC0_CFGADDR,r25
		mtdcr EBC0_CFGDATA,r4

		li r25,PB2CR				/* PB2CR=Peripheral Bank 2 Configuration Register */
		mtdcr EBC0_CFGADDR,r25

		lis r4,0x780B
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
/*
 * the other areas are only 1MiB in size
 */
		lis r4,0x7401
		ori r4,r4,0xA000

		li r25,PB6CR				/* PB6CR=Peripheral Bank 6 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7401
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

		li r25,PB7CR				/* PB7CR=Peripheral Bank 7 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7411
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

#ifndef CONFIG_ISP1161_PRESENT
		li r25,PB4CR				/* PB4CR=Peripheral Bank 4 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x7421
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
#endif
#ifdef IDE_USES_ISA_EMULATION
		li r25,PB5CR				/* PB5CR=Peripheral Bank 5 Configuration Register */
		mtdcr EBC0_CFGADDR,r25
		lis r4,0x0000
		ori r4,r4,0x0000
		mtdcr EBC0_CFGDATA,r4
#endif

/*-----------------------------------------------------------------------
 * Memory bank 4: USB controller Philips ISP6111
 * 0x77C00000 ... 0x77CFFFFF
 *
 * The chip is connected to:
 * - CPU CS#4
 * - CPU IRQ#2
 * - CPU DMA 3
 *
 * Timing:
 * - command to first data: 300ns. Software must ensure this timing!
 * - Write pulse: 26ns
 * - Read pulse: 33ns
 * - read cycle time: 150ns
 * - write cycle time: 140ns
 *
 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
 *
 *			  |- 300ns --|
 *		  |---- 420ns ---|---- 420ns ---| cycle
 * CS ############:###____#######:###____#######
 * OE ############:####___#######:####___#######
 * WE ############:####__########:####__########
 *
 * ----> 2 clocks RD/WR pulses: 60ns
 * ----> CSN: 3 clock, 90ns
 * ----> OEN: 1 clocks (read cycle)
 * ----> WBN: 1 clocks (write cycle)
 * ----> WBE: 2 clocks
 * ----> TH: 7 clock, 210ns
 * ----> TWT: 7 clocks
 *----------------------------------------------------------------------- */

#ifdef CONFIG_ISP1161_PRESENT

		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x030D
		ori r4,r4,0x5E80
		mtdcr EBC0_CFGDATA,r4

		li r4,PB4CR				/* PB2CR=Peripheral Bank 4 Configuration Register */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x77C1
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4

#endif

#ifndef IDE_USES_ISA_EMULATION

/*-----------------------------------------------------------------------
 * Memory Bank 5 used for IDE access
 *
 * Timings for IDE Interface
 *
 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
 *  70		165		30		PIO-Mode 0, [ns]
 *   3		  6		 1		[Cycles] ----> AP=0x040C0200
 *  50		125		20	   PIO-Mode 1, [ns]
 *   2		  5		 1		[Cycles] ----> AP=0x03080200
 *  30		100		15	   PIO-Mode 2, [ns]
 *   1		  4		 1		[Cycles] ----> AP=0x02040200
 *  30		 80		10	   PIO-Mode 3, [ns]
 *   1		  3		 1		[Cycles] ----> AP=0x01840200
 *  25		 70		10	   PIO-Mode 4, [ns]
 *   1		  3		 1		[Cycles] ----> AP=0x01840200
 *
 *----------------------------------------------------------------------- */

		li r4,PB5AP
		mtdcr EBC0_CFGADDR,r4
		lis r4,0x040C
		ori r4,r4,0x0200
		mtdcr EBC0_CFGDATA,r4

		li r4,PB5CR			/* PB2CR=Peripheral Bank 2 Configuration Register */
		mtdcr EBC0_CFGADDR,r4

		lis r4,0x7A01
		ori r4,r4,0xA000
		mtdcr EBC0_CFGDATA,r4
#endif
/*
 * External Peripheral Control Register
 */
		li r4,EBC0_CFG
		mtdcr EBC0_CFGADDR,r4

		lis r4,0xB84E
		ori r4,r4,0xF000
		mtdcr EBC0_CFGDATA,r4
/*
 * drive POST code
 */
		lis r4,0x7900
		ori r4,r4,0x0080
		li r3,0x0001
		stb r3,0(r4)			/* 01 -> external bus controller is initialized */
		nop				/* pass2 DCR errata #8 */
		blr
Commit	Line	Data
ca43ba18 HS	1	/*------------------------------------------------------------------------------+
ca43ba18 HS	2	*
f11033e7 WD	3	* This souce code has been made available to you by EuroDesign
	4	* (www.eurodsn.de). It's based on the original IBM source code, so
	5	* this follows:
ca43ba18	6	*
31773496 JB	7	* This source code is dual-licensed. You may use it under the terms of the
	8	* GNU General Public License version 2, or under the license below.
	9	*
f11033e7 WD	10	* This source code has been made available to you by IBM on an AS-IS
	11	* basis. Anyone receiving this source is licensed under IBM
	12	* copyrights to use it in any way he or she deems fit, including
	13	* copying it, modifying it, compiling it, and redistributing it either
	14	* with or without modifications. No license under IBM patents or
	15	* patent applications is to be implied by the copyright license.
ca43ba18	16	*
f11033e7 WD	17	* Any user of this software should understand that IBM cannot provide
	18	* technical support for this software and will not be responsible for
	19	* any consequences resulting from the use of this software.
ca43ba18	20	*
f11033e7 WD	21	* Any person who transfers this source code or any derivative work
	22	* must include the IBM copyright notice, this paragraph, and the
	23	* preceding two paragraphs in the transferred software.
ca43ba18	24	*
f11033e7 WD	25	* COPYRIGHT I B M CORPORATION 1995
f11033e7 WD	26	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
ca43ba18 HS	27	------------------------------------------------------------------------------- /
	28
	29	#include <config.h>
b36df561	30	#include <asm/ppc4xx.h>
ca43ba18 HS	31
	32	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	33
	34	#include <ppc_asm.tmpl>
	35	#include <ppc_defs.h>
	36
	37	#include <asm/cache.h>
	38	#include <asm/mmu.h>
	39
	40	/**
	41	* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
	42	*
	43	* IMPORTANT: For pass1 this code must run from cache since you can not
	44	* reliably change a peripheral banks timing register (pbxap) while running
	45	* code from that bank. For ex., since we are running from ROM on bank 0, we
	46	* can NOT execute the code that modifies bank 0 timings from ROM, so
	47	* we run it from cache.
	48	*
	49	* Bank 0 - Boot-Flash
	50	* Bank 1 - NAND-Flash
	51	* Bank 2 - ISA bus
	52	* Bank 3 - Second Flash
	53	* Bank 4 - USB controller
	54	*/
	55	.globl ext_bus_cntlr_init
	56	ext_bus_cntlr_init:
	57	/*
	58	* We need the current boot up configuration to set correct
	59	* timings into internal flash and external flash
	60	*/
d1c3b275	61	mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
f11033e7 WD	62	0 0 -> 8 bit external ROM
f11033e7 WD	63	0 1 -> 16 bit internal ROM */
ca43ba18 HS	64	addi r4,0,2
	65	srw r24,r24,r4 /* shift right r24 two positions */
	66	andi. r24,r24,0x06000
f11033e7	67	/*
ca43ba18 HS	68	* All calculations are based on 33MHz EBC clock.
	69	*
	70	* First, create a "very slow" timing (~250ns) with burst mode enabled
	71	* This is need for the external flash access
	72	*/
	73	lis r25,0x0800
	74	ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
	75	/*
	76	* Second, create a fast timing:
	77	* 90ns first cycle - 3 clock access
	78	* and 90ns burst cycle, plus 1 clock after the last access
	79	* This is used for the internal access
	80	*/
	81	lis r26,0x8900
	82	ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
	83	/*
	84	* We can't change settings on CS# if we currently use them.
	85	* -> load a few instructions into cache and run this code from cache
	86	*/
	87	mflr r4 /* save link register */
	88	bl ..getAddr
	89	..getAddr:
	90	mflr r3 /* get address of ..getAddr */
	91	mtlr r4 /* restore link register */
	92	addi r4,0,14 /* set ctr to 10; used to prefetch */
	93	mtctr r4 /* 10 cache lines to fit this function
	94	in cache (gives us 8x10=80 instructions) */
	95	..ebcloop:
	96	icbt r0,r3 /* prefetch cache line for addr in r3 */
	97	addi r3,r3,32 /* move to next cache line */
	98	bdnz ..ebcloop /* continue for 10 cache lines */
	99	/*
	100	* Delay to ensure all accesses to ROM are complete before changing
	101	* bank 0 timings. 200usec should be enough.
	102	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	103	*/
	104	lis r3,0x0
	105	ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
	106	mtctr r3
	107	..spinlp:
	108	bdnz ..spinlp /* spin loop */
	109
	110	/*-----------------------------------------------------------------------
	111	* Memory Bank 0 (BOOT-ROM) initialization
	112	* 0xFFEF00000....0xFFFFFFF
	113	* We only have to change the timing. Mapping is ok by boot-strapping
	114	----------------------------------------------------------------------- /
	115
d1c3b275 SR	116	li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
d1c3b275 SR	117	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	118
	119	mr r4,r26 /* assume internal fast flash is boot flash */
	120	cmpwi r24,0x2000 /* assumption true? ... */
	121	beq 1f /* ...yes! */
	122	mr r4,r25 /* ...no, use the slow variant */
	123	mr r25,r26 /* use this for the other flash */
	124	1:
d1c3b275	125	mtdcr EBC0_CFGDATA,r4 /* change timing now */
ca43ba18	126
d1c3b275 SR	127	li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
	128	mtdcr EBC0_CFGADDR,r4
	129	mfdcr r4,EBC0_CFGDATA
ca43ba18 HS	130	lis r3,0x0001
	131	ori r3,r3,0x8000 /* allow reads and writes */
	132	or r4,r4,r3
d1c3b275	133	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	134
ca43ba18 HS	135	/*-----------------------------------------------------------------------
f11033e7	136	* Memory Bank 3 (Second-Flash) initialization
ca43ba18 HS	137	* 0xF0000000...0xF01FFFFF -> 2MB
	138	----------------------------------------------------------------------- /
	139
d1c3b275 SR	140	li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
	141	mtdcr EBC0_CFGADDR,r4
	142	mtdcr EBC0_CFGDATA,r2 /* change timing */
ca43ba18	143
d1c3b275 SR	144	li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
d1c3b275 SR	145	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	146
	147	lis r4,0xF003
	148	ori r4,r4,0x8000
	149	/*
	150	* Consider boot configuration
	151	*/
	152	xori r24,r24,0x2000 /* invert current bus width */
	153	or r4,r4,r24
d1c3b275	154	mtdcr EBC0_CFGDATA,r4
f11033e7	155
ca43ba18 HS	156	/*-----------------------------------------------------------------------
	157	* Memory Bank 1 (NAND-Flash) initialization
	158	* 0x77D00000...0x77DFFFFF -> 1MB
	159	* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
	160	* - the setup time is 0ns
	161	* - the hold time is 15ns
	162	* ->
	163	* - TWT = 0
	164	* - CSN = 0
	165	* - OEN = 0
	166	* - WBN = 0
	167	* - WBF = 0
	168	* - TH = 1
	169	* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
	170	----------------------------------------------------------------------- /
	171
d1c3b275 SR	172	li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
d1c3b275 SR	173	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	174
	175	lis r4,0x0000
	176	ori r4,r4,0x0200
d1c3b275	177	mtdcr EBC0_CFGDATA,r4
ca43ba18	178
d1c3b275 SR	179	li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
d1c3b275 SR	180	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	181
	182	lis r4,0x77D1
	183	ori r4,r4,0x8000
d1c3b275	184	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	185
	186
	187	/* USB init (without acceleration) */
	188	#ifndef CONFIG_ISP1161_PRESENT
d1c3b275 SR	189	li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
d1c3b275 SR	190	mtdcr EBC0_CFGADDR,r4
ca43ba18	191	lis r4,0x0180
f11033e7	192	ori r4,r4,0x5940
d1c3b275	193	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	194	#endif
	195
	196	/*-----------------------------------------------------------------------
	197	* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
	198	* 0x78000000...0x7BFFFFFF -> 64 MB
	199	* Wir arbeiten bei 33 MHz -> 30ns
	200	*-----------------------------------------------------------------------
	201
	202	A7 (ppc notation) or A24 (standard notation) decides about
	203	the type of access:
	204	A7/A24=0 -> memory cycle
f11033e7	205	A7/ /A24=1 -> I/O cycle
ca43ba18	206	*/
d1c3b275 SR	207	li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
d1c3b275 SR	208	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	209	/*
	210	We emulate an ISA access
	211
	212	1. Address active
	213	2. wait 0 EBC clocks -> CSN=0
	214	3. set CS#
	215	4. wait 0 EBC clock -> OEN/WBN=0
	216	5. set OE#/WE#
	217	6. wait 4 clocks (ca. 90ns) and for Ready signal
	218	7. hold for 4 clocks -> TH=4
	219	*/
	220
	221	#if 1
	222	/* faster access to isa-bus */
	223	lis r4,0x0180
	224	ori r4,r4,0x5940
	225	#else
	226	lis r4,0x0100
	227	ori r4,r4,0x0340
	228	#endif
d1c3b275	229	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	230
ca43ba18 HS	231	#ifdef IDE_USES_ISA_EMULATION
d1c3b275 SR	232	li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
	233	mtdcr EBC0_CFGADDR,r25
	234	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	235	#endif
ca43ba18 HS	236
d1c3b275 SR	237	li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
	238	mtdcr EBC0_CFGADDR,r25
	239	mtdcr EBC0_CFGDATA,r4
	240	li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
	241	mtdcr EBC0_CFGADDR,r25
	242	mtdcr EBC0_CFGDATA,r4
ca43ba18	243
d1c3b275 SR	244	li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
d1c3b275 SR	245	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	246
	247	lis r4,0x780B
	248	ori r4,r4,0xA000
d1c3b275	249	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	250	/*
	251	* the other areas are only 1MiB in size
	252	*/
	253	lis r4,0x7401
	254	ori r4,r4,0xA000
	255
d1c3b275 SR	256	li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
d1c3b275 SR	257	mtdcr EBC0_CFGADDR,r25
ca43ba18	258	lis r4,0x7401
f11033e7	259	ori r4,r4,0xA000
d1c3b275	260	mtdcr EBC0_CFGDATA,r4
ca43ba18	261
d1c3b275 SR	262	li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
d1c3b275 SR	263	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	264	lis r4,0x7411
ca43ba18 HS	265	ori r4,r4,0xA000
d1c3b275	266	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	267
ca43ba18 HS	268	#ifndef CONFIG_ISP1161_PRESENT
d1c3b275 SR	269	li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
d1c3b275 SR	270	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	271	lis r4,0x7421
ca43ba18 HS	272	ori r4,r4,0xA000
d1c3b275	273	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	274	#endif
ca43ba18 HS	275	#ifdef IDE_USES_ISA_EMULATION
d1c3b275 SR	276	li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
d1c3b275 SR	277	mtdcr EBC0_CFGADDR,r25
ca43ba18 HS	278	lis r4,0x0000
ca43ba18 HS	279	ori r4,r4,0x0000
d1c3b275	280	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	281	#endif
	282
	283	/*-----------------------------------------------------------------------
	284	* Memory bank 4: USB controller Philips ISP6111
	285	* 0x77C00000 ... 0x77CFFFFF
	286	*
	287	* The chip is connected to:
	288	* - CPU CS#4
	289	* - CPU IRQ#2
	290	* - CPU DMA 3
	291	*
	292	* Timing:
	293	* - command to first data: 300ns. Software must ensure this timing!
	294	* - Write pulse: 26ns
	295	* - Read pulse: 33ns
	296	* - read cycle time: 150ns
	297	* - write cycle time: 140ns
	298	*
	299	* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
	300	*
f11033e7 WD	301	* \|- 300ns --\|
f11033e7 WD	302	* \|---- 420ns ---\|---- 420ns ---\| cycle
ca43ba18 HS	303	* CS ############:###____#######:###____#######
	304	* OE ############:####___#######:####___#######
	305	* WE ############:####__########:####__########
	306	*
	307	* ----> 2 clocks RD/WR pulses: 60ns
	308	* ----> CSN: 3 clock, 90ns
	309	* ----> OEN: 1 clocks (read cycle)
	310	* ----> WBN: 1 clocks (write cycle)
	311	* ----> WBE: 2 clocks
	312	* ----> TH: 7 clock, 210ns
	313	* ----> TWT: 7 clocks
	314	----------------------------------------------------------------------- /
	315
	316	#ifdef CONFIG_ISP1161_PRESENT
	317
d1c3b275 SR	318	li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
d1c3b275 SR	319	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	320
	321	lis r4,0x030D
	322	ori r4,r4,0x5E80
d1c3b275	323	mtdcr EBC0_CFGDATA,r4
ca43ba18	324
d1c3b275 SR	325	li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
d1c3b275 SR	326	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	327
	328	lis r4,0x77C1
	329	ori r4,r4,0xA000
d1c3b275	330	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	331
	332	#endif
	333
	334	#ifndef IDE_USES_ISA_EMULATION
	335
	336	/*-----------------------------------------------------------------------
	337	* Memory Bank 5 used for IDE access
	338	*
	339	* Timings for IDE Interface
	340	*
	341	* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
	342	* 70 165 30 PIO-Mode 0, [ns]
	343	* 3 6 1 [Cycles] ----> AP=0x040C0200
	344	* 50 125 20 PIO-Mode 1, [ns]
	345	* 2 5 1 [Cycles] ----> AP=0x03080200
	346	* 30 100 15 PIO-Mode 2, [ns]
	347	* 1 4 1 [Cycles] ----> AP=0x02040200
	348	* 30 80 10 PIO-Mode 3, [ns]
	349	* 1 3 1 [Cycles] ----> AP=0x01840200
	350	* 25 70 10 PIO-Mode 4, [ns]
	351	* 1 3 1 [Cycles] ----> AP=0x01840200
	352	*
	353	----------------------------------------------------------------------- /
	354
d1c3b275 SR	355	li r4,PB5AP
d1c3b275 SR	356	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	357	lis r4,0x040C
ca43ba18 HS	358	ori r4,r4,0x0200
d1c3b275	359	mtdcr EBC0_CFGDATA,r4
ca43ba18	360
d1c3b275 SR	361	li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
d1c3b275 SR	362	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	363
	364	lis r4,0x7A01
	365	ori r4,r4,0xA000
d1c3b275	366	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	367	#endif
	368	/*
	369	* External Peripheral Control Register
	370	*/
d1c3b275 SR	371	li r4,EBC0_CFG
d1c3b275 SR	372	mtdcr EBC0_CFGADDR,r4
ca43ba18 HS	373
	374	lis r4,0xB84E
	375	ori r4,r4,0xF000
d1c3b275	376	mtdcr EBC0_CFGDATA,r4
ca43ba18 HS	377	/*
	378	* drive POST code
	379	*/
	380	lis r4,0x7900
	381	ori r4,r4,0x0080
	382	li r3,0x0001
	383	stb r3,0(r4) /* 01 -> external bus controller is initialized */
	384	nop /* pass2 DCR errata #8 */
	385	blr