projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 4e3349b6 MV |
2 | /* |
| 3 | * SchulerControl GmbH, SC_SPS_1 module | |
| 4 | * | |
| 5 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> | |
| 6 | * on behalf of DENX Software Engineering GmbH | |
| 4e3349b6 MV |
7 | */ |
| 8 | ||
| 9 | #include <common.h> | |
| 10 | #include <asm/gpio.h> | |
| 11 | #include <asm/io.h> | |
| 12 | #include <asm/arch/imx-regs.h> | |
| 13 | #include <asm/arch/iomux-mx28.h> | |
| 14 | #include <asm/arch/clock.h> | |
| 15 | #include <asm/arch/sys_proto.h> | |
| 16 | #include <linux/mii.h> | |
| 17 | #include <miiphy.h> | |
| 18 | #include <netdev.h> | |
| 19 | #include <errno.h> | |
| 20 | ||
| 21 | DECLARE_GLOBAL_DATA_PTR; | |
| 22 | ||
| 23 | /* | |
| 24 | * Functions | |
| 25 | */ | |
| 26 | int board_early_init_f(void) | |
| 27 | { | |
| 28 | /* IO0 clock at 480MHz */ | |
| bf48fcb6 | 29 | mxs_set_ioclk(MXC_IOCLK0, 480000); |
| 4e3349b6 | 30 | /* IO1 clock at 480MHz */ |
| bf48fcb6 | 31 | mxs_set_ioclk(MXC_IOCLK1, 480000); |
| 4e3349b6 MV |
32 | |
| 33 | /* SSP0 clock at 96MHz */ | |
| bf48fcb6 | 34 | mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); |
| 4e3349b6 | 35 | /* SSP2 clock at 96MHz */ |
| bf48fcb6 | 36 | mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); |
| 4e3349b6 MV |
37 | |
| 38 | #ifdef CONFIG_CMD_USB | |
| 39 | mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); | |
| 40 | mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | | |
| 41 | MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); | |
| 42 | gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1); | |
| 43 | #endif | |
| 44 | ||
| 45 | return 0; | |
| 46 | } | |
| 47 | ||
| 48 | int board_init(void) | |
| 49 | { | |
| 50 | /* Adress of boot parameters */ | |
| 51 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
| 52 | ||
| 53 | return 0; | |
| 54 | } | |
| 55 | ||
| 56 | int dram_init(void) | |
| 57 | { | |
| 72f8ebf1 | 58 | return mxs_dram_init(); |
| 4e3349b6 MV |
59 | } |
| 60 | ||
| 61 | #ifdef CONFIG_CMD_MMC | |
| 62 | int board_mmc_init(bd_t *bis) | |
| 63 | { | |
| 90bc2bf2 | 64 | return mxsmmc_initialize(bis, 0, NULL, NULL); |
| 4e3349b6 MV |
65 | } |
| 66 | #endif | |
| 67 | ||
| 68 | #ifdef CONFIG_CMD_NET | |
| 69 | int board_eth_init(bd_t *bis) | |
| 70 | { | |
| 38d4a604 OS |
71 | struct mxs_clkctrl_regs *clkctrl_regs = |
| 72 | (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; | |
| 4e3349b6 MV |
73 | int ret; |
| 74 | ||
| 75 | ret = cpu_eth_init(bis); | |
| 76 | ||
| 77 | clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, | |
| 78 | CLKCTRL_ENET_TIME_SEL_MASK, | |
| 79 | CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); | |
| 80 | ||
| 81 | ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); | |
| 82 | if (ret) { | |
| 83 | printf("FEC MXS: Unable to init FEC0\n"); | |
| 84 | return ret; | |
| 85 | } | |
| 86 | ||
| 87 | ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); | |
| 88 | if (ret) { | |
| 89 | printf("FEC MXS: Unable to init FEC1\n"); | |
| 90 | return ret; | |
| 91 | } | |
| 92 | ||
| 93 | return ret; | |
| 94 | } | |
| 95 | ||
| 96 | #endif |