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1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ioports.h> | |
26 | #include <mpc8260.h> | |
27 | ||
28 | #include "scm.h" | |
29 | ||
30 | static void config_scoh_cs(void); | |
31 | extern int fpga_init(void); | |
32 | ||
33 | #if 0 | |
34 | #define DEBUGF(fmt,args...) printf (fmt ,##args) | |
35 | #else | |
36 | #define DEBUGF(fmt,args...) | |
37 | #endif | |
38 | ||
39 | /* | |
40 | * I/O Port configuration table | |
41 | * | |
42 | * if conf is 1, then that port pin will be configured at boot time | |
43 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
44 | */ | |
45 | ||
46 | const iop_conf_t iop_conf_tab[4][32] = { | |
47 | ||
48 | /* Port A configuration */ | |
49 | { /* conf ppar psor pdir podr pdat */ | |
50 | /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ | |
51 | /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ | |
52 | /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ | |
53 | /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ | |
54 | /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ | |
55 | /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ | |
56 | /* PA25 */ { 0, 0, 0, 1, 0, 0 }, | |
57 | /* PA24 */ { 0, 0, 0, 1, 0, 0 }, | |
58 | /* PA23 */ { 0, 0, 0, 1, 0, 0 }, | |
59 | /* PA22 */ { 0, 0, 0, 1, 0, 0 }, | |
60 | /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ | |
61 | /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ | |
62 | /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ | |
63 | /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ | |
64 | /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ | |
65 | /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/ | |
66 | /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ | |
67 | /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ | |
68 | /* PA13 */ { 0, 0, 0, 1, 0, 0 }, | |
69 | /* PA12 */ { 0, 0, 0, 1, 0, 0 }, | |
70 | /* PA11 */ { 0, 0, 0, 1, 0, 0 }, | |
71 | /* PA10 */ { 0, 0, 0, 1, 0, 0 }, | |
72 | /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */ | |
73 | /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */ | |
74 | /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */ | |
75 | /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */ | |
76 | /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */ | |
77 | /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */ | |
78 | /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */ | |
79 | /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */ | |
80 | /* PA1 */ { 0, 0, 0, 1, 0, 0 }, | |
81 | /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */ | |
82 | }, | |
83 | ||
84 | /* Port B configuration */ | |
85 | { /* conf ppar psor pdir podr pdat */ | |
86 | /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */ | |
87 | /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */ | |
88 | /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */ | |
89 | /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */ | |
90 | /* PB27 */ { 0, 1, 0, 0, 0, 0 }, | |
91 | /* PB26 */ { 0, 1, 0, 0, 0, 0 }, | |
92 | /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */ | |
93 | /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */ | |
94 | /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */ | |
95 | /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */ | |
96 | /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */ | |
97 | /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */ | |
98 | /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */ | |
99 | /* PB18 */ { 0, 1, 0, 0, 0, 0 }, | |
8bde7f77 WD |
100 | /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ |
101 | /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ | |
102 | /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ | |
103 | /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ | |
104 | /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ | |
105 | /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ | |
106 | /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ | |
107 | /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ | |
108 | /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ | |
109 | /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ | |
110 | /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ | |
111 | /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ | |
112 | /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ | |
113 | /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ | |
f8cac651 WD |
114 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
115 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
116 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
117 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
118 | }, | |
119 | ||
120 | /* Port C configuration */ | |
121 | { /* conf ppar psor pdir podr pdat */ | |
122 | /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */ | |
123 | /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */ | |
124 | /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */ | |
125 | /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */ | |
126 | /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */ | |
127 | /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */ | |
128 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, | |
129 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, | |
130 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, | |
131 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, | |
132 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ | |
133 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ | |
134 | /* PC19 */ { 0, 1, 0, 0, 0, 0 }, | |
135 | /* PC18 */ { 0, 1, 0, 0, 0, 0 }, | |
8bde7f77 WD |
136 | /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ |
137 | /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ | |
f8cac651 WD |
138 | /* PC15 */ { 0, 0, 0, 1, 0, 0 }, |
139 | /* PC14 */ { 0, 1, 0, 0, 0, 0 }, | |
140 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */ | |
141 | /* PC12 */ { 0, 0, 0, 1, 0, 0 }, | |
142 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, | |
143 | /* PC10 */ { 0, 0, 0, 1, 0, 0 }, | |
144 | /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */ | |
145 | /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */ | |
146 | /* PC7 */ { 0, 0, 0, 0, 0, 0 }, | |
147 | /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */ | |
148 | /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */ | |
149 | /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */ | |
150 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */ | |
151 | /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */ | |
152 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */ | |
153 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */ | |
154 | }, | |
155 | ||
156 | /* Port D configuration */ | |
157 | { /* conf ppar psor pdir podr pdat */ | |
158 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
159 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
160 | /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */ | |
161 | /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */ | |
162 | /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */ | |
163 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */ | |
164 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, | |
165 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, | |
166 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, | |
167 | /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */ | |
168 | /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */ | |
169 | /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ | |
170 | /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */ | |
171 | /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */ | |
172 | /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */ | |
173 | /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */ | |
174 | #if defined(CONFIG_SOFT_I2C) | |
175 | /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ | |
176 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ | |
177 | #else | |
178 | #if defined(CONFIG_HARD_I2C) | |
179 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
180 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
181 | #else /* normal I/O port pins */ | |
182 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
183 | /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
184 | #endif | |
185 | #endif | |
186 | /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */ | |
187 | /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */ | |
188 | /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */ | |
189 | /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */ | |
190 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
191 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
192 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, | |
193 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, | |
194 | /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */ | |
195 | /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */ | |
196 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
197 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
198 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
199 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
200 | } | |
201 | }; | |
202 | ||
203 | /* ------------------------------------------------------------------------- */ | |
204 | ||
205 | /* Check Board Identity: | |
206 | */ | |
207 | int checkboard (void) | |
208 | { | |
77ddac94 | 209 | char str[64]; |
f8cac651 WD |
210 | int i = getenv_r ("serial#", str, sizeof (str)); |
211 | ||
212 | puts ("Board: "); | |
213 | ||
214 | if (!i || strncmp (str, "TQM8260", 7)) { | |
215 | puts ("### No HW ID - assuming TQM8260\n"); | |
216 | return (0); | |
217 | } | |
218 | ||
219 | puts (str); | |
220 | putc ('\n'); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | /* ------------------------------------------------------------------------- */ | |
226 | ||
227 | /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
228 | * | |
229 | * This routine performs standard 8260 initialization sequence | |
230 | * and calculates the available memory size. It may be called | |
231 | * several times to try different SDRAM configurations on both | |
232 | * 60x and local buses. | |
233 | */ | |
234 | static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, | |
235 | ulong orx, volatile uchar * base) | |
236 | { | |
237 | volatile uchar c = 0xff; | |
f8cac651 WD |
238 | volatile uint *sdmr_ptr; |
239 | volatile uint *orx_ptr; | |
c83bf6a2 | 240 | ulong maxsize, size; |
f8cac651 | 241 | int i; |
f8cac651 WD |
242 | |
243 | /* We must be able to test a location outsize the maximum legal size | |
244 | * to find out THAT we are outside; but this address still has to be | |
245 | * mapped by the controller. That means, that the initial mapping has | |
246 | * to be (at least) twice as large as the maximum expected size. | |
247 | */ | |
248 | maxsize = (1 + (~orx | 0x7fff)) / 2; | |
249 | ||
250 | /* Since CFG_SDRAM_BASE is always 0 (??), we assume that | |
251 | * we are configuring CS1 if base != 0 | |
252 | */ | |
253 | sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; | |
254 | orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; | |
255 | ||
256 | *orx_ptr = orx; | |
257 | ||
258 | /* | |
259 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
260 | * | |
261 | * "At system reset, initialization software must set up the | |
262 | * programmable parameters in the memory controller banks registers | |
263 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
264 | * system software should execute the following initialization sequence | |
265 | * for each SDRAM device. | |
266 | * | |
267 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
268 | * 2. Issue eight CBR REFRESH commands | |
269 | * 3. Issue a MODE-SET command to initialize the mode register | |
270 | * | |
271 | * The initial commands are executed by setting P/LSDMR[OP] and | |
272 | * accessing the SDRAM with a single-byte transaction." | |
273 | * | |
274 | * The appropriate BRx/ORx registers have already been set when we | |
275 | * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. | |
276 | */ | |
277 | ||
278 | *sdmr_ptr = sdmr | PSDMR_OP_PREA; | |
279 | *base = c; | |
280 | ||
281 | *sdmr_ptr = sdmr | PSDMR_OP_CBRR; | |
282 | for (i = 0; i < 8; i++) | |
283 | *base = c; | |
284 | ||
285 | *sdmr_ptr = sdmr | PSDMR_OP_MRW; | |
286 | *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ | |
287 | ||
288 | *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
289 | *base = c; | |
290 | ||
c83bf6a2 | 291 | size = get_ram_size((long *)base, maxsize); |
f8cac651 | 292 | |
c83bf6a2 | 293 | *orx_ptr = orx | ~(size - 1); |
f8cac651 | 294 | |
c83bf6a2 | 295 | return (size); |
f8cac651 WD |
296 | } |
297 | ||
298 | /* | |
299 | * Test Power-On-Reset. | |
300 | */ | |
301 | int power_on_reset (void) | |
302 | { | |
303 | DECLARE_GLOBAL_DATA_PTR; | |
304 | ||
305 | /* Test Reset Status Register */ | |
306 | return gd->reset_status & RSR_CSRS ? 0 : 1; | |
307 | } | |
308 | ||
309 | long int initdram (int board_type) | |
310 | { | |
311 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
312 | volatile memctl8260_t *memctl = &immap->im_memctl; | |
313 | ||
314 | #ifndef CFG_RAMBOOT | |
315 | long size8, size9; | |
316 | #endif | |
317 | long psize, lsize; | |
318 | ||
319 | psize = 16 * 1024 * 1024; | |
320 | lsize = 0; | |
321 | ||
322 | memctl->memc_psrt = CFG_PSRT; | |
323 | memctl->memc_mptpr = CFG_MPTPR; | |
324 | ||
325 | #if 0 /* Just for debugging */ | |
326 | #define prt_br_or(brX,orX) do { \ | |
327 | ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ | |
328 | ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ | |
329 | printf ("\n" \ | |
8bde7f77 | 330 | #brX " 0x%08x " #orX " 0x%08x " \ |
f8cac651 WD |
331 | "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ |
332 | memctl->memc_ ## brX, memctl->memc_ ## orX, \ | |
333 | start, start+sizem, (sizem+1)>>20); \ | |
334 | } while (0) | |
335 | prt_br_or (br0, or0); | |
336 | prt_br_or (br1, or1); | |
337 | prt_br_or (br2, or2); | |
338 | prt_br_or (br3, or3); | |
339 | #endif | |
340 | ||
341 | #ifndef CFG_RAMBOOT | |
342 | /* 60x SDRAM setup: | |
343 | */ | |
344 | size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, | |
345 | (uchar *) CFG_SDRAM_BASE); | |
346 | size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, | |
347 | (uchar *) CFG_SDRAM_BASE); | |
348 | ||
349 | if (size8 < size9) { | |
350 | psize = size9; | |
351 | printf ("(60x:9COL - %ld MB, ", psize >> 20); | |
352 | } else { | |
353 | psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, | |
354 | (uchar *) CFG_SDRAM_BASE); | |
355 | printf ("(60x:8COL - %ld MB, ", psize >> 20); | |
356 | } | |
357 | ||
358 | /* Local SDRAM setup: | |
359 | */ | |
360 | #ifdef CFG_INIT_LOCAL_SDRAM | |
361 | memctl->memc_lsrt = CFG_LSRT; | |
362 | size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, | |
363 | (uchar *) SDRAM_BASE2_PRELIM); | |
364 | size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, | |
365 | (uchar *) SDRAM_BASE2_PRELIM); | |
366 | ||
367 | if (size8 < size9) { | |
368 | lsize = size9; | |
369 | printf ("Local:9COL - %ld MB) using ", lsize >> 20); | |
370 | } else { | |
371 | lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, | |
372 | (uchar *) SDRAM_BASE2_PRELIM); | |
373 | printf ("Local:8COL - %ld MB) using ", lsize >> 20); | |
374 | } | |
375 | ||
376 | #if 0 | |
377 | /* Set up BR2 so that the local SDRAM goes | |
378 | * right after the 60x SDRAM | |
379 | */ | |
380 | memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | | |
381 | (CFG_SDRAM_BASE + psize); | |
382 | #endif | |
383 | #endif /* CFG_INIT_LOCAL_SDRAM */ | |
384 | #endif /* CFG_RAMBOOT */ | |
385 | ||
386 | icache_enable (); | |
387 | ||
388 | config_scoh_cs (); | |
389 | ||
390 | return (psize); | |
391 | } | |
392 | ||
393 | /* ------------------------------------------------------------------------- */ | |
394 | ||
395 | static void config_scoh_cs (void) | |
396 | { | |
397 | volatile immap_t *immr = (immap_t *) CFG_IMMR; | |
398 | volatile memctl8260_t *memctl = &immr->im_memctl; | |
399 | volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; | |
400 | volatile uint tmp, i; | |
401 | ||
402 | /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ | |
403 | memctl->memc_or3 = CFG_CAN0_OR3; | |
404 | memctl->memc_br3 = CFG_CAN0_BR3; | |
405 | /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ | |
406 | memctl->memc_or4 = CFG_CAN1_OR4; | |
407 | memctl->memc_br4 = CFG_CAN1_BR4; | |
408 | ||
409 | /* Initialize MAMR to write in the array at address 0x0 */ | |
410 | memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; | |
411 | ||
412 | /* Initialize UPMA for CAN: single read */ | |
413 | memctl->memc_mdr = 0xcffeec00; | |
414 | udelay (1); /* Necessary to have the data correct in the UPM array!!!! */ | |
415 | /* The read on the CAN controller write the data of mdr in UPMA array. */ | |
416 | /* The index to the array will be incremented automatically | |
417 | through this read */ | |
418 | tmp = can->cpu_interface; | |
419 | ||
420 | memctl->memc_mdr = 0x0ffcec00; | |
421 | udelay (1); | |
422 | tmp = can->cpu_interface; | |
423 | ||
424 | memctl->memc_mdr = 0x0ffcec00; | |
425 | udelay (1); | |
426 | tmp = can->cpu_interface; | |
427 | ||
428 | memctl->memc_mdr = 0x0ffcec00; | |
429 | udelay (1); | |
430 | tmp = can->cpu_interface; | |
431 | ||
432 | memctl->memc_mdr = 0x0ffcec00; | |
433 | udelay (1); | |
434 | tmp = can->cpu_interface; | |
435 | ||
436 | memctl->memc_mdr = 0x0ffcfc00; | |
437 | udelay (1); | |
438 | tmp = can->cpu_interface; | |
439 | ||
440 | memctl->memc_mdr = 0x0ffcfc00; | |
441 | udelay (1); | |
442 | tmp = can->cpu_interface; | |
443 | ||
444 | memctl->memc_mdr = 0xfffdec07; | |
445 | udelay (1); | |
446 | tmp = can->cpu_interface; | |
447 | ||
448 | ||
449 | /* Initialize MAMR to write in the array at address 0x18 */ | |
450 | memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS; | |
451 | ||
452 | /* Initialize UPMA for CAN: single write */ | |
453 | memctl->memc_mdr = 0xfcffec00; | |
454 | udelay (1); | |
455 | tmp = can->cpu_interface; | |
456 | ||
457 | memctl->memc_mdr = 0x00ffec00; | |
458 | udelay (1); | |
459 | tmp = can->cpu_interface; | |
460 | ||
461 | memctl->memc_mdr = 0x00ffec00; | |
462 | udelay (1); | |
463 | tmp = can->cpu_interface; | |
464 | ||
465 | memctl->memc_mdr = 0x00ffec00; | |
466 | udelay (1); | |
467 | tmp = can->cpu_interface; | |
468 | ||
469 | memctl->memc_mdr = 0x00ffec00; | |
470 | udelay (1); | |
471 | tmp = can->cpu_interface; | |
472 | ||
473 | memctl->memc_mdr = 0x00fffc00; | |
474 | udelay (1); | |
475 | tmp = can->cpu_interface; | |
476 | ||
477 | memctl->memc_mdr = 0x00fffc00; | |
478 | udelay (1); | |
479 | tmp = can->cpu_interface; | |
480 | ||
481 | memctl->memc_mdr = 0x30ffec07; | |
482 | udelay (1); | |
483 | tmp = can->cpu_interface; | |
484 | ||
485 | /* Initialize MAMR */ | |
486 | memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */ | |
487 | ||
488 | ||
489 | /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ | |
490 | memctl->memc_or5 = CFG_EXTPROM_OR5; | |
491 | memctl->memc_br5 = CFG_EXTPROM_BR5; | |
492 | /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ | |
493 | memctl->memc_or6 = CFG_EXTPROM_OR6; | |
494 | memctl->memc_br6 = CFG_EXTPROM_BR6; | |
495 | ||
496 | /* Initialize OR7 / BR7 for the Glue Logic */ | |
497 | memctl->memc_or7 = CFG_FIOX_OR7; | |
498 | memctl->memc_br7 = CFG_FIOX_BR7; | |
499 | ||
500 | /* Initialize OR8 / BR8 for the DOH Logic */ | |
501 | memctl->memc_or8 = CFG_FDOHM_OR8; | |
502 | memctl->memc_br8 = CFG_FDOHM_BR8; | |
503 | ||
504 | DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); | |
505 | DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); | |
506 | DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2); | |
507 | DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3); | |
508 | DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4); | |
509 | DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5); | |
510 | DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6); | |
511 | DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7); | |
512 | DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8); | |
513 | ||
514 | DEBUGF ("UPMA addr 0x0\n"); | |
515 | memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS; | |
516 | for (i = 0; i < 0x8; i++) { | |
517 | tmp = can->cpu_interface; | |
518 | udelay (1); | |
519 | DEBUGF (" %08x ", memctl->memc_mdr); | |
520 | } | |
521 | DEBUGF ("\nUPMA addr 0x18\n"); | |
522 | memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS; | |
523 | for (i = 0; i < 0x8; i++) { | |
524 | tmp = can->cpu_interface; | |
525 | udelay (1); | |
526 | DEBUGF (" %08x ", memctl->memc_mdr); | |
527 | } | |
528 | DEBUGF ("\n"); | |
529 | memctl->memc_mamr = MxMR_GPL_x4DIS; | |
530 | } | |
531 | ||
532 | /* ------------------------------------------------------------------------- */ | |
533 | ||
534 | int misc_init_r (void) | |
535 | { | |
536 | fpga_init (); | |
537 | return (0); | |
538 | } | |
539 | ||
540 | /* ------------------------------------------------------------------------- */ |