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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c0dcece7 | 2 | /* |
820969f3 | 3 | * Board functions for TI AM335X based draco board |
c0dcece7 HS |
4 | * (C) Copyright 2013 Siemens Schweiz AG |
5 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
6 | * | |
7 | * Based on: | |
8 | * | |
9 | * Board functions for TI AM335X based boards | |
10 | * u-boot:/board/ti/am335x/board.c | |
11 | * | |
12 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
c0dcece7 HS |
13 | */ |
14 | ||
15 | #include <common.h> | |
09140113 | 16 | #include <command.h> |
9fb625ce | 17 | #include <env.h> |
c0dcece7 | 18 | #include <errno.h> |
5255932f | 19 | #include <init.h> |
90526e9f | 20 | #include <net.h> |
c0dcece7 HS |
21 | #include <spl.h> |
22 | #include <asm/arch/cpu.h> | |
23 | #include <asm/arch/hardware.h> | |
24 | #include <asm/arch/omap.h> | |
25 | #include <asm/arch/ddr_defs.h> | |
26 | #include <asm/arch/clock.h> | |
27 | #include <asm/arch/gpio.h> | |
28 | #include <asm/arch/mmc_host_def.h> | |
29 | #include <asm/arch/sys_proto.h> | |
6b3943f1 | 30 | #include <asm/arch/mem.h> |
c0dcece7 HS |
31 | #include <asm/io.h> |
32 | #include <asm/emif.h> | |
33 | #include <asm/gpio.h> | |
34 | #include <i2c.h> | |
35 | #include <miiphy.h> | |
36 | #include <cpsw.h> | |
37 | #include <watchdog.h> | |
38 | #include "board.h" | |
39 | #include "../common/factoryset.h" | |
6b3943f1 | 40 | #include <nand.h> |
c0dcece7 | 41 | |
c0dcece7 | 42 | #ifdef CONFIG_SPL_BUILD |
820969f3 | 43 | static struct draco_baseboard_id __attribute__((section(".data"))) settings; |
823b2c4c ES |
44 | |
45 | #if DDR_PLL_FREQ == 303 | |
6b3943f1 | 46 | #if !defined(CONFIG_TARGET_ETAMIN) |
823b2c4c ES |
47 | /* Default@303MHz-i0 */ |
48 | const struct ddr3_data ddr3_default = { | |
49 | 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, | |
61159b76 | 50 | 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32, |
823b2c4c ES |
51 | 0x0000093B, 0x0000014A, |
52 | "default name @303MHz \0", | |
53 | "default marking \0", | |
54 | }; | |
6b3943f1 HS |
55 | #else |
56 | /* etamin board */ | |
57 | const struct ddr3_data ddr3_default = { | |
58 | 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F, | |
59 | 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2, | |
60 | 0x0000093B, 0x0000018A, | |
61 | "test-etamin \0", | |
62 | "generic-8Gbit \0", | |
63 | }; | |
64 | #endif | |
823b2c4c ES |
65 | #elif DDR_PLL_FREQ == 400 |
66 | /* Default@400MHz-i0 */ | |
c0dcece7 | 67 | const struct ddr3_data ddr3_default = { |
823b2c4c ES |
68 | 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, |
69 | 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, | |
56eb3da4 | 70 | 0x00000618, 0x0000014A, |
823b2c4c ES |
71 | "default name @400MHz \0", |
72 | "default marking \0", | |
c0dcece7 | 73 | }; |
823b2c4c | 74 | #endif |
c0dcece7 HS |
75 | |
76 | static void set_default_ddr3_timings(void) | |
77 | { | |
78 | printf("Set default DDR3 settings\n"); | |
79 | settings.ddr3 = ddr3_default; | |
80 | } | |
81 | ||
82 | static void print_ddr3_timings(void) | |
83 | { | |
823b2c4c ES |
84 | printf("\nDDR3\n"); |
85 | printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); | |
86 | printf("device:\t\t%s\n", settings.ddr3.manu_name); | |
87 | printf("marking:\t%s\n", settings.ddr3.manu_marking); | |
61159b76 HS |
88 | printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom", |
89 | "default", "diff"); | |
c0dcece7 HS |
90 | PRINTARGS(magic); |
91 | PRINTARGS(version); | |
92 | PRINTARGS(ddr3_sratio); | |
93 | PRINTARGS(iclkout); | |
94 | ||
95 | PRINTARGS(dt0rdsratio0); | |
96 | PRINTARGS(dt0wdsratio0); | |
97 | PRINTARGS(dt0fwsratio0); | |
98 | PRINTARGS(dt0wrsratio0); | |
99 | ||
100 | PRINTARGS(sdram_tim1); | |
101 | PRINTARGS(sdram_tim2); | |
102 | PRINTARGS(sdram_tim3); | |
103 | ||
104 | PRINTARGS(emif_ddr_phy_ctlr_1); | |
105 | ||
106 | PRINTARGS(sdram_config); | |
107 | PRINTARGS(ref_ctrl); | |
56eb3da4 | 108 | PRINTARGS(ioctr_val); |
c0dcece7 HS |
109 | } |
110 | ||
111 | static void print_chip_data(void) | |
112 | { | |
61159b76 HS |
113 | struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
114 | dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); | |
823b2c4c ES |
115 | printf("\nCPU BOARD\n"); |
116 | printf("device: \t'%s'\n", settings.chip.sdevname); | |
117 | printf("hw version: \t'%s'\n", settings.chip.shwver); | |
61159b76 | 118 | printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m); |
c0dcece7 HS |
119 | } |
120 | #endif /* CONFIG_SPL_BUILD */ | |
121 | ||
02b11f11 HS |
122 | #define AM335X_NAND_ECC_MASK 0x0f |
123 | #define AM335X_NAND_ECC_TYPE_16 0x02 | |
124 | ||
125 | static int ecc_type; | |
126 | ||
127 | struct am335x_nand_geometry { | |
128 | u32 magic; | |
129 | u8 nand_geo_addr; | |
130 | u8 nand_geo_page; | |
131 | u8 nand_bus; | |
132 | }; | |
133 | ||
134 | static int draco_read_nand_geometry(void) | |
135 | { | |
136 | struct am335x_nand_geometry geo; | |
137 | ||
138 | /* Read NAND geometry */ | |
139 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2, | |
140 | (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { | |
141 | printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); | |
142 | return -EIO; | |
143 | } | |
144 | if (geo.magic != 0xa657b310) { | |
145 | printf("%s: bad magic: %x\n", __func__, geo.magic); | |
146 | return -EFAULT; | |
147 | } | |
148 | if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16) | |
149 | ecc_type = 16; | |
150 | else | |
151 | ecc_type = 8; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
c0dcece7 HS |
156 | /* |
157 | * Read header information from EEPROM into global structure. | |
158 | */ | |
159 | static int read_eeprom(void) | |
160 | { | |
161 | /* Check if baseboard eeprom is available */ | |
162 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { | |
163 | printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); | |
164 | return 1; | |
165 | } | |
166 | ||
167 | #ifdef CONFIG_SPL_BUILD | |
168 | /* Read Siemens eeprom data (DDR3) */ | |
169 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, | |
170 | (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { | |
171 | printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); | |
172 | set_default_ddr3_timings(); | |
173 | } | |
174 | /* Read Siemens eeprom data (CHIP) */ | |
175 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, | |
176 | (uchar *)&settings.chip, sizeof(settings.chip))) | |
177 | printf("Could not read chip settings\n"); | |
178 | ||
179 | if (ddr3_default.magic == settings.ddr3.magic && | |
180 | ddr3_default.version == settings.ddr3.version) { | |
181 | printf("Using DDR3 settings from EEPROM\n"); | |
182 | } else { | |
183 | if (ddr3_default.magic != settings.ddr3.magic) | |
823b2c4c | 184 | printf("Warning: No valid DDR3 data in eeprom.\n"); |
c0dcece7 | 185 | if (ddr3_default.version != settings.ddr3.version) |
823b2c4c | 186 | printf("Warning: DDR3 data version does not match.\n"); |
c0dcece7 HS |
187 | |
188 | printf("Using default settings\n"); | |
189 | set_default_ddr3_timings(); | |
190 | } | |
191 | ||
820969f3 | 192 | if (MAGIC_CHIP == settings.chip.magic) |
c0dcece7 | 193 | print_chip_data(); |
820969f3 | 194 | else |
823b2c4c | 195 | printf("Warning: No chip data in eeprom\n"); |
c0dcece7 HS |
196 | |
197 | print_ddr3_timings(); | |
02b11f11 HS |
198 | |
199 | return draco_read_nand_geometry(); | |
c0dcece7 HS |
200 | #endif |
201 | return 0; | |
202 | } | |
203 | ||
204 | #ifdef CONFIG_SPL_BUILD | |
205 | static void board_init_ddr(void) | |
206 | { | |
820969f3 | 207 | struct emif_regs draco_ddr3_emif_reg_data = { |
c0dcece7 HS |
208 | .zq_config = 0x50074BE4, |
209 | }; | |
210 | ||
820969f3 | 211 | struct ddr_data draco_ddr3_data = { |
c0dcece7 HS |
212 | }; |
213 | ||
820969f3 | 214 | struct cmd_control draco_ddr3_cmd_ctrl_data = { |
c0dcece7 | 215 | }; |
965de8b9 | 216 | |
820969f3 | 217 | struct ctrl_ioregs draco_ddr3_ioregs = { |
965de8b9 LV |
218 | }; |
219 | ||
c0dcece7 | 220 | /* pass values from eeprom */ |
820969f3 ES |
221 | draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; |
222 | draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; | |
223 | draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; | |
224 | draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = | |
c0dcece7 | 225 | settings.ddr3.emif_ddr_phy_ctlr_1; |
820969f3 | 226 | draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; |
6b3943f1 | 227 | draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000; |
820969f3 ES |
228 | draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; |
229 | ||
230 | draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; | |
231 | draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; | |
232 | draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; | |
233 | draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; | |
234 | ||
235 | draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; | |
236 | draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; | |
237 | draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; | |
238 | draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; | |
239 | draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; | |
240 | draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; | |
241 | ||
242 | draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, | |
243 | draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, | |
244 | draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, | |
245 | draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, | |
246 | draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, | |
247 | ||
248 | config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, | |
249 | &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); | |
c0dcece7 HS |
250 | } |
251 | ||
252 | static void spl_siemens_board_init(void) | |
253 | { | |
254 | return; | |
255 | } | |
256 | #endif /* if def CONFIG_SPL_BUILD */ | |
257 | ||
61159b76 HS |
258 | #ifdef CONFIG_BOARD_LATE_INIT |
259 | int board_late_init(void) | |
260 | { | |
02b11f11 HS |
261 | int ret; |
262 | ||
263 | ret = draco_read_nand_geometry(); | |
264 | if (ret != 0) | |
265 | return ret; | |
266 | ||
267 | nand_curr_device = 0; | |
268 | omap_nand_switch_ecc(1, ecc_type); | |
6b3943f1 HS |
269 | #ifdef CONFIG_TARGET_ETAMIN |
270 | nand_curr_device = 1; | |
271 | omap_nand_switch_ecc(1, ecc_type); | |
272 | #endif | |
61159b76 HS |
273 | #ifdef CONFIG_FACTORYSET |
274 | /* Set ASN in environment*/ | |
275 | if (factory_dat.asn[0] != 0) { | |
382bee57 | 276 | env_set("dtb_name", (char *)factory_dat.asn); |
61159b76 HS |
277 | } else { |
278 | /* dtb suffix gets added in load script */ | |
382bee57 | 279 | env_set("dtb_name", "am335x-draco"); |
61159b76 HS |
280 | } |
281 | #else | |
382bee57 | 282 | env_set("dtb_name", "am335x-draco"); |
61159b76 HS |
283 | #endif |
284 | ||
285 | return 0; | |
286 | } | |
287 | #endif | |
288 | ||
c0dcece7 HS |
289 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
290 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
291 | static void cpsw_control(int enabled) | |
292 | { | |
293 | /* VTP can be added here */ | |
294 | ||
295 | return; | |
296 | } | |
297 | ||
298 | static struct cpsw_slave_data cpsw_slaves[] = { | |
299 | { | |
300 | .slave_reg_ofs = 0x208, | |
301 | .sliver_reg_ofs = 0xd80, | |
9c653aad | 302 | .phy_addr = 0, |
c0dcece7 HS |
303 | .phy_if = PHY_INTERFACE_MODE_MII, |
304 | }, | |
305 | }; | |
306 | ||
307 | static struct cpsw_platform_data cpsw_data = { | |
308 | .mdio_base = CPSW_MDIO_BASE, | |
309 | .cpsw_base = CPSW_BASE, | |
310 | .mdio_div = 0xff, | |
311 | .channels = 4, | |
312 | .cpdma_reg_ofs = 0x800, | |
313 | .slaves = 1, | |
314 | .slave_data = cpsw_slaves, | |
315 | .ale_reg_ofs = 0xd00, | |
316 | .ale_entries = 1024, | |
317 | .host_port_reg_ofs = 0x108, | |
318 | .hw_stats_reg_ofs = 0x900, | |
319 | .bd_ram_ofs = 0x2000, | |
320 | .mac_control = (1 << 5), | |
321 | .control = cpsw_control, | |
322 | .host_port_num = 0, | |
323 | .version = CPSW_CTRL_VERSION_2, | |
324 | }; | |
325 | ||
326 | #if defined(CONFIG_DRIVER_TI_CPSW) || \ | |
95de1e2f | 327 | (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) |
c0dcece7 HS |
328 | int board_eth_init(bd_t *bis) |
329 | { | |
330 | struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | |
331 | int n = 0; | |
332 | int rv; | |
333 | ||
382bee57 | 334 | factoryset_env_set(); |
c0dcece7 HS |
335 | |
336 | /* Set rgmii mode and enable rmii clock to be sourced from chip */ | |
337 | writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); | |
338 | ||
339 | rv = cpsw_register(&cpsw_data); | |
340 | if (rv < 0) | |
341 | printf("Error %d registering CPSW switch\n", rv); | |
342 | else | |
343 | n += rv; | |
344 | return n; | |
345 | } | |
ec716e33 | 346 | |
09140113 SG |
347 | static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc, |
348 | char *const argv[]) | |
ec716e33 SR |
349 | { |
350 | /* Reset SMSC LAN9303 switch for default configuration */ | |
351 | gpio_request(GPIO_LAN9303_NRST, "nRST"); | |
352 | gpio_direction_output(GPIO_LAN9303_NRST, 0); | |
353 | /* assert active low reset for 200us */ | |
354 | udelay(200); | |
355 | gpio_set_value(GPIO_LAN9303_NRST, 1); | |
356 | ||
357 | return 0; | |
358 | }; | |
359 | ||
360 | U_BOOT_CMD( | |
361 | switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, | |
362 | "Reset LAN9303 switch via its reset pin", | |
363 | "" | |
364 | ); | |
c0dcece7 HS |
365 | #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ |
366 | #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ | |
367 | ||
6b3943f1 HS |
368 | #ifdef CONFIG_NAND_CS_INIT |
369 | /* GPMC definitions for second nand cs1 */ | |
370 | static const u32 gpmc_nand_config[] = { | |
371 | ETAMIN_NAND_GPMC_CONFIG1, | |
372 | ETAMIN_NAND_GPMC_CONFIG2, | |
373 | ETAMIN_NAND_GPMC_CONFIG3, | |
374 | ETAMIN_NAND_GPMC_CONFIG4, | |
375 | ETAMIN_NAND_GPMC_CONFIG5, | |
376 | ETAMIN_NAND_GPMC_CONFIG6, | |
377 | /*CONFIG7- computed as params */ | |
378 | }; | |
379 | ||
380 | static void board_nand_cs_init(void) | |
381 | { | |
382 | enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1], | |
383 | 0x18000000, GPMC_SIZE_16M); | |
384 | } | |
385 | #endif | |
386 | ||
c0dcece7 | 387 | #include "../common/board.c" |