[people/ms/u-boot.git] / board / siemens / draco / board.c

/*
 * Board functions for TI AM335X based draco board
 * (C) Copyright 2013 Siemens Schweiz AG
 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * Based on:
 *
 * Board functions for TI AM335X based boards
 * u-boot:/board/ti/am335x/board.c
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SPL_BUILD
static struct draco_baseboard_id __attribute__((section(".data"))) settings;

#if DDR_PLL_FREQ == 303
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
	0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
	0x0000093B, 0x0000014A,
	"default name @303MHz           \0",
	"default marking                \0",
};
#elif DDR_PLL_FREQ == 400
/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
	0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
	0x00000618, 0x0000014A,
	"default name @400MHz           \0",
	"default marking                \0",
};
#endif

static void set_default_ddr3_timings(void)
{
	printf("Set default DDR3 settings\n");
	settings.ddr3 = ddr3_default;
}

static void print_ddr3_timings(void)
{
	printf("\nDDR3\n");
	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
	printf("device:\t\t%s\n", settings.ddr3.manu_name);
	printf("marking:\t%s\n", settings.ddr3.manu_marking);
	printf("timing parameters\n");
	printf("diff\teeprom\tdefault\n");
	PRINTARGS(magic);
	PRINTARGS(version);
	PRINTARGS(ddr3_sratio);
	PRINTARGS(iclkout);

	PRINTARGS(dt0rdsratio0);
	PRINTARGS(dt0wdsratio0);
	PRINTARGS(dt0fwsratio0);
	PRINTARGS(dt0wrsratio0);

	PRINTARGS(sdram_tim1);
	PRINTARGS(sdram_tim2);
	PRINTARGS(sdram_tim3);

	PRINTARGS(emif_ddr_phy_ctlr_1);

	PRINTARGS(sdram_config);
	PRINTARGS(ref_ctrl);
	PRINTARGS(ioctr_val);
}

static void print_chip_data(void)
{
	printf("\nCPU BOARD\n");
	printf("device: \t'%s'\n", settings.chip.sdevname);
	printf("hw version: \t'%s'\n", settings.chip.shwver);
}
#endif /* CONFIG_SPL_BUILD */

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(void)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
		return 1;
	}

#ifdef CONFIG_SPL_BUILD
	/* Read Siemens eeprom data (DDR3) */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
		     (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
		printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
		set_default_ddr3_timings();
	}
	/* Read Siemens eeprom data (CHIP) */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
		     (uchar *)&settings.chip, sizeof(settings.chip)))
		printf("Could not read chip settings\n");

	if (ddr3_default.magic == settings.ddr3.magic &&
	    ddr3_default.version == settings.ddr3.version) {
		printf("Using DDR3 settings from EEPROM\n");
	} else {
		if (ddr3_default.magic != settings.ddr3.magic)
			printf("Warning: No valid DDR3 data in eeprom.\n");
		if (ddr3_default.version != settings.ddr3.version)
			printf("Warning: DDR3 data version does not match.\n");

		printf("Using default settings\n");
		set_default_ddr3_timings();
	}

	if (MAGIC_CHIP == settings.chip.magic)
		print_chip_data();
	else
		printf("Warning: No chip data in eeprom\n");

	print_ddr3_timings();
#endif
	return 0;
}

#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs draco_ddr3_emif_reg_data = {
	.zq_config = 0x50074BE4,
};

struct ddr_data draco_ddr3_data = {
};

struct cmd_control draco_ddr3_cmd_ctrl_data = {
};

struct ctrl_ioregs draco_ddr3_ioregs = {
};

	/* pass values from eeprom */
	draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
	draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
	draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
		settings.ddr3.emif_ddr_phy_ctlr_1;
	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;

	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
	draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
	draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
	draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;

	draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
	draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
	draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;

	draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,

	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
		   &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
}

static void spl_siemens_board_init(void)
{
	return;
}
#endif /* if def CONFIG_SPL_BUILD */

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_MII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 4,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
	int n = 0;
	int rv;

	factoryset_setenv();

	/* Set rgmii mode and enable rmii clock to be sourced from chip */
	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
	return n;
}

static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
			   char *const argv[])
{
	/* Reset SMSC LAN9303 switch for default configuration */
	gpio_request(GPIO_LAN9303_NRST, "nRST");
	gpio_direction_output(GPIO_LAN9303_NRST, 0);
	/* assert active low reset for 200us */
	udelay(200);
	gpio_set_value(GPIO_LAN9303_NRST, 1);

	return 0;
};

U_BOOT_CMD(
	switch_rst, CONFIG_SYS_MAXARGS, 1,	do_switch_reset,
	"Reset LAN9303 switch via its reset pin",
	""
);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */

#include "../common/board.c"
Commit	Line	Data
c0dcece7	1	/*
820969f3	2	* Board functions for TI AM335X based draco board
c0dcece7 HS	3	* (C) Copyright 2013 Siemens Schweiz AG
	4	* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
	5	*
	6	* Based on:
	7	*
	8	* Board functions for TI AM335X based boards
	9	* u-boot:/board/ti/am335x/board.c
	10	*
	11	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	12	*
	13	* SPDX-License-Identifier: GPL-2.0+
	14	*/
	15
	16	#include <common.h>
	17	#include <errno.h>
	18	#include <spl.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/arch/hardware.h>
	21	#include <asm/arch/omap.h>
	22	#include <asm/arch/ddr_defs.h>
	23	#include <asm/arch/clock.h>
	24	#include <asm/arch/gpio.h>
	25	#include <asm/arch/mmc_host_def.h>
	26	#include <asm/arch/sys_proto.h>
	27	#include <asm/io.h>
	28	#include <asm/emif.h>
	29	#include <asm/gpio.h>
	30	#include <i2c.h>
	31	#include <miiphy.h>
	32	#include <cpsw.h>
	33	#include <watchdog.h>
	34	#include "board.h"
	35	#include "../common/factoryset.h"
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
	39	#ifdef CONFIG_SPL_BUILD
820969f3	40	static struct draco_baseboard_id __attribute__((section(".data"))) settings;
823b2c4c ES	41
	42	#if DDR_PLL_FREQ == 303
	43	/* Default@303MHz-i0 */
	44	const struct ddr3_data ddr3_default = {
	45	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
	46	0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
	47	0x0000093B, 0x0000014A,
	48	"default name @303MHz \0",
	49	"default marking \0",
	50	};
	51	#elif DDR_PLL_FREQ == 400
	52	/* Default@400MHz-i0 */
c0dcece7	53	const struct ddr3_data ddr3_default = {
823b2c4c ES	54	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
823b2c4c ES	55	0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
56eb3da4	56	0x00000618, 0x0000014A,
823b2c4c ES	57	"default name @400MHz \0",
823b2c4c ES	58	"default marking \0",
c0dcece7	59	};
823b2c4c	60	#endif
c0dcece7 HS	61
	62	static void set_default_ddr3_timings(void)
	63	{
	64	printf("Set default DDR3 settings\n");
	65	settings.ddr3 = ddr3_default;
	66	}
	67
	68	static void print_ddr3_timings(void)
	69	{
823b2c4c ES	70	printf("\nDDR3\n");
	71	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
	72	printf("device:\t\t%s\n", settings.ddr3.manu_name);
	73	printf("marking:\t%s\n", settings.ddr3.manu_marking);
	74	printf("timing parameters\n");
	75	printf("diff\teeprom\tdefault\n");
c0dcece7 HS	76	PRINTARGS(magic);
	77	PRINTARGS(version);
	78	PRINTARGS(ddr3_sratio);
	79	PRINTARGS(iclkout);
	80
	81	PRINTARGS(dt0rdsratio0);
	82	PRINTARGS(dt0wdsratio0);
	83	PRINTARGS(dt0fwsratio0);
	84	PRINTARGS(dt0wrsratio0);
	85
	86	PRINTARGS(sdram_tim1);
	87	PRINTARGS(sdram_tim2);
	88	PRINTARGS(sdram_tim3);
	89
	90	PRINTARGS(emif_ddr_phy_ctlr_1);
	91
	92	PRINTARGS(sdram_config);
	93	PRINTARGS(ref_ctrl);
56eb3da4	94	PRINTARGS(ioctr_val);
c0dcece7 HS	95	}
	96
	97	static void print_chip_data(void)
	98	{
823b2c4c ES	99	printf("\nCPU BOARD\n");
	100	printf("device: \t'%s'\n", settings.chip.sdevname);
	101	printf("hw version: \t'%s'\n", settings.chip.shwver);
c0dcece7 HS	102	}
	103	#endif /* CONFIG_SPL_BUILD */
	104
	105	/*
	106	* Read header information from EEPROM into global structure.
	107	*/
	108	static int read_eeprom(void)
	109	{
	110	/* Check if baseboard eeprom is available */
	111	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	112	printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
	113	return 1;
	114	}
	115
	116	#ifdef CONFIG_SPL_BUILD
	117	/* Read Siemens eeprom data (DDR3) */
	118	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
	119	(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
	120	printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
	121	set_default_ddr3_timings();
	122	}
	123	/* Read Siemens eeprom data (CHIP) */
	124	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
	125	(uchar *)&settings.chip, sizeof(settings.chip)))
	126	printf("Could not read chip settings\n");
	127
	128	if (ddr3_default.magic == settings.ddr3.magic &&
	129	ddr3_default.version == settings.ddr3.version) {
	130	printf("Using DDR3 settings from EEPROM\n");
	131	} else {
	132	if (ddr3_default.magic != settings.ddr3.magic)
823b2c4c	133	printf("Warning: No valid DDR3 data in eeprom.\n");
c0dcece7	134	if (ddr3_default.version != settings.ddr3.version)
823b2c4c	135	printf("Warning: DDR3 data version does not match.\n");
c0dcece7 HS	136
	137	printf("Using default settings\n");
	138	set_default_ddr3_timings();
	139	}
	140
820969f3	141	if (MAGIC_CHIP == settings.chip.magic)
c0dcece7	142	print_chip_data();
820969f3	143	else
823b2c4c	144	printf("Warning: No chip data in eeprom\n");
c0dcece7 HS	145
	146	print_ddr3_timings();
	147	#endif
	148	return 0;
	149	}
	150
	151	#ifdef CONFIG_SPL_BUILD
	152	static void board_init_ddr(void)
	153	{
820969f3	154	struct emif_regs draco_ddr3_emif_reg_data = {
c0dcece7 HS	155	.zq_config = 0x50074BE4,
	156	};
	157
820969f3	158	struct ddr_data draco_ddr3_data = {
c0dcece7 HS	159	};
c0dcece7 HS	160
820969f3	161	struct cmd_control draco_ddr3_cmd_ctrl_data = {
c0dcece7	162	};
965de8b9	163
820969f3	164	struct ctrl_ioregs draco_ddr3_ioregs = {
965de8b9 LV	165	};
965de8b9 LV	166
c0dcece7	167	/* pass values from eeprom */
820969f3 ES	168	draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
	169	draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
	170	draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
	171	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
c0dcece7	172	settings.ddr3.emif_ddr_phy_ctlr_1;
820969f3 ES	173	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
	174	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
	175
	176	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
	177	draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
	178	draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
	179	draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
	180
	181	draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
	182	draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
	183	draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
	184	draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
	185	draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
	186	draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
	187
	188	draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
	189	draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
	190	draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
	191	draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
	192	draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
	193
	194	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
	195	&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
c0dcece7 HS	196	}
	197
	198	static void spl_siemens_board_init(void)
	199	{
	200	return;
	201	}
	202	#endif /* if def CONFIG_SPL_BUILD */
	203
	204	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	205	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	206	static void cpsw_control(int enabled)
	207	{
	208	/* VTP can be added here */
	209
	210	return;
	211	}
	212
	213	static struct cpsw_slave_data cpsw_slaves[] = {
	214	{
	215	.slave_reg_ofs = 0x208,
	216	.sliver_reg_ofs = 0xd80,
9c653aad	217	.phy_addr = 0,
c0dcece7 HS	218	.phy_if = PHY_INTERFACE_MODE_MII,
	219	},
	220	};
	221
	222	static struct cpsw_platform_data cpsw_data = {
	223	.mdio_base = CPSW_MDIO_BASE,
	224	.cpsw_base = CPSW_BASE,
	225	.mdio_div = 0xff,
	226	.channels = 4,
	227	.cpdma_reg_ofs = 0x800,
	228	.slaves = 1,
	229	.slave_data = cpsw_slaves,
	230	.ale_reg_ofs = 0xd00,
	231	.ale_entries = 1024,
	232	.host_port_reg_ofs = 0x108,
	233	.hw_stats_reg_ofs = 0x900,
	234	.bd_ram_ofs = 0x2000,
	235	.mac_control = (1 << 5),
	236	.control = cpsw_control,
	237	.host_port_num = 0,
	238	.version = CPSW_CTRL_VERSION_2,
	239	};
	240
	241	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
	242	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
	243	int board_eth_init(bd_t *bis)
	244	{
	245	struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	246	int n = 0;
	247	int rv;
	248
	249	factoryset_setenv();
	250
	251	/* Set rgmii mode and enable rmii clock to be sourced from chip */
	252	writel((RMII_MODE_ENABLE \| RMII_CHIPCKL_ENABLE), &cdev->miisel);
	253
	254	rv = cpsw_register(&cpsw_data);
	255	if (rv < 0)
	256	printf("Error %d registering CPSW switch\n", rv);
	257	else
	258	n += rv;
	259	return n;
	260	}
ec716e33 SR	261
	262	static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
	263	char *const argv[])
	264	{
	265	/* Reset SMSC LAN9303 switch for default configuration */
	266	gpio_request(GPIO_LAN9303_NRST, "nRST");
	267	gpio_direction_output(GPIO_LAN9303_NRST, 0);
	268	/* assert active low reset for 200us */
	269	udelay(200);
	270	gpio_set_value(GPIO_LAN9303_NRST, 1);
	271
	272	return 0;
	273	};
	274
	275	U_BOOT_CMD(
	276	switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
	277	"Reset LAN9303 switch via its reset pin",
	278	""
	279	);
c0dcece7 HS	280	#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
	281	#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
	282
	283	#include "../common/board.c"