[thirdparty/u-boot.git] / board / siemens / draco / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Board functions for TI AM335X based draco board
 * (C) Copyright 2013 Siemens Schweiz AG
 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * Based on:
 *
 * Board functions for TI AM335X based boards
 * u-boot:/board/ti/am335x/board.c
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
#include <nand.h>

#ifdef CONFIG_SPL_BUILD
static struct draco_baseboard_id __attribute__((section(".data"))) settings;

#if DDR_PLL_FREQ == 303
#if !defined(CONFIG_TARGET_ETAMIN)
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
	0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
	0x0000093B, 0x0000014A,
	"default name @303MHz           \0",
	"default marking                \0",
};
#else
/* etamin board */
const struct ddr3_data ddr3_default = {
	0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
	0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
	0x0000093B, 0x0000018A,
	"test-etamin                    \0",
	"generic-8Gbit                  \0",
};
#endif
#elif DDR_PLL_FREQ == 400
/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
	0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
	0x00000618, 0x0000014A,
	"default name @400MHz           \0",
	"default marking                \0",
};
#endif

static void set_default_ddr3_timings(void)
{
	printf("Set default DDR3 settings\n");
	settings.ddr3 = ddr3_default;
}

static void print_ddr3_timings(void)
{
	printf("\nDDR3\n");
	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
	printf("device:\t\t%s\n", settings.ddr3.manu_name);
	printf("marking:\t%s\n", settings.ddr3.manu_marking);
	printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
	       "default", "diff");
	PRINTARGS(magic);
	PRINTARGS(version);
	PRINTARGS(ddr3_sratio);
	PRINTARGS(iclkout);

	PRINTARGS(dt0rdsratio0);
	PRINTARGS(dt0wdsratio0);
	PRINTARGS(dt0fwsratio0);
	PRINTARGS(dt0wrsratio0);

	PRINTARGS(sdram_tim1);
	PRINTARGS(sdram_tim2);
	PRINTARGS(sdram_tim3);

	PRINTARGS(emif_ddr_phy_ctlr_1);

	PRINTARGS(sdram_config);
	PRINTARGS(ref_ctrl);
	PRINTARGS(ioctr_val);
}

static void print_chip_data(void)
{
	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
	printf("\nCPU BOARD\n");
	printf("device: \t'%s'\n", settings.chip.sdevname);
	printf("hw version: \t'%s'\n", settings.chip.shwver);
	printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
}
#endif /* CONFIG_SPL_BUILD */

#define AM335X_NAND_ECC_MASK 0x0f
#define AM335X_NAND_ECC_TYPE_16 0x02

static int ecc_type;

struct am335x_nand_geometry {
	u32 magic;
	u8 nand_geo_addr;
	u8 nand_geo_page;
	u8 nand_bus;
};

static int draco_read_nand_geometry(void)
{
	struct am335x_nand_geometry geo;

	/* Read NAND geometry */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
		     (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
		printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
		return -EIO;
	}
	if (geo.magic != 0xa657b310) {
		printf("%s: bad magic: %x\n", __func__, geo.magic);
		return -EFAULT;
	}
	if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
		ecc_type = 16;
	else
		ecc_type = 8;

	return 0;
}

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(void)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
		return 1;
	}

#ifdef CONFIG_SPL_BUILD
	/* Read Siemens eeprom data (DDR3) */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
		     (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
		printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
		set_default_ddr3_timings();
	}
	/* Read Siemens eeprom data (CHIP) */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
		     (uchar *)&settings.chip, sizeof(settings.chip)))
		printf("Could not read chip settings\n");

	if (ddr3_default.magic == settings.ddr3.magic &&
	    ddr3_default.version == settings.ddr3.version) {
		printf("Using DDR3 settings from EEPROM\n");
	} else {
		if (ddr3_default.magic != settings.ddr3.magic)
			printf("Warning: No valid DDR3 data in eeprom.\n");
		if (ddr3_default.version != settings.ddr3.version)
			printf("Warning: DDR3 data version does not match.\n");

		printf("Using default settings\n");
		set_default_ddr3_timings();
	}

	if (MAGIC_CHIP == settings.chip.magic)
		print_chip_data();
	else
		printf("Warning: No chip data in eeprom\n");

	print_ddr3_timings();

	return draco_read_nand_geometry();
#endif
	return 0;
}

#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs draco_ddr3_emif_reg_data = {
	.zq_config = 0x50074BE4,
};

struct ddr_data draco_ddr3_data = {
};

struct cmd_control draco_ddr3_cmd_ctrl_data = {
};

struct ctrl_ioregs draco_ddr3_ioregs = {
};

	/* pass values from eeprom */
	draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
	draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
	draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
		settings.ddr3.emif_ddr_phy_ctlr_1;
	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
	draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;

	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
	draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
	draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
	draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;

	draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
	draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
	draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
	draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;

	draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
	draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,

	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
		   &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
}

static void spl_siemens_board_init(void)
{
	return;
}
#endif /* if def CONFIG_SPL_BUILD */

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	int ret;

	ret = draco_read_nand_geometry();
	if (ret != 0)
		return ret;

	nand_curr_device = 0;
	omap_nand_switch_ecc(1, ecc_type);
#ifdef CONFIG_TARGET_ETAMIN
	nand_curr_device = 1;
	omap_nand_switch_ecc(1, ecc_type);
#endif
#ifdef CONFIG_FACTORYSET
	/* Set ASN in environment*/
	if (factory_dat.asn[0] != 0) {
		env_set("dtb_name", (char *)factory_dat.asn);
	} else {
		/* dtb suffix gets added in load script */
		env_set("dtb_name", "am335x-draco");
	}
#else
	env_set("dtb_name", "am335x-draco");
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_MII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 4,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
	int n = 0;
	int rv;

	factoryset_env_set();

	/* Set rgmii mode and enable rmii clock to be sourced from chip */
	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
	return n;
}

static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
			  char *const argv[])
{
	/* Reset SMSC LAN9303 switch for default configuration */
	gpio_request(GPIO_LAN9303_NRST, "nRST");
	gpio_direction_output(GPIO_LAN9303_NRST, 0);
	/* assert active low reset for 200us */
	udelay(200);
	gpio_set_value(GPIO_LAN9303_NRST, 1);

	return 0;
};

U_BOOT_CMD(
	switch_rst, CONFIG_SYS_MAXARGS, 1,	do_switch_reset,
	"Reset LAN9303 switch via its reset pin",
	""
);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */

#ifdef CONFIG_NAND_CS_INIT
/* GPMC definitions for second nand cs1 */
static const u32 gpmc_nand_config[] = {
	ETAMIN_NAND_GPMC_CONFIG1,
	ETAMIN_NAND_GPMC_CONFIG2,
	ETAMIN_NAND_GPMC_CONFIG3,
	ETAMIN_NAND_GPMC_CONFIG4,
	ETAMIN_NAND_GPMC_CONFIG5,
	ETAMIN_NAND_GPMC_CONFIG6,
	/*CONFIG7- computed as params */
};

static void board_nand_cs_init(void)
{
	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
			      0x18000000, GPMC_SIZE_16M);
}
#endif

#include "../common/board.c"
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c0dcece7	2	/*
820969f3	3	* Board functions for TI AM335X based draco board
c0dcece7 HS	4	* (C) Copyright 2013 Siemens Schweiz AG
	5	* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
	7	* Based on:
	8	*
	9	* Board functions for TI AM335X based boards
	10	* u-boot:/board/ti/am335x/board.c
	11	*
	12	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
c0dcece7 HS	13	*/
	14
	15	#include <common.h>
	16	#include <errno.h>
	17	#include <spl.h>
	18	#include <asm/arch/cpu.h>
	19	#include <asm/arch/hardware.h>
	20	#include <asm/arch/omap.h>
	21	#include <asm/arch/ddr_defs.h>
	22	#include <asm/arch/clock.h>
	23	#include <asm/arch/gpio.h>
	24	#include <asm/arch/mmc_host_def.h>
	25	#include <asm/arch/sys_proto.h>
6b3943f1	26	#include <asm/arch/mem.h>
c0dcece7 HS	27	#include <asm/io.h>
	28	#include <asm/emif.h>
	29	#include <asm/gpio.h>
	30	#include <i2c.h>
	31	#include <miiphy.h>
	32	#include <cpsw.h>
	33	#include <watchdog.h>
	34	#include "board.h"
	35	#include "../common/factoryset.h"
6b3943f1	36	#include <nand.h>
c0dcece7	37
c0dcece7	38	#ifdef CONFIG_SPL_BUILD
820969f3	39	static struct draco_baseboard_id __attribute__((section(".data"))) settings;
823b2c4c ES	40
823b2c4c ES	41	#if DDR_PLL_FREQ == 303
6b3943f1	42	#if !defined(CONFIG_TARGET_ETAMIN)
823b2c4c ES	43	/* Default@303MHz-i0 */
	44	const struct ddr3_data ddr3_default = {
	45	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
61159b76	46	0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
823b2c4c ES	47	0x0000093B, 0x0000014A,
	48	"default name @303MHz \0",
	49	"default marking \0",
	50	};
6b3943f1 HS	51	#else
	52	/* etamin board */
	53	const struct ddr3_data ddr3_default = {
	54	0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
	55	0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
	56	0x0000093B, 0x0000018A,
	57	"test-etamin \0",
	58	"generic-8Gbit \0",
	59	};
	60	#endif
823b2c4c ES	61	#elif DDR_PLL_FREQ == 400
823b2c4c ES	62	/* Default@400MHz-i0 */
c0dcece7	63	const struct ddr3_data ddr3_default = {
823b2c4c ES	64	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
823b2c4c ES	65	0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
56eb3da4	66	0x00000618, 0x0000014A,
823b2c4c ES	67	"default name @400MHz \0",
823b2c4c ES	68	"default marking \0",
c0dcece7	69	};
823b2c4c	70	#endif
c0dcece7 HS	71
	72	static void set_default_ddr3_timings(void)
	73	{
	74	printf("Set default DDR3 settings\n");
	75	settings.ddr3 = ddr3_default;
	76	}
	77
	78	static void print_ddr3_timings(void)
	79	{
823b2c4c ES	80	printf("\nDDR3\n");
	81	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
	82	printf("device:\t\t%s\n", settings.ddr3.manu_name);
	83	printf("marking:\t%s\n", settings.ddr3.manu_marking);
61159b76 HS	84	printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
61159b76 HS	85	"default", "diff");
c0dcece7 HS	86	PRINTARGS(magic);
	87	PRINTARGS(version);
	88	PRINTARGS(ddr3_sratio);
	89	PRINTARGS(iclkout);
	90
	91	PRINTARGS(dt0rdsratio0);
	92	PRINTARGS(dt0wdsratio0);
	93	PRINTARGS(dt0fwsratio0);
	94	PRINTARGS(dt0wrsratio0);
	95
	96	PRINTARGS(sdram_tim1);
	97	PRINTARGS(sdram_tim2);
	98	PRINTARGS(sdram_tim3);
	99
	100	PRINTARGS(emif_ddr_phy_ctlr_1);
	101
	102	PRINTARGS(sdram_config);
	103	PRINTARGS(ref_ctrl);
56eb3da4	104	PRINTARGS(ioctr_val);
c0dcece7 HS	105	}
	106
	107	static void print_chip_data(void)
	108	{
61159b76 HS	109	struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
61159b76 HS	110	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
823b2c4c ES	111	printf("\nCPU BOARD\n");
	112	printf("device: \t'%s'\n", settings.chip.sdevname);
	113	printf("hw version: \t'%s'\n", settings.chip.shwver);
61159b76	114	printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
c0dcece7 HS	115	}
	116	#endif /* CONFIG_SPL_BUILD */
	117
02b11f11 HS	118	#define AM335X_NAND_ECC_MASK 0x0f
	119	#define AM335X_NAND_ECC_TYPE_16 0x02
	120
	121	static int ecc_type;
	122
	123	struct am335x_nand_geometry {
	124	u32 magic;
	125	u8 nand_geo_addr;
	126	u8 nand_geo_page;
	127	u8 nand_bus;
	128	};
	129
	130	static int draco_read_nand_geometry(void)
	131	{
	132	struct am335x_nand_geometry geo;
	133
	134	/* Read NAND geometry */
	135	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
	136	(uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
	137	printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
	138	return -EIO;
	139	}
	140	if (geo.magic != 0xa657b310) {
	141	printf("%s: bad magic: %x\n", __func__, geo.magic);
	142	return -EFAULT;
	143	}
	144	if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
	145	ecc_type = 16;
	146	else
	147	ecc_type = 8;
	148
	149	return 0;
	150	}
	151
c0dcece7 HS	152	/*
	153	* Read header information from EEPROM into global structure.
	154	*/
	155	static int read_eeprom(void)
	156	{
	157	/* Check if baseboard eeprom is available */
	158	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	159	printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
	160	return 1;
	161	}
	162
	163	#ifdef CONFIG_SPL_BUILD
	164	/* Read Siemens eeprom data (DDR3) */
	165	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
	166	(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
	167	printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
	168	set_default_ddr3_timings();
	169	}
	170	/* Read Siemens eeprom data (CHIP) */
	171	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
	172	(uchar *)&settings.chip, sizeof(settings.chip)))
	173	printf("Could not read chip settings\n");
	174
	175	if (ddr3_default.magic == settings.ddr3.magic &&
	176	ddr3_default.version == settings.ddr3.version) {
	177	printf("Using DDR3 settings from EEPROM\n");
	178	} else {
	179	if (ddr3_default.magic != settings.ddr3.magic)
823b2c4c	180	printf("Warning: No valid DDR3 data in eeprom.\n");
c0dcece7	181	if (ddr3_default.version != settings.ddr3.version)
823b2c4c	182	printf("Warning: DDR3 data version does not match.\n");
c0dcece7 HS	183
	184	printf("Using default settings\n");
	185	set_default_ddr3_timings();
	186	}
	187
820969f3	188	if (MAGIC_CHIP == settings.chip.magic)
c0dcece7	189	print_chip_data();
820969f3	190	else
823b2c4c	191	printf("Warning: No chip data in eeprom\n");
c0dcece7 HS	192
c0dcece7 HS	193	print_ddr3_timings();
02b11f11 HS	194
02b11f11 HS	195	return draco_read_nand_geometry();
c0dcece7 HS	196	#endif
	197	return 0;
	198	}
	199
	200	#ifdef CONFIG_SPL_BUILD
	201	static void board_init_ddr(void)
	202	{
820969f3	203	struct emif_regs draco_ddr3_emif_reg_data = {
c0dcece7 HS	204	.zq_config = 0x50074BE4,
	205	};
	206
820969f3	207	struct ddr_data draco_ddr3_data = {
c0dcece7 HS	208	};
c0dcece7 HS	209
820969f3	210	struct cmd_control draco_ddr3_cmd_ctrl_data = {
c0dcece7	211	};
965de8b9	212
820969f3	213	struct ctrl_ioregs draco_ddr3_ioregs = {
965de8b9 LV	214	};
965de8b9 LV	215
c0dcece7	216	/* pass values from eeprom */
820969f3 ES	217	draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
	218	draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
	219	draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
	220	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
c0dcece7	221	settings.ddr3.emif_ddr_phy_ctlr_1;
820969f3	222	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
6b3943f1	223	draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
820969f3 ES	224	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
	225
	226	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
	227	draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
	228	draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
	229	draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
	230
	231	draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
	232	draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
	233	draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
	234	draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
	235	draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
	236	draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
	237
	238	draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
	239	draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
	240	draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
	241	draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
	242	draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
	243
	244	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
	245	&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
c0dcece7 HS	246	}
	247
	248	static void spl_siemens_board_init(void)
	249	{
	250	return;
	251	}
	252	#endif /* if def CONFIG_SPL_BUILD */
	253
61159b76 HS	254	#ifdef CONFIG_BOARD_LATE_INIT
	255	int board_late_init(void)
	256	{
02b11f11 HS	257	int ret;
	258
	259	ret = draco_read_nand_geometry();
	260	if (ret != 0)
	261	return ret;
	262
	263	nand_curr_device = 0;
	264	omap_nand_switch_ecc(1, ecc_type);
6b3943f1 HS	265	#ifdef CONFIG_TARGET_ETAMIN
	266	nand_curr_device = 1;
	267	omap_nand_switch_ecc(1, ecc_type);
	268	#endif
61159b76 HS	269	#ifdef CONFIG_FACTORYSET
	270	/* Set ASN in environment*/
	271	if (factory_dat.asn[0] != 0) {
382bee57	272	env_set("dtb_name", (char *)factory_dat.asn);
61159b76 HS	273	} else {
61159b76 HS	274	/* dtb suffix gets added in load script */
382bee57	275	env_set("dtb_name", "am335x-draco");
61159b76 HS	276	}
61159b76 HS	277	#else
382bee57	278	env_set("dtb_name", "am335x-draco");
61159b76 HS	279	#endif
	280
	281	return 0;
	282	}
	283	#endif
	284
c0dcece7 HS	285	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	286	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	287	static void cpsw_control(int enabled)
	288	{
	289	/* VTP can be added here */
	290
	291	return;
	292	}
	293
	294	static struct cpsw_slave_data cpsw_slaves[] = {
	295	{
	296	.slave_reg_ofs = 0x208,
	297	.sliver_reg_ofs = 0xd80,
9c653aad	298	.phy_addr = 0,
c0dcece7 HS	299	.phy_if = PHY_INTERFACE_MODE_MII,
	300	},
	301	};
	302
	303	static struct cpsw_platform_data cpsw_data = {
	304	.mdio_base = CPSW_MDIO_BASE,
	305	.cpsw_base = CPSW_BASE,
	306	.mdio_div = 0xff,
	307	.channels = 4,
	308	.cpdma_reg_ofs = 0x800,
	309	.slaves = 1,
	310	.slave_data = cpsw_slaves,
	311	.ale_reg_ofs = 0xd00,
	312	.ale_entries = 1024,
	313	.host_port_reg_ofs = 0x108,
	314	.hw_stats_reg_ofs = 0x900,
	315	.bd_ram_ofs = 0x2000,
	316	.mac_control = (1 << 5),
	317	.control = cpsw_control,
	318	.host_port_num = 0,
	319	.version = CPSW_CTRL_VERSION_2,
	320	};
	321
	322	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
95de1e2f	323	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
c0dcece7 HS	324	int board_eth_init(bd_t *bis)
	325	{
	326	struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	327	int n = 0;
	328	int rv;
	329
382bee57	330	factoryset_env_set();
c0dcece7 HS	331
	332	/* Set rgmii mode and enable rmii clock to be sourced from chip */
	333	writel((RMII_MODE_ENABLE \| RMII_CHIPCKL_ENABLE), &cdev->miisel);
	334
	335	rv = cpsw_register(&cpsw_data);
	336	if (rv < 0)
	337	printf("Error %d registering CPSW switch\n", rv);
	338	else
	339	n += rv;
	340	return n;
	341	}
ec716e33 SR	342
ec716e33 SR	343	static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
6b3943f1	344	char *const argv[])
ec716e33 SR	345	{
	346	/* Reset SMSC LAN9303 switch for default configuration */
	347	gpio_request(GPIO_LAN9303_NRST, "nRST");
	348	gpio_direction_output(GPIO_LAN9303_NRST, 0);
	349	/* assert active low reset for 200us */
	350	udelay(200);
	351	gpio_set_value(GPIO_LAN9303_NRST, 1);
	352
	353	return 0;
	354	};
	355
	356	U_BOOT_CMD(
	357	switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
	358	"Reset LAN9303 switch via its reset pin",
	359	""
	360	);
c0dcece7 HS	361	#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
	362	#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
	363
6b3943f1 HS	364	#ifdef CONFIG_NAND_CS_INIT
	365	/* GPMC definitions for second nand cs1 */
	366	static const u32 gpmc_nand_config[] = {
	367	ETAMIN_NAND_GPMC_CONFIG1,
	368	ETAMIN_NAND_GPMC_CONFIG2,
	369	ETAMIN_NAND_GPMC_CONFIG3,
	370	ETAMIN_NAND_GPMC_CONFIG4,
	371	ETAMIN_NAND_GPMC_CONFIG5,
	372	ETAMIN_NAND_GPMC_CONFIG6,
	373	/CONFIG7- computed as params /
	374	};
	375
	376	static void board_nand_cs_init(void)
	377	{
	378	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
	379	0x18000000, GPMC_SIZE_16M);
	380	}
	381	#endif
	382
c0dcece7	383	#include "../common/board.c"