[people/ms/u-boot.git] / board / siemens / smartweb / smartweb.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Achim Ehrlich <aehrlich@taskit.de>
 * taskit GmbH <www.taskit.de>
 *
 * (C) Copyright 2012-
 * Markus Hubig <mhubig@imko.de>
 * IMKO GmbH <www.imko.de>
 * (C) Copyright 2014
 * Heiko Schocher <hs@denx.de>
 * DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_serial.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <watchdog.h>
# include <net.h>
#ifndef CONFIG_DM_ETH
# include <netdev.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

static void smartweb_request_gpio(void)
{
	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
	gpio_request(AT91_PIN_PA26, "ena PHY");
}

static void smartweb_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Assign CS3 to NAND/SmartMedia Interface */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}

static void smartweb_macb_hw_init(void)
{
	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;

	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
	at91_set_gpio_output(AT91_PIN_PA26, 0);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PA14) |
		pin_to_mask(AT91_PIN_PA15) |
		pin_to_mask(AT91_PIN_PA17) |
		pin_to_mask(AT91_PIN_PA25) |
		pin_to_mask(AT91_PIN_PA26) |
		pin_to_mask(AT91_PIN_PA28) |
		pin_to_mask(AT91_PIN_PA29),
		&pioa->pudr);

	at91_phy_reset();

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PA14) |
		pin_to_mask(AT91_PIN_PA15) |
		pin_to_mask(AT91_PIN_PA17) |
		pin_to_mask(AT91_PIN_PA25) |
		pin_to_mask(AT91_PIN_PA26) |
		pin_to_mask(AT91_PIN_PA28) |
		pin_to_mask(AT91_PIN_PA29),
		&pioa->puer);

	/* Initialize EMAC=MACB hardware */
	at91_macb_hw_init();
}

#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>

void at91_udp_hw_init(void)
{
	/* Enable PLLB */
	at91_pllb_clk_enable(get_pllb_init());

	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	at91_periph_clk_enable(ATMEL_ID_UDP);

	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
}

struct at91_udc_data board_udc_data  = {
	.baseaddr = ATMEL_BASE_UDP0,
};
#endif

int board_early_init_f(void)
{
	/* enable this here, as we have SPL without serial support */
	at91_seriald_hw_init();
	smartweb_request_gpio();
	return 0;
}

int board_init(void)
{
	smartweb_request_gpio();
	/* power LED red */
	at91_set_gpio_output(AT91_PIN_PC6, 0);
	at91_set_gpio_output(AT91_PIN_PC7, 1);
	/* alarm LED off */
	at91_set_gpio_output(AT91_PIN_PC8, 0);
	at91_set_gpio_output(AT91_PIN_PC9, 0);
	/* prog LED red */
	at91_set_gpio_output(AT91_PIN_PC10, 0);
	at91_set_gpio_output(AT91_PIN_PC11, 1);

#ifdef CONFIG_USB_GADGET_AT91
	at91_udp_hw_init();
	at91_udc_probe(&board_udc_data);
#endif

	/* Adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	smartweb_nand_hw_init();
	smartweb_macb_hw_init();
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size(
		(void *)CONFIG_SYS_SDRAM_BASE,
		CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

#ifndef CONFIG_DM_ETH
#ifdef CONFIG_MACB
int board_eth_init(bd_t *bis)
{
	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
}
#endif /* CONFIG_MACB */
#endif

#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>

void matrix_init(void)
{
	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
			| AT91_MATRIX_SLOT_CYCLE_(0x40),
			&mat->scfg[3]);
}

void at91_spl_board_init(void)
{
	smartweb_request_gpio();
	/* power LED orange */
	at91_set_gpio_output(AT91_PIN_PC6, 1);
	at91_set_gpio_output(AT91_PIN_PC7, 1);
	/* alarm LED orange */
	at91_set_gpio_output(AT91_PIN_PC8, 1);
	at91_set_gpio_output(AT91_PIN_PC9, 1);
	/* prog LED red */
	at91_set_gpio_output(AT91_PIN_PC10, 0);
	at91_set_gpio_output(AT91_PIN_PC11, 1);

	smartweb_nand_hw_init();
	at91_set_gpio_input(AT91_PIN_PA28, 1);
	at91_set_gpio_input(AT91_PIN_PA29, 1);

	/* check if both  button are pressed */
	if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
		at91_get_gpio_value(AT91_PIN_PA29) == 0) {
		smartweb_nand_hw_init();
		nand_init();
		spl_nand_erase_one(0, 0);
	}
}

#define SDRAM_BASE_CONF	(AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
			 | AT91_SDRAMC_CAS_2 \
			 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
			 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
			 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
			 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))

void mem_init(void)
{
	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
	struct sdramc_reg setting;

	setting.cr = SDRAM_BASE_CONF;
	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;

	/*
	 * I write here directly in this register, because this
	 * approach is smaller than calling at91_set_a_periph() in a
	 * for loop. This saved me 96 bytes.
	 */
	writel(0xffff0000, &port->pdr);

	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
	sdramc_initialize(ATMEL_BASE_CS1, &setting);
}
#endif

static struct atmel_serial_platdata at91sam9260_serial_plat = {
	.base_addr = ATMEL_BASE_DBGU,
};

U_BOOT_DEVICE(at91sam9260_serial) = {
	.name	= "serial_atmel",
	.platdata = &at91sam9260_serial_plat,
};
Commit	Line	Data
3b5df50e HS	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian@popies.net>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Achim Ehrlich <aehrlich@taskit.de>
	7	* taskit GmbH <www.taskit.de>
	8	*
	9	* (C) Copyright 2012-
	10	* Markus Hubig <mhubig@imko.de>
	11	* IMKO GmbH <www.imko.de>
	12	* (C) Copyright 2014
	13	* Heiko Schocher <hs@denx.de>
	14	* DENX Software Engineering GmbH
	15	*
	16	* SPDX-License-Identifier: GPL-2.0+
	17	*/
	18
	19	#include <common.h>
13ee7890	20	#include <dm.h>
3b5df50e HS	21	#include <asm/io.h>
	22	#include <asm/arch/at91sam9_sdramc.h>
	23	#include <asm/arch/at91sam9260_matrix.h>
	24	#include <asm/arch/at91sam9_smc.h>
	25	#include <asm/arch/at91_common.h>
13ee7890	26	#include <asm/arch/atmel_serial.h>
3b5df50e HS	27	#include <asm/arch/at91_spi.h>
3b5df50e HS	28	#include <spi.h>
e8b81eef	29	#include <asm/arch/clk.h>
3b5df50e	30	#include <asm/arch/gpio.h>
13ee7890	31	#include <asm/gpio.h>
3b5df50e	32	#include <watchdog.h>
3b5df50e	33	# include <net.h>
13ee7890	34	#ifndef CONFIG_DM_ETH
3b5df50e HS	35	# include <netdev.h>
	36	#endif
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
13ee7890 HS	40	static void smartweb_request_gpio(void)
	41	{
	42	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
	43	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
	44	gpio_request(AT91_PIN_PA26, "ena PHY");
	45	}
	46
3b5df50e HS	47	static void smartweb_nand_hw_init(void)
	48	{
	49	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	50	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	51	unsigned long csa;
	52
	53	/* Assign CS3 to NAND/SmartMedia Interface */
	54	csa = readl(&matrix->ebicsa);
	55	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	56	writel(csa, &matrix->ebicsa);
	57
	58	/* Configure SMC CS3 for NAND/SmartMedia */
	59	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	60	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	61	&smc->cs[3].setup);
	62	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	63	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	64	&smc->cs[3].pulse);
	65	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	66	&smc->cs[3].cycle);
	67	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	68	AT91_SMC_MODE_TDF_CYCLE(2),
	69	&smc->cs[3].mode);
	70
	71	/* Configure RDY/BSY */
	72	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
	73
	74	/* Enable NandFlash */
	75	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
	76	}
	77
3b5df50e HS	78	static void smartweb_macb_hw_init(void)
	79	{
	80	struct at91_port pioa = (struct at91_port )ATMEL_BASE_PIOA;
	81
	82	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
	83	at91_set_gpio_output(AT91_PIN_PA26, 0);
	84
	85	/*
	86	* Disable pull-up on:
	87	* RXDV (PA17) => PHY normal mode (not Test mode)
	88	* ERX0 (PA14) => PHY ADDR0
	89	* ERX1 (PA15) => PHY ADDR1
	90	* ERX2 (PA25) => PHY ADDR2
	91	* ERX3 (PA26) => PHY ADDR3
	92	* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
	93	*
	94	* PHY has internal pull-down
	95	*/
	96	writel(pin_to_mask(AT91_PIN_PA14) \|
	97	pin_to_mask(AT91_PIN_PA15) \|
	98	pin_to_mask(AT91_PIN_PA17) \|
	99	pin_to_mask(AT91_PIN_PA25) \|
	100	pin_to_mask(AT91_PIN_PA26) \|
aca5d083 HS	101	pin_to_mask(AT91_PIN_PA28) \|
aca5d083 HS	102	pin_to_mask(AT91_PIN_PA29),
3b5df50e HS	103	&pioa->pudr);
	104
	105	at91_phy_reset();
	106
	107	/* Re-enable pull-up */
	108	writel(pin_to_mask(AT91_PIN_PA14) \|
	109	pin_to_mask(AT91_PIN_PA15) \|
	110	pin_to_mask(AT91_PIN_PA17) \|
	111	pin_to_mask(AT91_PIN_PA25) \|
	112	pin_to_mask(AT91_PIN_PA26) \|
aca5d083 HS	113	pin_to_mask(AT91_PIN_PA28) \|
aca5d083 HS	114	pin_to_mask(AT91_PIN_PA29),
3b5df50e HS	115	&pioa->puer);
	116
	117	/* Initialize EMAC=MACB hardware */
	118	at91_macb_hw_init();
	119	}
3b5df50e	120
e8b81eef HS	121	#ifdef CONFIG_USB_GADGET_AT91
	122	#include <linux/usb/at91_udc.h>
	123
	124	void at91_udp_hw_init(void)
	125	{
e8b81eef	126	/* Enable PLLB */
30f65c85	127	at91_pllb_clk_enable(get_pllb_init());
e8b81eef HS	128
	129	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
	130	at91_periph_clk_enable(ATMEL_ID_UDP);
	131
70341e2e	132	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
e8b81eef HS	133	}
	134
	135	struct at91_udc_data board_udc_data = {
	136	.baseaddr = ATMEL_BASE_UDP0,
	137	};
	138	#endif
	139
3b5df50e HS	140	int board_early_init_f(void)
	141	{
	142	/* enable this here, as we have SPL without serial support */
	143	at91_seriald_hw_init();
13ee7890	144	smartweb_request_gpio();
3b5df50e HS	145	return 0;
	146	}
	147
	148	int board_init(void)
	149	{
13ee7890	150	smartweb_request_gpio();
3b5df50e HS	151	/* power LED red */
	152	at91_set_gpio_output(AT91_PIN_PC6, 0);
	153	at91_set_gpio_output(AT91_PIN_PC7, 1);
	154	/* alarm LED off */
	155	at91_set_gpio_output(AT91_PIN_PC8, 0);
	156	at91_set_gpio_output(AT91_PIN_PC9, 0);
	157	/* prog LED red */
	158	at91_set_gpio_output(AT91_PIN_PC10, 0);
	159	at91_set_gpio_output(AT91_PIN_PC11, 1);
	160
e8b81eef HS	161	#ifdef CONFIG_USB_GADGET_AT91
	162	at91_udp_hw_init();
	163	at91_udc_probe(&board_udc_data);
	164	#endif
	165
aca5d083 HS	166	/* Adress of boot parameters */
	167	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	168
	169	smartweb_nand_hw_init();
aca5d083	170	smartweb_macb_hw_init();
3b5df50e HS	171	return 0;
	172	}
	173
	174	int dram_init(void)
	175	{
	176	gd->ram_size = get_ram_size(
	177	(void *)CONFIG_SYS_SDRAM_BASE,
	178	CONFIG_SYS_SDRAM_SIZE);
	179	return 0;
	180	}
	181
13ee7890	182	#ifndef CONFIG_DM_ETH
3b5df50e HS	183	#ifdef CONFIG_MACB
	184	int board_eth_init(bd_t *bis)
	185	{
	186	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
	187	}
	188	#endif /* CONFIG_MACB */
13ee7890	189	#endif
3b5df50e HS	190
	191	#if defined(CONFIG_SPL_BUILD)
	192	#include <spl.h>
	193	#include <nand.h>
	194	#include <spi_flash.h>
	195
	196	void matrix_init(void)
	197	{
	198	struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	199
	200	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
	201	\| AT91_MATRIX_SLOT_CYCLE_(0x40),
	202	&mat->scfg[3]);
	203	}
	204
13ee7890	205	void at91_spl_board_init(void)
3b5df50e	206	{
13ee7890	207	smartweb_request_gpio();
aca5d083	208	/* power LED orange */
3b5df50e HS	209	at91_set_gpio_output(AT91_PIN_PC6, 1);
	210	at91_set_gpio_output(AT91_PIN_PC7, 1);
	211	/* alarm LED orange */
	212	at91_set_gpio_output(AT91_PIN_PC8, 1);
	213	at91_set_gpio_output(AT91_PIN_PC9, 1);
	214	/* prog LED red */
	215	at91_set_gpio_output(AT91_PIN_PC10, 0);
	216	at91_set_gpio_output(AT91_PIN_PC11, 1);
	217
	218	smartweb_nand_hw_init();
	219	at91_set_gpio_input(AT91_PIN_PA28, 1);
	220	at91_set_gpio_input(AT91_PIN_PA29, 1);
	221
	222	/* check if both button are pressed */
	223	if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
aca5d083 HS	224	at91_get_gpio_value(AT91_PIN_PA29) == 0) {
aca5d083 HS	225	smartweb_nand_hw_init();
3b5df50e HS	226	nand_init();
	227	spl_nand_erase_one(0, 0);
	228	}
	229	}
	230
	231	#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 \| AT91_SDRAMC_NR_13 \
	232	\| AT91_SDRAMC_CAS_2 \
	233	\| AT91_SDRAMC_NB_4 \| AT91_SDRAMC_DBW_32 \
	234	\| AT91_SDRAMC_TWR_VAL(2) \| AT91_SDRAMC_TRC_VAL(7) \
	235	\| AT91_SDRAMC_TRP_VAL(2) \| AT91_SDRAMC_TRCD_VAL(2) \
	236	\| AT91_SDRAMC_TRAS_VAL(5) \| AT91_SDRAMC_TXSR_VAL(8))
	237
	238	void mem_init(void)
	239	{
	240	struct at91_matrix ma = (struct at91_matrix )ATMEL_BASE_MATRIX;
	241	struct at91_port port = (struct at91_port )ATMEL_BASE_PIOC;
	242	struct sdramc_reg setting;
	243
	244	setting.cr = SDRAM_BASE_CONF;
	245	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	246	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
	247
	248	/*
	249	* I write here directly in this register, because this
	250	* approach is smaller than calling at91_set_a_periph() in a
	251	* for loop. This saved me 96 bytes.
	252	*/
	253	writel(0xffff0000, &port->pdr);
	254
	255	writel(readl(&ma->ebicsa) \| AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
	256	sdramc_initialize(ATMEL_BASE_CS1, &setting);
	257	}
	258	#endif
13ee7890 HS	259
	260	static struct atmel_serial_platdata at91sam9260_serial_plat = {
	261	.base_addr = ATMEL_BASE_DBGU,
	262	};
	263
	264	U_BOOT_DEVICE(at91sam9260_serial) = {
	265	.name = "serial_atmel",
	266	.platdata = &at91sam9260_serial_plat,
	267	};