[people/ms/u-boot.git] / board / siemens / taurus / taurus.c

/*
 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
 * (C) Copyright Siemens AG
 *
 * Based on:
 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
 *
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/clk.h>
#include <linux/mtd/nand.h>
#include <atmel_mci.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>

#include <net.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

static void taurus_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Assign CS3 to NAND/SmartMedia Interface */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}

#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>

void matrix_init(void)
{
	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
			| AT91_MATRIX_SLOT_CYCLE_(0x40),
			&mat->scfg[3]);
}

void at91_spl_board_init(void)
{
	taurus_nand_hw_init();
	at91_spi0_hw_init(TAURUS_SPI_MASK);

	/* Configure recovery button PINs */
	at91_set_gpio_input(AT91_PIN_PA31, 1);

	/* check if button is pressed */
	if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
		struct spi_flash *flash;

		debug("Recovery button pressed\n");
		nand_init();
		spl_nand_erase_one(0, 0);
		flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
					0,
					CONFIG_SF_DEFAULT_SPEED,
					SPI_MODE_3);
		if (!flash) {
			puts("no flash\n");
		} else {
			puts("erase spi flash sector 0\n");
			spi_flash_erase(flash, 0,
					CONFIG_SYS_NAND_U_BOOT_SIZE);
		}
	}
}

void mem_init(void)
{
	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct sdramc_reg setting;

	at91_sdram_hw_init();
	setting.cr = (AT91_SDRAMC_NC_9 |
		      AT91_SDRAMC_NR_13 |
		      AT91_SDRAMC_CAS_3 |
		      AT91_SDRAMC_NB_4 |
		      AT91_SDRAMC_DBW_32 |
		      AT91_SDRAMC_TWR_VAL(3) |
		      AT91_SDRAMC_TRC_VAL(9) |
		      AT91_SDRAMC_TRP_VAL(3) |
		      AT91_SDRAMC_TRCD_VAL(3) |
		      AT91_SDRAMC_TRAS_VAL(6) |
		      AT91_SDRAMC_TXSR_VAL(10));
	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;


	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
		AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
		&ma->ebicsa);
	sdramc_initialize(ATMEL_BASE_CS1, &setting);
}
#endif

#ifdef CONFIG_MACB
static void taurus_macb_hw_init(void)
{
	/* Enable EMAC clock */
	at91_periph_clk_enable(ATMEL_ID_EMAC0);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);

	at91_phy_reset();

	at91_set_gpio_input(AT91_PIN_PA25, 1);   /* ERST tri-state */

	/* Re-enable pull-up */
	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);

	/* Initialize EMAC=MACB hardware */
	at91_macb_hw_init();
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bd)
{
	at91_mci_hw_init();

	return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
#endif

int board_early_init_f(void)
{
	/* Enable clocks for all PIOs */
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);

	at91_seriald_hw_init();

	return 0;
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	taurus_nand_hw_init();
#endif
#ifdef CONFIG_MACB
	taurus_macb_hw_init();
#endif
	at91_spi0_hw_init(TAURUS_SPI_MASK);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
#endif
	return rc;
}
Commit	Line	Data
0f8bc283 HS	1	/*
	2	* Board functions for Siemens TAURUS (AT91SAM9G20) based boards
	3	* (C) Copyright Siemens AG
	4	*
	5	* Based on:
	6	* U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
	7	*
	8	* (C) Copyright 2007-2008
	9	* Stelian Pop <stelian@popies.net>
	10	* Lead Tech Design <www.leadtechdesign.com>
	11	*
	12	* SPDX-License-Identifier: GPL-2.0+
	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/at91sam9260_matrix.h>
	18	#include <asm/arch/at91sam9_smc.h>
	19	#include <asm/arch/at91_common.h>
	20	#include <asm/arch/at91_pmc.h>
	21	#include <asm/arch/at91_rstc.h>
	22	#include <asm/arch/gpio.h>
	23	#include <asm/arch/at91sam9_sdramc.h>
237e3793 HS	24	#include <asm/arch/clk.h>
237e3793 HS	25	#include <linux/mtd/nand.h>
0f8bc283	26	#include <atmel_mci.h>
50921cdc HS	27	#include <asm/arch/at91_spi.h>
50921cdc HS	28	#include <spi.h>
0f8bc283 HS	29
	30	#include <net.h>
	31	#include <netdev.h>
	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
0f8bc283 HS	35	static void taurus_nand_hw_init(void)
	36	{
	37	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	38	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	39	unsigned long csa;
	40
	41	/* Assign CS3 to NAND/SmartMedia Interface */
	42	csa = readl(&matrix->ebicsa);
	43	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	44	writel(csa, &matrix->ebicsa);
	45
	46	/* Configure SMC CS3 for NAND/SmartMedia */
	47	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	48	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	49	&smc->cs[3].setup);
	50	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(3) \|
	51	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(3),
	52	&smc->cs[3].pulse);
	53	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(7),
	54	&smc->cs[3].cycle);
	55	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	56	AT91_SMC_MODE_EXNW_DISABLE \|
	57	AT91_SMC_MODE_DBW_8 \|
	58	AT91_SMC_MODE_TDF_CYCLE(3),
	59	&smc->cs[3].mode);
	60
	61	/* Configure RDY/BSY */
	62	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
	63
	64	/* Enable NandFlash */
	65	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
	66	}
237e3793 HS	67
	68	#if defined(CONFIG_SPL_BUILD)
	69	#include <spl.h>
	70	#include <nand.h>
a1655bb2	71	#include <spi_flash.h>
237e3793 HS	72
	73	void matrix_init(void)
	74	{
	75	struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	76
	77	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
	78	\| AT91_MATRIX_SLOT_CYCLE_(0x40),
	79	&mat->scfg[3]);
	80	}
	81
	82	void at91_spl_board_init(void)
	83	{
	84	taurus_nand_hw_init();
a1655bb2	85	at91_spi0_hw_init(TAURUS_SPI_MASK);
237e3793 HS	86
	87	/* Configure recovery button PINs */
	88	at91_set_gpio_input(AT91_PIN_PA31, 1);
	89
	90	/* check if button is pressed */
	91	if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
a1655bb2	92	struct spi_flash *flash;
237e3793 HS	93
237e3793 HS	94	debug("Recovery button pressed\n");
a1655bb2 HS	95	nand_init();
	96	spl_nand_erase_one(0, 0);
	97	flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
	98	0,
	99	CONFIG_SF_DEFAULT_SPEED,
	100	SPI_MODE_3);
	101	if (!flash) {
	102	puts("no flash\n");
	103	} else {
	104	puts("erase spi flash sector 0\n");
	105	spi_flash_erase(flash, 0,
	106	CONFIG_SYS_NAND_U_BOOT_SIZE);
237e3793 HS	107	}
	108	}
	109	}
	110
	111	void mem_init(void)
	112	{
	113	struct at91_matrix ma = (struct at91_matrix )ATMEL_BASE_MATRIX;
	114	struct sdramc_reg setting;
	115
	116	at91_sdram_hw_init();
	117	setting.cr = (AT91_SDRAMC_NC_9 \|
	118	AT91_SDRAMC_NR_13 \|
	119	AT91_SDRAMC_CAS_3 \|
	120	AT91_SDRAMC_NB_4 \|
	121	AT91_SDRAMC_DBW_32 \|
	122	AT91_SDRAMC_TWR_VAL(3) \|
	123	AT91_SDRAMC_TRC_VAL(9) \|
	124	AT91_SDRAMC_TRP_VAL(3) \|
	125	AT91_SDRAMC_TRCD_VAL(3) \|
	126	AT91_SDRAMC_TRAS_VAL(6) \|
	127	AT91_SDRAMC_TXSR_VAL(10));
	128	setting.mdr = AT91_SDRAMC_MD_SDRAM;
	129	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
	130
	131
	132	writel(readl(&ma->ebicsa) \| AT91_MATRIX_CS1A_SDRAMC \|
	133	AT91_MATRIX_VDDIOMSEL_3_3V \| AT91_MATRIX_EBI_IOSR_SEL,
	134	&ma->ebicsa);
	135	sdramc_initialize(ATMEL_BASE_CS1, &setting);
	136	}
0f8bc283 HS	137	#endif
	138
	139	#ifdef CONFIG_MACB
	140	static void taurus_macb_hw_init(void)
	141	{
0f8bc283	142	/* Enable EMAC clock */
237e3793	143	at91_periph_clk_enable(ATMEL_ID_EMAC0);
0f8bc283 HS	144
	145	/*
	146	* Disable pull-up on:
	147	* RXDV (PA17) => PHY normal mode (not Test mode)
	148	* ERX0 (PA14) => PHY ADDR0
	149	* ERX1 (PA15) => PHY ADDR1
	150	* ERX2 (PA25) => PHY ADDR2
	151	* ERX3 (PA26) => PHY ADDR3
	152	* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
	153	*
	154	* PHY has internal pull-down
	155	*/
	156	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
	157	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
	158	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
	159	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
	160	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
	161	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
	162
	163	at91_phy_reset();
	164
	165	at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
	166
	167	/* Re-enable pull-up */
	168	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
	169	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
	170	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
	171	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
	172	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
	173	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
	174
	175	/* Initialize EMAC=MACB hardware */
	176	at91_macb_hw_init();
	177	}
	178	#endif
	179
	180	#ifdef CONFIG_GENERIC_ATMEL_MCI
	181	int board_mmc_init(bd_t *bd)
	182	{
	183	at91_mci_hw_init();
	184
	185	return atmel_mci_init((void *)ATMEL_BASE_MCI);
	186	}
	187	#endif
	188
	189	int board_early_init_f(void)
	190	{
0f8bc283	191	/* Enable clocks for all PIOs */
237e3793 HS	192	at91_periph_clk_enable(ATMEL_ID_PIOA);
	193	at91_periph_clk_enable(ATMEL_ID_PIOB);
	194	at91_periph_clk_enable(ATMEL_ID_PIOC);
	195
	196	at91_seriald_hw_init();
0f8bc283 HS	197
	198	return 0;
	199	}
	200
50921cdc HS	201	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	202	{
	203	return bus == 0 && cs == 0;
	204	}
	205
	206	void spi_cs_activate(struct spi_slave *slave)
	207	{
	208	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
	209	}
	210
	211	void spi_cs_deactivate(struct spi_slave *slave)
	212	{
	213	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
	214	}
	215
0f8bc283 HS	216	int board_init(void)
	217	{
	218	/* adress of boot parameters */
	219	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	220
0f8bc283 HS	221	#ifdef CONFIG_CMD_NAND
	222	taurus_nand_hw_init();
	223	#endif
	224	#ifdef CONFIG_MACB
	225	taurus_macb_hw_init();
	226	#endif
50921cdc	227	at91_spi0_hw_init(TAURUS_SPI_MASK);
0f8bc283 HS	228
	229	return 0;
	230	}
	231
	232	int dram_init(void)
	233	{
	234	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	235	CONFIG_SYS_SDRAM_SIZE);
	236	return 0;
	237	}
	238
	239	int board_eth_init(bd_t *bis)
	240	{
	241	int rc = 0;
	242	#ifdef CONFIG_MACB
	243	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
	244	#endif
	245	return rc;
	246	}