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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Dave Ellis, SIXNET, dge@sixnetio.com. | |
4 | * Based on code by: | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * and other contributors to U-Boot. See file CREDITS for list | |
7 | * of people who contributed to this project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <config.h> | |
27 | #include <mpc8xx.h> | |
28 | #include <net.h> /* for eth_init() */ | |
29 | #include <rtc.h> | |
30 | #include "sixnet.h" | |
506f0441 WD |
31 | #ifdef CONFIG_SHOW_BOOT_PROGRESS |
32 | # include <status_led.h> | |
33 | #endif | |
5b1d7137 WD |
34 | |
35 | #define ORMASK(size) ((-size) & OR_AM_MSK) | |
36 | ||
37 | static long ram_size(ulong *, long); | |
38 | ||
39 | /* ------------------------------------------------------------------------- */ | |
40 | ||
506f0441 WD |
41 | #ifdef CONFIG_SHOW_BOOT_PROGRESS |
42 | void show_boot_progress (int status) | |
43 | { | |
44 | #if defined(CONFIG_STATUS_LED) | |
45 | # if defined(STATUS_LED_BOOT) | |
46 | if (status == 15) { | |
47 | /* ready to transfer to kernel, make sure LED is proper state */ | |
48 | status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); | |
49 | } | |
50 | # endif /* STATUS_LED_BOOT */ | |
51 | #endif /* CONFIG_STATUS_LED */ | |
52 | } | |
53 | #endif | |
54 | ||
55 | /* ------------------------------------------------------------------------- */ | |
56 | ||
5b1d7137 WD |
57 | /* |
58 | * Check Board Identity: | |
59 | * returns 0 if recognized, -1 if unknown | |
60 | */ | |
61 | ||
62 | int checkboard (void) | |
63 | { | |
64 | puts ("Board: SIXNET SXNI855T\n"); | |
65 | return 0; | |
66 | } | |
67 | ||
68 | /* ------------------------------------------------------------------------- */ | |
69 | ||
70 | #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) | |
71 | #error "SXNI855T has no PCMCIA port" | |
72 | #endif /* CFG_CMD_PCMCIA */ | |
73 | ||
74 | /* ------------------------------------------------------------------------- */ | |
75 | ||
76 | #define _not_used_ 0xffffffff | |
77 | ||
78 | /* UPMB table for dual UART. */ | |
79 | ||
80 | /* this table is for 50MHz operation, it should work at all lower speeds */ | |
81 | const uint duart_table[] = | |
82 | { | |
83 | /* single read. (offset 0 in upm RAM) */ | |
84 | 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, | |
85 | 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, | |
86 | ||
87 | /* burst read. (offset 8 in upm RAM) */ | |
88 | _not_used_, _not_used_, _not_used_, _not_used_, | |
89 | _not_used_, _not_used_, _not_used_, _not_used_, | |
90 | _not_used_, _not_used_, _not_used_, _not_used_, | |
91 | _not_used_, _not_used_, _not_used_, _not_used_, | |
92 | ||
93 | /* single write. (offset 18 in upm RAM) */ | |
94 | 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, | |
95 | 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, | |
96 | ||
97 | /* burst write. (offset 20 in upm RAM) */ | |
98 | _not_used_, _not_used_, _not_used_, _not_used_, | |
99 | _not_used_, _not_used_, _not_used_, _not_used_, | |
100 | _not_used_, _not_used_, _not_used_, _not_used_, | |
101 | _not_used_, _not_used_, _not_used_, _not_used_, | |
102 | ||
103 | /* refresh. (offset 30 in upm RAM) */ | |
104 | _not_used_, _not_used_, _not_used_, _not_used_, | |
105 | _not_used_, _not_used_, _not_used_, _not_used_, | |
106 | _not_used_, _not_used_, _not_used_, _not_used_, | |
107 | ||
108 | /* exception. (offset 3c in upm RAM) */ | |
109 | _not_used_, _not_used_, _not_used_, _not_used_, | |
110 | }; | |
111 | ||
112 | /* Load FPGA very early in boot sequence, since it must be | |
113 | * loaded before the 16C2550 serial channels can be used as | |
114 | * console channels. | |
115 | * | |
116 | * Note: Much of the configuration is not complete. The | |
117 | * stack is in DPRAM since SDRAM has not been initialized, | |
118 | * so the stack must be kept small. Global variables | |
119 | * are still in FLASH, so they cannot be written. | |
120 | * Only the FLASH, DPRAM, immap and FPGA can be addressed, | |
121 | * the other chip selects may not have been initialized. | |
122 | * The clocks have been initialized, so udelay() can be | |
123 | * used. | |
124 | */ | |
125 | #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ | |
126 | #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ | |
127 | #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ | |
128 | #define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */ | |
129 | ||
130 | int board_postclk_init (void) | |
131 | { | |
132 | ||
133 | /* the data to load to the XCSxxXL FPGA */ | |
134 | static const unsigned char fpgadata[] = { | |
135 | # include "fpgadata.c" | |
136 | }; | |
137 | ||
138 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
139 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
140 | #define porta (immap->im_ioport.iop_padat) | |
141 | const unsigned char* pdata; | |
142 | ||
143 | /* /INITFPGA and DONEFPGA signals are inputs */ | |
144 | immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); | |
145 | ||
146 | /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ | |
147 | porta &= ~FPGA_PROGRAM_L; | |
148 | ||
149 | /* Set FPGA as an output */ | |
150 | immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; | |
151 | ||
152 | /* delay a little to make sure FPGA sees it, really | |
153 | * only need less than a microsecond. | |
154 | */ | |
155 | udelay(10); | |
156 | ||
157 | /* unassert /PROGRAM */ | |
158 | porta |= FPGA_PROGRAM_L; | |
159 | ||
160 | /* delay while FPGA does last erase, indicated by | |
161 | * /INITFPGA going high. This should happen within a | |
162 | * few milliseconds. | |
163 | */ | |
164 | /* ### FIXME - a timeout check would be good, maybe flash | |
165 | * the status LED to indicate the error? | |
166 | */ | |
167 | while ((porta & FPGA_INIT_L) == 0) | |
168 | ; /* waiting */ | |
169 | ||
170 | /* write program data to FPGA at the programming address | |
171 | * so extra /CS1 strobes at end of configuration don't actually | |
172 | * write to any registers. | |
173 | */ | |
174 | fpga = 0xff; /* first write is ignored */ | |
175 | fpga = 0xff; /* fill byte */ | |
176 | fpga = 0xff; /* fill byte */ | |
177 | fpga = 0x4f; /* preamble code */ | |
178 | fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ | |
179 | fpga = 0x4b; /* field check code */ | |
180 | ||
181 | pdata = fpgadata; | |
182 | /* while no error write out each of the 28 byte frames */ | |
183 | while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L | |
184 | && pdata < fpgadata + sizeof(fpgadata)) { | |
185 | ||
186 | fpga = 0x4f; /* preamble code */ | |
187 | ||
188 | /* 21 bytes of data in a frame */ | |
189 | fpga = *(pdata++); fpga = *(pdata++); | |
190 | fpga = *(pdata++); fpga = *(pdata++); | |
191 | fpga = *(pdata++); fpga = *(pdata++); | |
192 | fpga = *(pdata++); fpga = *(pdata++); | |
193 | fpga = *(pdata++); fpga = *(pdata++); | |
194 | fpga = *(pdata++); fpga = *(pdata++); | |
195 | fpga = *(pdata++); fpga = *(pdata++); | |
196 | fpga = *(pdata++); fpga = *(pdata++); | |
197 | fpga = *(pdata++); fpga = *(pdata++); | |
198 | fpga = *(pdata++); fpga = *(pdata++); | |
199 | fpga = *(pdata++); | |
200 | ||
201 | fpga = 0x4b; /* field check code */ | |
202 | fpga = 0xff; /* extended write cycle */ | |
203 | fpga = 0x4b; /* extended write cycle | |
204 | * (actually 0x4b from bitgen.exe) | |
205 | */ | |
206 | fpga = 0xff; /* extended write cycle */ | |
207 | fpga = 0xff; /* extended write cycle */ | |
208 | fpga = 0xff; /* extended write cycle */ | |
209 | } | |
210 | ||
211 | fpga = 0xff; /* startup byte */ | |
212 | fpga = 0xff; /* startup byte */ | |
213 | fpga = 0xff; /* startup byte */ | |
214 | fpga = 0xff; /* startup byte */ | |
215 | ||
216 | #if 0 /* ### FIXME */ | |
217 | /* If didn't load all the data or FPGA_DONE is low the load failed. | |
218 | * Maybe someday stop here and flash the status LED? The console | |
219 | * is not configured, so can't print an error message. Can't write | |
220 | * global variables to set a flag (except gd?). | |
221 | * For now it must work. | |
222 | */ | |
223 | #endif | |
224 | ||
225 | /* Now that the FPGA is loaded, set up the Dual UART chip | |
226 | * selects. Must be done here since it may be used as the console. | |
227 | */ | |
228 | upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); | |
229 | ||
230 | memctl->memc_mbmr = DUART_MBMR; | |
231 | memctl->memc_or5 = DUART_OR_VALUE; | |
232 | memctl->memc_br5 = DUART_BR5_VALUE; | |
233 | memctl->memc_or6 = DUART_OR_VALUE; | |
234 | memctl->memc_br6 = DUART_BR6_VALUE; | |
235 | ||
236 | return (0); | |
237 | } | |
238 | ||
239 | /* ------------------------------------------------------------------------- */ | |
240 | ||
241 | /* base address for SRAM, assume 32-bit port, valid */ | |
242 | #define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V) | |
243 | ||
244 | /* up to 64MB - will be adjusted for actual size */ | |
245 | #define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \ | |
246 | | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) | |
247 | /* | |
248 | * Miscellaneous platform dependent initializations after running in RAM. | |
249 | */ | |
250 | ||
251 | int misc_init_r (void) | |
252 | { | |
253 | DECLARE_GLOBAL_DATA_PTR; | |
254 | ||
255 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
256 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
506f0441 WD |
257 | char* s; |
258 | char* e; | |
259 | int reg; | |
5b1d7137 WD |
260 | bd_t *bd = gd->bd; |
261 | ||
262 | memctl->memc_or2 = NVRAM_OR_PRELIM; | |
263 | memctl->memc_br2 = NVRAM_BR_VALUE; | |
264 | ||
265 | /* Is there any SRAM? Is it 16 or 32 bits wide? */ | |
266 | ||
267 | /* First look for 32-bit SRAM */ | |
268 | bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); | |
269 | ||
270 | if (bd->bi_sramsize == 0) { | |
271 | /* no 32-bit SRAM, but there could be 16-bit SRAM since | |
272 | * it would report size 0 when configured for 32-bit bus. | |
273 | * Try again with a 16-bit bus. | |
274 | */ | |
275 | memctl->memc_br2 |= BR_PS_16; | |
276 | bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); | |
277 | } | |
278 | ||
279 | if (bd->bi_sramsize == 0) { | |
280 | memctl->memc_br2 = 0; /* disable select since nothing there */ | |
281 | } | |
282 | else { | |
283 | /* adjust or2 for actual size of SRAM */ | |
284 | memctl->memc_or2 |= ORMASK(bd->bi_sramsize); | |
285 | bd->bi_sramstart = CFG_SRAM_BASE; | |
286 | printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); | |
287 | } | |
288 | ||
289 | ||
290 | /* set standard MPC8xx clock so kernel will see the time | |
291 | * even if it doesn't have a DS1306 clock driver. | |
292 | * This helps with experimenting with standard kernels. | |
293 | */ | |
294 | { | |
295 | ulong tim; | |
296 | struct rtc_time tmp; | |
297 | ||
298 | rtc_get(&tmp); /* get time from DS1306 RTC */ | |
299 | ||
300 | /* convert to seconds since 1970 */ | |
301 | tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, | |
302 | tmp.tm_hour, tmp.tm_min, tmp.tm_sec); | |
303 | ||
304 | immap->im_sitk.sitk_rtck = KAPWR_KEY; | |
305 | immap->im_sit.sit_rtc = tim; | |
306 | } | |
307 | ||
506f0441 WD |
308 | /* set up ethernet address for SCC ethernet. If eth1addr |
309 | * is present it gets a unique address, otherwise it | |
310 | * shares the FEC address. | |
5b1d7137 | 311 | */ |
506f0441 WD |
312 | s = getenv("eth1addr"); |
313 | if (s == NULL) | |
314 | s = getenv("ethaddr"); | |
315 | for (reg=0; reg<6; ++reg) { | |
316 | bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0; | |
317 | if (s) | |
318 | s = (*e) ? e+1 : e; | |
319 | } | |
5b1d7137 | 320 | |
5b1d7137 WD |
321 | return (0); |
322 | } | |
323 | ||
324 | /* ------------------------------------------------------------------------- */ | |
325 | ||
326 | /* | |
327 | * Check memory range for valid RAM. A simple memory test determines | |
328 | * the actually available RAM size between addresses `base' and | |
329 | * `base + maxsize'. | |
330 | * | |
331 | * The memory size MUST be a power of 2 for this to work. | |
332 | * | |
506f0441 | 333 | * The only memory modified is 8 bytes at offset 0. This is important |
5b1d7137 WD |
334 | * since for the SRAM this location is reserved for autosizing, so if |
335 | * it is modified and the board is reset before ram_size() completes | |
336 | * no damage is done. Normally even the memory at 0 is preserved. The | |
337 | * higher SRAM addresses may contain battery backed RAM disk data which | |
338 | * must never be corrupted. | |
339 | */ | |
340 | ||
341 | static long ram_size(ulong *base, long maxsize) | |
342 | { | |
343 | volatile long *test_addr; | |
344 | volatile long *base_addr = base; | |
5b1d7137 WD |
345 | ulong ofs; /* byte offset from base_addr */ |
346 | ulong save; /* to make test non-destructive */ | |
506f0441 | 347 | ulong save2; /* to make test non-destructive */ |
5b1d7137 WD |
348 | long ramsize = -1; /* size not determined yet */ |
349 | ||
350 | save = *base_addr; /* save value at 0 so can restore */ | |
506f0441 | 351 | save2 = *(base_addr+1); /* save value at 4 so can restore */ |
5b1d7137 WD |
352 | |
353 | /* is any SRAM present? */ | |
354 | *base_addr = 0x5555aaaa; | |
355 | ||
506f0441 WD |
356 | /* It is important to drive the data bus with different data so |
357 | * it doesn't remember the value and look like RAM that isn't there. | |
5b1d7137 | 358 | */ |
506f0441 | 359 | *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ |
5b1d7137 WD |
360 | |
361 | if (*base_addr != 0x5555aaaa) | |
362 | ramsize = 0; /* no RAM present, or defective */ | |
363 | else { | |
364 | *base_addr = 0xaaaa5555; | |
506f0441 | 365 | *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ |
5b1d7137 WD |
366 | if (*base_addr != 0xaaaa5555) |
367 | ramsize = 0; /* no RAM present, or defective */ | |
368 | } | |
369 | ||
370 | /* now size it if any is present */ | |
371 | for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { | |
372 | test_addr = (long*)((long)base_addr + ofs); /* location to test */ | |
373 | ||
374 | *base_addr = ~*test_addr; | |
375 | if (*base_addr == *test_addr) | |
376 | ramsize = ofs; /* wrapped back to 0, so this is the size */ | |
377 | } | |
378 | ||
379 | *base_addr = save; /* restore value at 0 */ | |
506f0441 | 380 | *(base_addr+1) = save2; /* restore value at 4 */ |
5b1d7137 WD |
381 | return (ramsize); |
382 | } | |
383 | ||
384 | /* ------------------------------------------------------------------------- */ | |
385 | /* sdram table based on the FADS manual */ | |
386 | /* for chip MB811171622A-100 */ | |
387 | ||
388 | /* this table is for 50MHz operation, it should work at all lower speeds */ | |
389 | ||
390 | const uint sdram_table[] = | |
391 | { | |
392 | /* single read. (offset 0 in upm RAM) */ | |
393 | 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, | |
394 | 0x1ff77c47, | |
395 | ||
396 | /* precharge and Mode Register Set initialization (offset 5). | |
397 | * This is also entered at offset 6 to do Mode Register Set | |
398 | * without the precharge. | |
399 | */ | |
400 | 0x1ff77c34, 0xefeabc34, 0x1fb57c35, | |
401 | ||
402 | /* burst read. (offset 8 in upm RAM) */ | |
403 | 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, | |
404 | 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, | |
405 | _not_used_, _not_used_, _not_used_, _not_used_, | |
406 | _not_used_, _not_used_, _not_used_, _not_used_, | |
407 | ||
408 | /* single write. (offset 18 in upm RAM) */ | |
409 | /* FADS had 0x1f27fc04, ... | |
410 | * but most other boards have 0x1f07fc04, which | |
411 | * sets GPL0 from A11MPC to 0 1/4 clock earlier, | |
412 | * like the single read. | |
413 | * This seems better so I am going with the change. | |
414 | */ | |
415 | 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, | |
416 | _not_used_, _not_used_, _not_used_, _not_used_, | |
417 | ||
418 | /* burst write. (offset 20 in upm RAM) */ | |
419 | 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, | |
420 | 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, | |
421 | _not_used_, _not_used_, _not_used_, _not_used_, | |
422 | _not_used_, _not_used_, _not_used_, _not_used_, | |
423 | ||
424 | /* refresh. (offset 30 in upm RAM) */ | |
425 | 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, | |
426 | 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, | |
427 | _not_used_, _not_used_, _not_used_, _not_used_, | |
428 | ||
429 | /* exception. (offset 3c in upm RAM) */ | |
430 | 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; | |
431 | ||
432 | /* ------------------------------------------------------------------------- */ | |
433 | ||
434 | #define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ | |
435 | ||
436 | /* precharge and set Mode Register */ | |
437 | #define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
438 | MCR_MB_CS3 | /* chip select */ \ | |
439 | MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ | |
440 | ||
441 | /* set Mode Register, no precharge */ | |
442 | #define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
443 | MCR_MB_CS3 | /* chip select */ \ | |
444 | MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ | |
445 | ||
446 | /* runs refresh loop twice so get 8 refresh cycles */ | |
447 | #define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
448 | MCR_MB_CS3 | /* chip select */ \ | |
449 | MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ | |
450 | ||
451 | /* MAMR values work in either mamr or mbmr */ | |
506f0441 | 452 | #define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ |
5b1d7137 | 453 | ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ |
5b1d7137 | 454 | | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ |
5b1d7137 WD |
455 | | MAMR_RLFA_1X /* Read loop 1 time */ \ |
456 | | MAMR_WLFA_1X /* Write loop 1 time */ \ | |
457 | | MAMR_TLFA_4X) /* Timer loop 4 times */ | |
506f0441 WD |
458 | /* 8 column SDRAM */ |
459 | #define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ | |
460 | | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ | |
461 | | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ | |
5b1d7137 WD |
462 | |
463 | /* 9 column SDRAM */ | |
506f0441 WD |
464 | #define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ |
465 | | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ | |
466 | | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ | |
5b1d7137 WD |
467 | |
468 | /* base address 0, 32-bit port, SDRAM UPM, valid */ | |
469 | #define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) | |
470 | ||
471 | /* up to 256MB, SAM, G5LS - will be adjusted for actual size */ | |
472 | #define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) | |
473 | ||
474 | /* This is the Mode Select Register value for the SDRAM. | |
475 | * Burst length: 4 | |
476 | * Burst Type: sequential | |
477 | * CAS Latency: 2 | |
478 | * Write Burst Length: burst | |
479 | */ | |
480 | #define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ | |
481 | ||
482 | /* ------------------------------------------------------------------------- */ | |
483 | ||
484 | long int initdram(int board_type) | |
485 | { | |
486 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
487 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
488 | uint size_sdram = 0; | |
489 | uint size_sdram9 = 0; | |
490 | uint base = 0; /* SDRAM must start at 0 */ | |
491 | int i; | |
492 | ||
493 | upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); | |
494 | ||
495 | /* Configure the refresh (mostly). This needs to be | |
496 | * based upon processor clock speed and optimized to provide | |
497 | * the highest level of performance. | |
498 | * | |
499 | * Preliminary prescaler for refresh. | |
500 | * This value is selected for four cycles in 31.2 us, | |
501 | * which gives 8192 cycles in 64 milliseconds. | |
502 | * This may be too fast, but works for any memory. | |
503 | * It is adjusted to 4096 cycles in 64 milliseconds if | |
504 | * possible once we know what memory we have. | |
505 | * | |
506 | * We have to be careful changing UPM registers after we | |
507 | * ask it to run these commands. | |
508 | * | |
509 | * PTA - periodic timer period for our design is | |
510 | * 50 MHz x 31.2us | |
511 | * --------------- = 195 | |
512 | * 1 x 8 x 1 | |
513 | * | |
514 | * 50MHz clock | |
515 | * 31.2us refresh interval | |
516 | * SCCR[DFBRG] 0 | |
517 | * PTP divide by 8 | |
518 | * 1 chip select | |
519 | */ | |
520 | memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ | |
521 | memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ | |
522 | ||
523 | /* The SDRAM Mode Register value is shifted left 2 bits since | |
524 | * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. | |
525 | */ | |
526 | memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ | |
527 | udelay(200); /* SDRAM needs 200uS before set it up */ | |
528 | ||
529 | /* Now run the precharge/nop/mrs commands. */ | |
530 | memctl->memc_mcr = SDRAM_MCR_PRE; | |
531 | udelay(2); | |
532 | ||
533 | /* Run 8 refresh cycles (2 sets of 4) */ | |
534 | memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ | |
535 | udelay(2); | |
536 | ||
537 | /* some brands want Mode Register set after the refresh | |
538 | * cycles. This shouldn't hurt anything for the brands | |
539 | * that were happy with the first time we set it. | |
540 | */ | |
541 | memctl->memc_mcr = SDRAM_MCR_MRS; | |
542 | udelay(2); | |
543 | ||
544 | memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ | |
545 | memctl->memc_or3 = SDRAM_OR_PRELIM; | |
546 | memctl->memc_br3 = SDRAM_BR_VALUE + base; | |
547 | ||
548 | /* Some brands need at least 10 DRAM accesses to stabilize. | |
549 | * It wont hurt the brands that don't. | |
550 | */ | |
551 | for (i=0; i<10; ++i) { | |
552 | volatile ulong *addr = (volatile ulong *)base; | |
553 | ulong val; | |
554 | ||
555 | val = *(addr + i); | |
556 | *(addr + i) = val; | |
557 | } | |
558 | ||
559 | /* Check SDRAM memory Size in 8 column mode. | |
560 | * For a 9 column memory we will get half the actual size. | |
561 | */ | |
562 | size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); | |
563 | ||
564 | /* Check SDRAM memory Size in 9 column mode. | |
565 | * For an 8 column memory we will see at most 4 megabytes. | |
566 | */ | |
567 | memctl->memc_mamr = SDRAM_MAMR_9COL; | |
568 | size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); | |
569 | ||
570 | if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ | |
571 | size_sdram = size_sdram9; | |
572 | else /* go back to 8 columns */ | |
573 | memctl->memc_mamr = SDRAM_MAMR_8COL; | |
574 | ||
575 | /* adjust or3 for actual size of SDRAM | |
576 | */ | |
577 | memctl->memc_or3 |= ORMASK(size_sdram); | |
578 | ||
579 | /* Adjust refresh rate depending on SDRAM type. | |
580 | * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave | |
581 | * it at the current (fast) rate. | |
582 | * For 16, 64 and 128 MBit half the rate will do. | |
583 | */ | |
584 | if (size_sdram <= 32 * 1024 * 1024) | |
585 | memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ | |
586 | ||
587 | return (size_sdram); | |
588 | } | |
589 |