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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Dave Ellis, SIXNET, dge@sixnetio.com. | |
4 | * Based on code by: | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * and other contributors to U-Boot. See file CREDITS for list | |
7 | * of people who contributed to this project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <config.h> | |
27 | #include <mpc8xx.h> | |
28 | #include <net.h> /* for eth_init() */ | |
29 | #include <rtc.h> | |
30 | #include "sixnet.h" | |
506f0441 WD |
31 | #ifdef CONFIG_SHOW_BOOT_PROGRESS |
32 | # include <status_led.h> | |
33 | #endif | |
5b1d7137 | 34 | |
7a8e9bed WD |
35 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
36 | #include <linux/mtd/nand.h> | |
37 | extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; | |
38 | #endif | |
39 | ||
5b1d7137 WD |
40 | #define ORMASK(size) ((-size) & OR_AM_MSK) |
41 | ||
42 | static long ram_size(ulong *, long); | |
43 | ||
44 | /* ------------------------------------------------------------------------- */ | |
45 | ||
506f0441 WD |
46 | #ifdef CONFIG_SHOW_BOOT_PROGRESS |
47 | void show_boot_progress (int status) | |
48 | { | |
49 | #if defined(CONFIG_STATUS_LED) | |
50 | # if defined(STATUS_LED_BOOT) | |
51 | if (status == 15) { | |
52 | /* ready to transfer to kernel, make sure LED is proper state */ | |
53 | status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); | |
54 | } | |
55 | # endif /* STATUS_LED_BOOT */ | |
56 | #endif /* CONFIG_STATUS_LED */ | |
57 | } | |
58 | #endif | |
59 | ||
60 | /* ------------------------------------------------------------------------- */ | |
61 | ||
5b1d7137 WD |
62 | /* |
63 | * Check Board Identity: | |
64 | * returns 0 if recognized, -1 if unknown | |
65 | */ | |
66 | ||
67 | int checkboard (void) | |
68 | { | |
69 | puts ("Board: SIXNET SXNI855T\n"); | |
70 | return 0; | |
71 | } | |
72 | ||
73 | /* ------------------------------------------------------------------------- */ | |
74 | ||
75 | #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) | |
76 | #error "SXNI855T has no PCMCIA port" | |
77 | #endif /* CFG_CMD_PCMCIA */ | |
78 | ||
79 | /* ------------------------------------------------------------------------- */ | |
80 | ||
81 | #define _not_used_ 0xffffffff | |
82 | ||
83 | /* UPMB table for dual UART. */ | |
84 | ||
85 | /* this table is for 50MHz operation, it should work at all lower speeds */ | |
86 | const uint duart_table[] = | |
87 | { | |
88 | /* single read. (offset 0 in upm RAM) */ | |
89 | 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, | |
90 | 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, | |
91 | ||
92 | /* burst read. (offset 8 in upm RAM) */ | |
93 | _not_used_, _not_used_, _not_used_, _not_used_, | |
94 | _not_used_, _not_used_, _not_used_, _not_used_, | |
95 | _not_used_, _not_used_, _not_used_, _not_used_, | |
96 | _not_used_, _not_used_, _not_used_, _not_used_, | |
97 | ||
98 | /* single write. (offset 18 in upm RAM) */ | |
99 | 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, | |
100 | 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, | |
101 | ||
102 | /* burst write. (offset 20 in upm RAM) */ | |
103 | _not_used_, _not_used_, _not_used_, _not_used_, | |
104 | _not_used_, _not_used_, _not_used_, _not_used_, | |
105 | _not_used_, _not_used_, _not_used_, _not_used_, | |
106 | _not_used_, _not_used_, _not_used_, _not_used_, | |
107 | ||
108 | /* refresh. (offset 30 in upm RAM) */ | |
109 | _not_used_, _not_used_, _not_used_, _not_used_, | |
110 | _not_used_, _not_used_, _not_used_, _not_used_, | |
111 | _not_used_, _not_used_, _not_used_, _not_used_, | |
112 | ||
113 | /* exception. (offset 3c in upm RAM) */ | |
114 | _not_used_, _not_used_, _not_used_, _not_used_, | |
115 | }; | |
116 | ||
117 | /* Load FPGA very early in boot sequence, since it must be | |
118 | * loaded before the 16C2550 serial channels can be used as | |
119 | * console channels. | |
120 | * | |
121 | * Note: Much of the configuration is not complete. The | |
122 | * stack is in DPRAM since SDRAM has not been initialized, | |
123 | * so the stack must be kept small. Global variables | |
124 | * are still in FLASH, so they cannot be written. | |
125 | * Only the FLASH, DPRAM, immap and FPGA can be addressed, | |
126 | * the other chip selects may not have been initialized. | |
127 | * The clocks have been initialized, so udelay() can be | |
128 | * used. | |
129 | */ | |
130 | #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ | |
131 | #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ | |
132 | #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ | |
133 | #define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */ | |
134 | ||
135 | int board_postclk_init (void) | |
136 | { | |
137 | ||
138 | /* the data to load to the XCSxxXL FPGA */ | |
139 | static const unsigned char fpgadata[] = { | |
140 | # include "fpgadata.c" | |
141 | }; | |
142 | ||
143 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
144 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
145 | #define porta (immap->im_ioport.iop_padat) | |
146 | const unsigned char* pdata; | |
147 | ||
148 | /* /INITFPGA and DONEFPGA signals are inputs */ | |
149 | immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); | |
150 | ||
151 | /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ | |
152 | porta &= ~FPGA_PROGRAM_L; | |
153 | ||
154 | /* Set FPGA as an output */ | |
155 | immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; | |
156 | ||
157 | /* delay a little to make sure FPGA sees it, really | |
158 | * only need less than a microsecond. | |
159 | */ | |
160 | udelay(10); | |
161 | ||
162 | /* unassert /PROGRAM */ | |
163 | porta |= FPGA_PROGRAM_L; | |
164 | ||
165 | /* delay while FPGA does last erase, indicated by | |
166 | * /INITFPGA going high. This should happen within a | |
167 | * few milliseconds. | |
168 | */ | |
169 | /* ### FIXME - a timeout check would be good, maybe flash | |
170 | * the status LED to indicate the error? | |
171 | */ | |
172 | while ((porta & FPGA_INIT_L) == 0) | |
173 | ; /* waiting */ | |
174 | ||
175 | /* write program data to FPGA at the programming address | |
176 | * so extra /CS1 strobes at end of configuration don't actually | |
177 | * write to any registers. | |
178 | */ | |
179 | fpga = 0xff; /* first write is ignored */ | |
180 | fpga = 0xff; /* fill byte */ | |
181 | fpga = 0xff; /* fill byte */ | |
182 | fpga = 0x4f; /* preamble code */ | |
183 | fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ | |
184 | fpga = 0x4b; /* field check code */ | |
185 | ||
186 | pdata = fpgadata; | |
187 | /* while no error write out each of the 28 byte frames */ | |
188 | while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L | |
189 | && pdata < fpgadata + sizeof(fpgadata)) { | |
190 | ||
191 | fpga = 0x4f; /* preamble code */ | |
192 | ||
193 | /* 21 bytes of data in a frame */ | |
194 | fpga = *(pdata++); fpga = *(pdata++); | |
195 | fpga = *(pdata++); fpga = *(pdata++); | |
196 | fpga = *(pdata++); fpga = *(pdata++); | |
197 | fpga = *(pdata++); fpga = *(pdata++); | |
198 | fpga = *(pdata++); fpga = *(pdata++); | |
199 | fpga = *(pdata++); fpga = *(pdata++); | |
200 | fpga = *(pdata++); fpga = *(pdata++); | |
201 | fpga = *(pdata++); fpga = *(pdata++); | |
202 | fpga = *(pdata++); fpga = *(pdata++); | |
203 | fpga = *(pdata++); fpga = *(pdata++); | |
204 | fpga = *(pdata++); | |
205 | ||
206 | fpga = 0x4b; /* field check code */ | |
207 | fpga = 0xff; /* extended write cycle */ | |
208 | fpga = 0x4b; /* extended write cycle | |
209 | * (actually 0x4b from bitgen.exe) | |
210 | */ | |
211 | fpga = 0xff; /* extended write cycle */ | |
212 | fpga = 0xff; /* extended write cycle */ | |
213 | fpga = 0xff; /* extended write cycle */ | |
214 | } | |
215 | ||
216 | fpga = 0xff; /* startup byte */ | |
217 | fpga = 0xff; /* startup byte */ | |
218 | fpga = 0xff; /* startup byte */ | |
219 | fpga = 0xff; /* startup byte */ | |
220 | ||
221 | #if 0 /* ### FIXME */ | |
222 | /* If didn't load all the data or FPGA_DONE is low the load failed. | |
223 | * Maybe someday stop here and flash the status LED? The console | |
224 | * is not configured, so can't print an error message. Can't write | |
225 | * global variables to set a flag (except gd?). | |
226 | * For now it must work. | |
227 | */ | |
228 | #endif | |
229 | ||
230 | /* Now that the FPGA is loaded, set up the Dual UART chip | |
231 | * selects. Must be done here since it may be used as the console. | |
232 | */ | |
233 | upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); | |
234 | ||
235 | memctl->memc_mbmr = DUART_MBMR; | |
236 | memctl->memc_or5 = DUART_OR_VALUE; | |
237 | memctl->memc_br5 = DUART_BR5_VALUE; | |
238 | memctl->memc_or6 = DUART_OR_VALUE; | |
239 | memctl->memc_br6 = DUART_BR6_VALUE; | |
240 | ||
241 | return (0); | |
242 | } | |
243 | ||
244 | /* ------------------------------------------------------------------------- */ | |
245 | ||
246 | /* base address for SRAM, assume 32-bit port, valid */ | |
247 | #define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V) | |
248 | ||
249 | /* up to 64MB - will be adjusted for actual size */ | |
250 | #define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \ | |
251 | | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) | |
252 | /* | |
253 | * Miscellaneous platform dependent initializations after running in RAM. | |
254 | */ | |
255 | ||
256 | int misc_init_r (void) | |
257 | { | |
258 | DECLARE_GLOBAL_DATA_PTR; | |
259 | ||
260 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
261 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
506f0441 WD |
262 | char* s; |
263 | char* e; | |
264 | int reg; | |
5b1d7137 WD |
265 | bd_t *bd = gd->bd; |
266 | ||
267 | memctl->memc_or2 = NVRAM_OR_PRELIM; | |
268 | memctl->memc_br2 = NVRAM_BR_VALUE; | |
269 | ||
270 | /* Is there any SRAM? Is it 16 or 32 bits wide? */ | |
271 | ||
272 | /* First look for 32-bit SRAM */ | |
273 | bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); | |
274 | ||
275 | if (bd->bi_sramsize == 0) { | |
276 | /* no 32-bit SRAM, but there could be 16-bit SRAM since | |
277 | * it would report size 0 when configured for 32-bit bus. | |
278 | * Try again with a 16-bit bus. | |
279 | */ | |
280 | memctl->memc_br2 |= BR_PS_16; | |
281 | bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); | |
282 | } | |
283 | ||
284 | if (bd->bi_sramsize == 0) { | |
285 | memctl->memc_br2 = 0; /* disable select since nothing there */ | |
286 | } | |
287 | else { | |
288 | /* adjust or2 for actual size of SRAM */ | |
289 | memctl->memc_or2 |= ORMASK(bd->bi_sramsize); | |
290 | bd->bi_sramstart = CFG_SRAM_BASE; | |
291 | printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); | |
292 | } | |
293 | ||
294 | ||
295 | /* set standard MPC8xx clock so kernel will see the time | |
296 | * even if it doesn't have a DS1306 clock driver. | |
297 | * This helps with experimenting with standard kernels. | |
298 | */ | |
299 | { | |
300 | ulong tim; | |
301 | struct rtc_time tmp; | |
302 | ||
303 | rtc_get(&tmp); /* get time from DS1306 RTC */ | |
304 | ||
305 | /* convert to seconds since 1970 */ | |
306 | tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, | |
307 | tmp.tm_hour, tmp.tm_min, tmp.tm_sec); | |
308 | ||
309 | immap->im_sitk.sitk_rtck = KAPWR_KEY; | |
310 | immap->im_sit.sit_rtc = tim; | |
311 | } | |
312 | ||
506f0441 WD |
313 | /* set up ethernet address for SCC ethernet. If eth1addr |
314 | * is present it gets a unique address, otherwise it | |
315 | * shares the FEC address. | |
5b1d7137 | 316 | */ |
506f0441 WD |
317 | s = getenv("eth1addr"); |
318 | if (s == NULL) | |
319 | s = getenv("ethaddr"); | |
320 | for (reg=0; reg<6; ++reg) { | |
321 | bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0; | |
322 | if (s) | |
323 | s = (*e) ? e+1 : e; | |
324 | } | |
5b1d7137 | 325 | |
5b1d7137 WD |
326 | return (0); |
327 | } | |
328 | ||
7a8e9bed WD |
329 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
330 | void nand_init(void) | |
331 | { | |
332 | nand_probe(CFG_DFLASH_BASE); /* see if any NAND flash present */ | |
333 | if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { | |
334 | puts("NAND: "); | |
335 | print_size(nand_dev_desc[0].totlen, "\n"); | |
336 | } | |
337 | } | |
338 | #endif | |
339 | ||
5b1d7137 WD |
340 | /* ------------------------------------------------------------------------- */ |
341 | ||
342 | /* | |
343 | * Check memory range for valid RAM. A simple memory test determines | |
344 | * the actually available RAM size between addresses `base' and | |
345 | * `base + maxsize'. | |
346 | * | |
347 | * The memory size MUST be a power of 2 for this to work. | |
348 | * | |
506f0441 | 349 | * The only memory modified is 8 bytes at offset 0. This is important |
5b1d7137 WD |
350 | * since for the SRAM this location is reserved for autosizing, so if |
351 | * it is modified and the board is reset before ram_size() completes | |
352 | * no damage is done. Normally even the memory at 0 is preserved. The | |
353 | * higher SRAM addresses may contain battery backed RAM disk data which | |
354 | * must never be corrupted. | |
355 | */ | |
356 | ||
357 | static long ram_size(ulong *base, long maxsize) | |
358 | { | |
359 | volatile long *test_addr; | |
360 | volatile long *base_addr = base; | |
5b1d7137 WD |
361 | ulong ofs; /* byte offset from base_addr */ |
362 | ulong save; /* to make test non-destructive */ | |
506f0441 | 363 | ulong save2; /* to make test non-destructive */ |
5b1d7137 WD |
364 | long ramsize = -1; /* size not determined yet */ |
365 | ||
366 | save = *base_addr; /* save value at 0 so can restore */ | |
506f0441 | 367 | save2 = *(base_addr+1); /* save value at 4 so can restore */ |
5b1d7137 WD |
368 | |
369 | /* is any SRAM present? */ | |
370 | *base_addr = 0x5555aaaa; | |
371 | ||
506f0441 WD |
372 | /* It is important to drive the data bus with different data so |
373 | * it doesn't remember the value and look like RAM that isn't there. | |
5b1d7137 | 374 | */ |
506f0441 | 375 | *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ |
5b1d7137 WD |
376 | |
377 | if (*base_addr != 0x5555aaaa) | |
378 | ramsize = 0; /* no RAM present, or defective */ | |
379 | else { | |
380 | *base_addr = 0xaaaa5555; | |
506f0441 | 381 | *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ |
5b1d7137 WD |
382 | if (*base_addr != 0xaaaa5555) |
383 | ramsize = 0; /* no RAM present, or defective */ | |
384 | } | |
385 | ||
386 | /* now size it if any is present */ | |
387 | for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { | |
388 | test_addr = (long*)((long)base_addr + ofs); /* location to test */ | |
389 | ||
390 | *base_addr = ~*test_addr; | |
391 | if (*base_addr == *test_addr) | |
392 | ramsize = ofs; /* wrapped back to 0, so this is the size */ | |
393 | } | |
394 | ||
395 | *base_addr = save; /* restore value at 0 */ | |
506f0441 | 396 | *(base_addr+1) = save2; /* restore value at 4 */ |
5b1d7137 WD |
397 | return (ramsize); |
398 | } | |
399 | ||
400 | /* ------------------------------------------------------------------------- */ | |
401 | /* sdram table based on the FADS manual */ | |
402 | /* for chip MB811171622A-100 */ | |
403 | ||
404 | /* this table is for 50MHz operation, it should work at all lower speeds */ | |
405 | ||
406 | const uint sdram_table[] = | |
407 | { | |
408 | /* single read. (offset 0 in upm RAM) */ | |
409 | 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, | |
410 | 0x1ff77c47, | |
411 | ||
412 | /* precharge and Mode Register Set initialization (offset 5). | |
413 | * This is also entered at offset 6 to do Mode Register Set | |
414 | * without the precharge. | |
415 | */ | |
416 | 0x1ff77c34, 0xefeabc34, 0x1fb57c35, | |
417 | ||
418 | /* burst read. (offset 8 in upm RAM) */ | |
419 | 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, | |
420 | 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, | |
421 | _not_used_, _not_used_, _not_used_, _not_used_, | |
422 | _not_used_, _not_used_, _not_used_, _not_used_, | |
423 | ||
424 | /* single write. (offset 18 in upm RAM) */ | |
425 | /* FADS had 0x1f27fc04, ... | |
426 | * but most other boards have 0x1f07fc04, which | |
427 | * sets GPL0 from A11MPC to 0 1/4 clock earlier, | |
428 | * like the single read. | |
429 | * This seems better so I am going with the change. | |
430 | */ | |
431 | 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, | |
432 | _not_used_, _not_used_, _not_used_, _not_used_, | |
433 | ||
434 | /* burst write. (offset 20 in upm RAM) */ | |
435 | 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, | |
436 | 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, | |
437 | _not_used_, _not_used_, _not_used_, _not_used_, | |
438 | _not_used_, _not_used_, _not_used_, _not_used_, | |
439 | ||
440 | /* refresh. (offset 30 in upm RAM) */ | |
441 | 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, | |
442 | 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, | |
443 | _not_used_, _not_used_, _not_used_, _not_used_, | |
444 | ||
445 | /* exception. (offset 3c in upm RAM) */ | |
446 | 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; | |
447 | ||
448 | /* ------------------------------------------------------------------------- */ | |
449 | ||
450 | #define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ | |
451 | ||
452 | /* precharge and set Mode Register */ | |
453 | #define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
454 | MCR_MB_CS3 | /* chip select */ \ | |
455 | MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ | |
456 | ||
457 | /* set Mode Register, no precharge */ | |
458 | #define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
459 | MCR_MB_CS3 | /* chip select */ \ | |
460 | MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ | |
461 | ||
462 | /* runs refresh loop twice so get 8 refresh cycles */ | |
463 | #define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ | |
464 | MCR_MB_CS3 | /* chip select */ \ | |
465 | MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ | |
466 | ||
467 | /* MAMR values work in either mamr or mbmr */ | |
506f0441 | 468 | #define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ |
5b1d7137 | 469 | ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ |
5b1d7137 | 470 | | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ |
5b1d7137 WD |
471 | | MAMR_RLFA_1X /* Read loop 1 time */ \ |
472 | | MAMR_WLFA_1X /* Write loop 1 time */ \ | |
473 | | MAMR_TLFA_4X) /* Timer loop 4 times */ | |
506f0441 WD |
474 | /* 8 column SDRAM */ |
475 | #define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ | |
476 | | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ | |
477 | | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ | |
5b1d7137 WD |
478 | |
479 | /* 9 column SDRAM */ | |
506f0441 WD |
480 | #define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ |
481 | | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ | |
482 | | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ | |
5b1d7137 WD |
483 | |
484 | /* base address 0, 32-bit port, SDRAM UPM, valid */ | |
485 | #define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) | |
486 | ||
487 | /* up to 256MB, SAM, G5LS - will be adjusted for actual size */ | |
488 | #define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) | |
489 | ||
490 | /* This is the Mode Select Register value for the SDRAM. | |
491 | * Burst length: 4 | |
492 | * Burst Type: sequential | |
493 | * CAS Latency: 2 | |
494 | * Write Burst Length: burst | |
495 | */ | |
496 | #define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ | |
497 | ||
498 | /* ------------------------------------------------------------------------- */ | |
499 | ||
500 | long int initdram(int board_type) | |
501 | { | |
502 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
503 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
504 | uint size_sdram = 0; | |
505 | uint size_sdram9 = 0; | |
506 | uint base = 0; /* SDRAM must start at 0 */ | |
507 | int i; | |
508 | ||
509 | upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); | |
510 | ||
511 | /* Configure the refresh (mostly). This needs to be | |
512 | * based upon processor clock speed and optimized to provide | |
513 | * the highest level of performance. | |
514 | * | |
515 | * Preliminary prescaler for refresh. | |
516 | * This value is selected for four cycles in 31.2 us, | |
517 | * which gives 8192 cycles in 64 milliseconds. | |
518 | * This may be too fast, but works for any memory. | |
519 | * It is adjusted to 4096 cycles in 64 milliseconds if | |
520 | * possible once we know what memory we have. | |
521 | * | |
522 | * We have to be careful changing UPM registers after we | |
523 | * ask it to run these commands. | |
524 | * | |
525 | * PTA - periodic timer period for our design is | |
526 | * 50 MHz x 31.2us | |
527 | * --------------- = 195 | |
528 | * 1 x 8 x 1 | |
529 | * | |
530 | * 50MHz clock | |
531 | * 31.2us refresh interval | |
532 | * SCCR[DFBRG] 0 | |
533 | * PTP divide by 8 | |
534 | * 1 chip select | |
535 | */ | |
536 | memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ | |
537 | memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ | |
538 | ||
539 | /* The SDRAM Mode Register value is shifted left 2 bits since | |
540 | * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. | |
541 | */ | |
542 | memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ | |
543 | udelay(200); /* SDRAM needs 200uS before set it up */ | |
544 | ||
545 | /* Now run the precharge/nop/mrs commands. */ | |
546 | memctl->memc_mcr = SDRAM_MCR_PRE; | |
547 | udelay(2); | |
548 | ||
549 | /* Run 8 refresh cycles (2 sets of 4) */ | |
550 | memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ | |
551 | udelay(2); | |
552 | ||
553 | /* some brands want Mode Register set after the refresh | |
554 | * cycles. This shouldn't hurt anything for the brands | |
555 | * that were happy with the first time we set it. | |
556 | */ | |
557 | memctl->memc_mcr = SDRAM_MCR_MRS; | |
558 | udelay(2); | |
559 | ||
560 | memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ | |
561 | memctl->memc_or3 = SDRAM_OR_PRELIM; | |
562 | memctl->memc_br3 = SDRAM_BR_VALUE + base; | |
563 | ||
564 | /* Some brands need at least 10 DRAM accesses to stabilize. | |
565 | * It wont hurt the brands that don't. | |
566 | */ | |
567 | for (i=0; i<10; ++i) { | |
568 | volatile ulong *addr = (volatile ulong *)base; | |
569 | ulong val; | |
570 | ||
571 | val = *(addr + i); | |
572 | *(addr + i) = val; | |
573 | } | |
574 | ||
575 | /* Check SDRAM memory Size in 8 column mode. | |
576 | * For a 9 column memory we will get half the actual size. | |
577 | */ | |
578 | size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); | |
579 | ||
580 | /* Check SDRAM memory Size in 9 column mode. | |
581 | * For an 8 column memory we will see at most 4 megabytes. | |
582 | */ | |
583 | memctl->memc_mamr = SDRAM_MAMR_9COL; | |
584 | size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); | |
585 | ||
586 | if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ | |
587 | size_sdram = size_sdram9; | |
588 | else /* go back to 8 columns */ | |
589 | memctl->memc_mamr = SDRAM_MAMR_8COL; | |
590 | ||
591 | /* adjust or3 for actual size of SDRAM | |
592 | */ | |
593 | memctl->memc_or3 |= ORMASK(size_sdram); | |
594 | ||
595 | /* Adjust refresh rate depending on SDRAM type. | |
596 | * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave | |
597 | * it at the current (fast) rate. | |
598 | * For 16, 64 and 128 MBit half the rate will do. | |
599 | */ | |
600 | if (size_sdram <= 32 * 1024 * 1024) | |
601 | memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ | |
602 | ||
603 | return (size_sdram); | |
604 | } | |
605 |