[people/ms/u-boot.git] / board / socrates / nand.c

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#if defined(CONFIG_SYS_NAND_BASE)
#include <nand.h>
#include <asm/errno.h>
#include <asm/io.h>

static int state;
static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
static u_char sc_nand_read_byte(struct mtd_info *mtd);
static u16 sc_nand_read_word(struct mtd_info *mtd);
static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
static int sc_nand_device_ready(struct mtd_info *mtdinfo);

#define FPGA_NAND_CMD_MASK		(0x7 << 28)
#define FPGA_NAND_CMD_COMMAND		(0x0 << 28)
#define FPGA_NAND_CMD_ADDR		(0x1 << 28)
#define FPGA_NAND_CMD_READ		(0x2 << 28)
#define FPGA_NAND_CMD_WRITE		(0x3 << 28)
#define FPGA_NAND_BUSY			(0x1 << 15)
#define FPGA_NAND_ENABLE		(0x1 << 31)
#define FPGA_NAND_DATA_SHIFT		16

/**
 * sc_nand_write_byte -  write one byte to the chip
 * @mtd:	MTD device structure
 * @byte:	pointer to data byte to write
 */
static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
{
	sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
}

/**
 * sc_nand_write_buf -  write buffer to chip
 * @mtd:	MTD device structure
 * @buf:	data buffer
 * @len:	number of bytes to write
 */
static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;

	for (i = 0; i < len; i++) {
		out_be32(this->IO_ADDR_W,
			 state | (buf[i] << FPGA_NAND_DATA_SHIFT));
	}
}


/**
 * sc_nand_read_byte -  read one byte from the chip
 * @mtd:	MTD device structure
 */
static u_char sc_nand_read_byte(struct mtd_info *mtd)
{
	u8 byte;
	sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
	return byte;
}

/**
 * sc_nand_read_word -  read one word from the chip
 * @mtd:	MTD device structure
 */
static u16 sc_nand_read_word(struct mtd_info *mtd)
{
	u16 word;
	sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
	return word;
}

/**
 * sc_nand_read_buf -  read chip data into buffer
 * @mtd:	MTD device structure
 * @buf:	buffer to store date
 * @len:	number of bytes to read
 */
static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;
	int val;

	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;

	out_be32(this->IO_ADDR_W, val);
	for (i = 0; i < len; i++) {
		buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
	}
}

/**
 * sc_nand_verify_buf -  Verify chip data against buffer
 * @mtd:	MTD device structure
 * @buf:	buffer containing the data to compare
 * @len:	number of bytes to compare
 */
static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;

	for (i = 0; i < len; i++) {
		if (buf[i] != sc_nand_read_byte(mtd));
			return -EFAULT;
	}
	return 0;
}

/**
 * sc_nand_device_ready - Check the NAND device is ready for next command.
 * @mtd:	MTD device structure
 */
static int sc_nand_device_ready(struct mtd_info *mtdinfo)
{
	struct nand_chip *this = mtdinfo->priv;

	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
		return 0; /* busy */
	return 1;
}

/**
 * sc_nand_hwcontrol - NAND control functions wrapper.
 * @mtd:	MTD device structure
 * @cmd:	Command
 */
static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
	if (ctrl & NAND_CTRL_CHANGE) {
		state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);

		switch (ctrl & (NAND_ALE | NAND_CLE)) {
		case 0:
			state |= FPGA_NAND_CMD_WRITE;
			break;

		case NAND_ALE:
			state |= FPGA_NAND_CMD_ADDR;
			break;

		case NAND_CLE:
			state |= FPGA_NAND_CMD_COMMAND;
			break;

		default:
			printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
		}

		if (ctrl & NAND_NCE)
			state |= FPGA_NAND_ENABLE;
	}

	if (cmd != NAND_CMD_NONE)
		sc_nand_write_byte(mtdinfo, cmd);
}

int board_nand_init(struct nand_chip *nand)
{
	nand->cmd_ctrl = sc_nand_hwcontrol;
	nand->ecc.mode = NAND_ECC_SOFT;
	nand->dev_ready = sc_nand_device_ready;
	nand->read_byte = sc_nand_read_byte;
	nand->read_word = sc_nand_read_word;
	nand->write_buf = sc_nand_write_buf;
	nand->read_buf = sc_nand_read_buf;
	nand->verify_buf = sc_nand_verify_buf;

	return 0;
}

#endif
Commit	Line	Data
fd51b0e0 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
fd51b0e0 SP	6	*/
	7
	8	#include <common.h>
	9
6d0f6bcf	10	#if defined(CONFIG_SYS_NAND_BASE)
fd51b0e0 SP	11	#include <nand.h>
	12	#include <asm/errno.h>
	13	#include <asm/io.h>
	14
	15	static int state;
169de905 MV	16	static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
	17	static void sc_nand_write_buf(struct mtd_info mtd, const u_char buf, int len);
	18	static u_char sc_nand_read_byte(struct mtd_info *mtd);
	19	static u16 sc_nand_read_word(struct mtd_info *mtd);
	20	static void sc_nand_read_buf(struct mtd_info mtd, u_char buf, int len);
	21	static int sc_nand_verify_buf(struct mtd_info mtd, const u_char buf, int len);
	22	static int sc_nand_device_ready(struct mtd_info *mtdinfo);
fd51b0e0 SP	23
fd51b0e0 SP	24	#define FPGA_NAND_CMD_MASK (0x7 << 28)
68cf19aa	25	#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
fd51b0e0 SP	26	#define FPGA_NAND_CMD_ADDR (0x1 << 28)
	27	#define FPGA_NAND_CMD_READ (0x2 << 28)
	28	#define FPGA_NAND_CMD_WRITE (0x3 << 28)
	29	#define FPGA_NAND_BUSY (0x1 << 15)
	30	#define FPGA_NAND_ENABLE (0x1 << 31)
68cf19aa	31	#define FPGA_NAND_DATA_SHIFT 16
fd51b0e0 SP	32
fd51b0e0 SP	33	/**
169de905	34	* sc_nand_write_byte - write one byte to the chip
fd51b0e0 SP	35	* @mtd: MTD device structure
	36	* @byte: pointer to data byte to write
	37	*/
169de905	38	static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
fd51b0e0	39	{
169de905	40	sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
fd51b0e0 SP	41	}
fd51b0e0 SP	42
fd51b0e0	43	/**
169de905	44	* sc_nand_write_buf - write buffer to chip
fd51b0e0 SP	45	* @mtd: MTD device structure
	46	* @buf: data buffer
	47	* @len: number of bytes to write
	48	*/
169de905	49	static void sc_nand_write_buf(struct mtd_info mtd, const u_char buf, int len)
fd51b0e0 SP	50	{
	51	int i;
	52	struct nand_chip *this = mtd->priv;
fd51b0e0 SP	53
fd51b0e0 SP	54	for (i = 0; i < len; i++) {
68cf19aa SW	55	out_be32(this->IO_ADDR_W,
68cf19aa SW	56	state \| (buf[i] << FPGA_NAND_DATA_SHIFT));
fd51b0e0 SP	57	}
	58	}
	59
	60
	61	/**
169de905	62	* sc_nand_read_byte - read one byte from the chip
fd51b0e0 SP	63	* @mtd: MTD device structure
fd51b0e0 SP	64	*/
169de905	65	static u_char sc_nand_read_byte(struct mtd_info *mtd)
fd51b0e0 SP	66	{
fd51b0e0 SP	67	u8 byte;
169de905	68	sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
fd51b0e0 SP	69	return byte;
	70	}
	71
	72	/**
169de905	73	* sc_nand_read_word - read one word from the chip
fd51b0e0 SP	74	* @mtd: MTD device structure
fd51b0e0 SP	75	*/
169de905	76	static u16 sc_nand_read_word(struct mtd_info *mtd)
fd51b0e0 SP	77	{
fd51b0e0 SP	78	u16 word;
169de905	79	sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
fd51b0e0 SP	80	return word;
	81	}
	82
	83	/**
169de905	84	* sc_nand_read_buf - read chip data into buffer
fd51b0e0 SP	85	* @mtd: MTD device structure
	86	* @buf: buffer to store date
	87	* @len: number of bytes to read
	88	*/
169de905	89	static void sc_nand_read_buf(struct mtd_info mtd, u_char buf, int len)
fd51b0e0 SP	90	{
	91	int i;
	92	struct nand_chip *this = mtd->priv;
	93	int val;
	94
	95	val = (state & FPGA_NAND_ENABLE) \| FPGA_NAND_CMD_READ;
	96
	97	out_be32(this->IO_ADDR_W, val);
	98	for (i = 0; i < len; i++) {
	99	buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
	100	}
	101	}
	102
	103	/**
169de905	104	* sc_nand_verify_buf - Verify chip data against buffer
fd51b0e0 SP	105	* @mtd: MTD device structure
	106	* @buf: buffer containing the data to compare
	107	* @len: number of bytes to compare
	108	*/
169de905	109	static int sc_nand_verify_buf(struct mtd_info mtd, const u_char buf, int len)
fd51b0e0 SP	110	{
	111	int i;
	112
	113	for (i = 0; i < len; i++) {
169de905	114	if (buf[i] != sc_nand_read_byte(mtd));
68cf19aa	115	return -EFAULT;
fd51b0e0 SP	116	}
	117	return 0;
	118	}
	119
	120	/**
169de905	121	* sc_nand_device_ready - Check the NAND device is ready for next command.
fd51b0e0 SP	122	* @mtd: MTD device structure
fd51b0e0 SP	123	*/
169de905	124	static int sc_nand_device_ready(struct mtd_info *mtdinfo)
fd51b0e0 SP	125	{
	126	struct nand_chip *this = mtdinfo->priv;
	127
	128	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
	129	return 0; /* busy */
	130	return 1;
	131	}
	132
	133	/**
169de905	134	* sc_nand_hwcontrol - NAND control functions wrapper.
fd51b0e0 SP	135	* @mtd: MTD device structure
	136	* @cmd: Command
	137	*/
169de905	138	static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
fd51b0e0	139	{
68cf19aa SW	140	if (ctrl & NAND_CTRL_CHANGE) {
	141	state &= ~(FPGA_NAND_CMD_MASK \| FPGA_NAND_ENABLE);
	142
	143	switch (ctrl & (NAND_ALE \| NAND_CLE)) {
	144	case 0:
	145	state \|= FPGA_NAND_CMD_WRITE;
	146	break;
	147
	148	case NAND_ALE:
	149	state \|= FPGA_NAND_CMD_ADDR;
	150	break;
fd51b0e0	151
68cf19aa SW	152	case NAND_CLE:
	153	state \|= FPGA_NAND_CMD_COMMAND;
	154	break;
	155
	156	default:
	157	printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
	158	}
	159
	160	if (ctrl & NAND_NCE)
	161	state \|= FPGA_NAND_ENABLE;
fd51b0e0	162	}
68cf19aa SW	163
68cf19aa SW	164	if (cmd != NAND_CMD_NONE)
169de905	165	sc_nand_write_byte(mtdinfo, cmd);
fd51b0e0 SP	166	}
	167
	168	int board_nand_init(struct nand_chip *nand)
	169	{
169de905	170	nand->cmd_ctrl = sc_nand_hwcontrol;
68cf19aa	171	nand->ecc.mode = NAND_ECC_SOFT;
169de905 MV	172	nand->dev_ready = sc_nand_device_ready;
	173	nand->read_byte = sc_nand_read_byte;
	174	nand->read_word = sc_nand_read_word;
	175	nand->write_buf = sc_nand_write_buf;
	176	nand->read_buf = sc_nand_read_buf;
	177	nand->verify_buf = sc_nand_verify_buf;
fd51b0e0 SP	178
	179	return 0;
	180	}
	181
	182	#endif