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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
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2 | /* |
3 | * (C) Copyright 2008 | |
4 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
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5 | */ |
6 | ||
7 | #include <common.h> | |
8 | ||
6d0f6bcf | 9 | #if defined(CONFIG_SYS_NAND_BASE) |
fd51b0e0 | 10 | #include <nand.h> |
1221ce45 | 11 | #include <linux/errno.h> |
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12 | #include <asm/io.h> |
13 | ||
14 | static int state; | |
169de905 MV |
15 | static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte); |
16 | static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); | |
17 | static u_char sc_nand_read_byte(struct mtd_info *mtd); | |
18 | static u16 sc_nand_read_word(struct mtd_info *mtd); | |
19 | static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); | |
169de905 | 20 | static int sc_nand_device_ready(struct mtd_info *mtdinfo); |
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21 | |
22 | #define FPGA_NAND_CMD_MASK (0x7 << 28) | |
68cf19aa | 23 | #define FPGA_NAND_CMD_COMMAND (0x0 << 28) |
fd51b0e0 SP |
24 | #define FPGA_NAND_CMD_ADDR (0x1 << 28) |
25 | #define FPGA_NAND_CMD_READ (0x2 << 28) | |
26 | #define FPGA_NAND_CMD_WRITE (0x3 << 28) | |
27 | #define FPGA_NAND_BUSY (0x1 << 15) | |
28 | #define FPGA_NAND_ENABLE (0x1 << 31) | |
68cf19aa | 29 | #define FPGA_NAND_DATA_SHIFT 16 |
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30 | |
31 | /** | |
169de905 | 32 | * sc_nand_write_byte - write one byte to the chip |
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33 | * @mtd: MTD device structure |
34 | * @byte: pointer to data byte to write | |
35 | */ | |
169de905 | 36 | static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) |
fd51b0e0 | 37 | { |
169de905 | 38 | sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); |
fd51b0e0 SP |
39 | } |
40 | ||
fd51b0e0 | 41 | /** |
169de905 | 42 | * sc_nand_write_buf - write buffer to chip |
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43 | * @mtd: MTD device structure |
44 | * @buf: data buffer | |
45 | * @len: number of bytes to write | |
46 | */ | |
169de905 | 47 | static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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48 | { |
49 | int i; | |
17cb4b8f | 50 | struct nand_chip *this = mtd_to_nand(mtd); |
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51 | |
52 | for (i = 0; i < len; i++) { | |
68cf19aa SW |
53 | out_be32(this->IO_ADDR_W, |
54 | state | (buf[i] << FPGA_NAND_DATA_SHIFT)); | |
fd51b0e0 SP |
55 | } |
56 | } | |
57 | ||
58 | ||
59 | /** | |
169de905 | 60 | * sc_nand_read_byte - read one byte from the chip |
fd51b0e0 SP |
61 | * @mtd: MTD device structure |
62 | */ | |
169de905 | 63 | static u_char sc_nand_read_byte(struct mtd_info *mtd) |
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64 | { |
65 | u8 byte; | |
169de905 | 66 | sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); |
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67 | return byte; |
68 | } | |
69 | ||
70 | /** | |
169de905 | 71 | * sc_nand_read_word - read one word from the chip |
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72 | * @mtd: MTD device structure |
73 | */ | |
169de905 | 74 | static u16 sc_nand_read_word(struct mtd_info *mtd) |
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75 | { |
76 | u16 word; | |
169de905 | 77 | sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); |
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78 | return word; |
79 | } | |
80 | ||
81 | /** | |
169de905 | 82 | * sc_nand_read_buf - read chip data into buffer |
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83 | * @mtd: MTD device structure |
84 | * @buf: buffer to store date | |
85 | * @len: number of bytes to read | |
86 | */ | |
169de905 | 87 | static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
fd51b0e0 SP |
88 | { |
89 | int i; | |
17cb4b8f | 90 | struct nand_chip *this = mtd_to_nand(mtd); |
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91 | int val; |
92 | ||
93 | val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; | |
94 | ||
95 | out_be32(this->IO_ADDR_W, val); | |
96 | for (i = 0; i < len; i++) { | |
97 | buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; | |
98 | } | |
99 | } | |
100 | ||
fd51b0e0 | 101 | /** |
169de905 | 102 | * sc_nand_device_ready - Check the NAND device is ready for next command. |
fd51b0e0 SP |
103 | * @mtd: MTD device structure |
104 | */ | |
169de905 | 105 | static int sc_nand_device_ready(struct mtd_info *mtdinfo) |
fd51b0e0 | 106 | { |
17cb4b8f | 107 | struct nand_chip *this = mtd_to_nand(mtdinfo); |
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108 | |
109 | if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) | |
110 | return 0; /* busy */ | |
111 | return 1; | |
112 | } | |
113 | ||
114 | /** | |
169de905 | 115 | * sc_nand_hwcontrol - NAND control functions wrapper. |
fd51b0e0 SP |
116 | * @mtd: MTD device structure |
117 | * @cmd: Command | |
118 | */ | |
169de905 | 119 | static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
fd51b0e0 | 120 | { |
68cf19aa SW |
121 | if (ctrl & NAND_CTRL_CHANGE) { |
122 | state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE); | |
123 | ||
124 | switch (ctrl & (NAND_ALE | NAND_CLE)) { | |
125 | case 0: | |
126 | state |= FPGA_NAND_CMD_WRITE; | |
127 | break; | |
128 | ||
129 | case NAND_ALE: | |
130 | state |= FPGA_NAND_CMD_ADDR; | |
131 | break; | |
fd51b0e0 | 132 | |
68cf19aa SW |
133 | case NAND_CLE: |
134 | state |= FPGA_NAND_CMD_COMMAND; | |
135 | break; | |
136 | ||
137 | default: | |
138 | printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); | |
139 | } | |
140 | ||
141 | if (ctrl & NAND_NCE) | |
142 | state |= FPGA_NAND_ENABLE; | |
fd51b0e0 | 143 | } |
68cf19aa SW |
144 | |
145 | if (cmd != NAND_CMD_NONE) | |
169de905 | 146 | sc_nand_write_byte(mtdinfo, cmd); |
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147 | } |
148 | ||
149 | int board_nand_init(struct nand_chip *nand) | |
150 | { | |
169de905 | 151 | nand->cmd_ctrl = sc_nand_hwcontrol; |
68cf19aa | 152 | nand->ecc.mode = NAND_ECC_SOFT; |
169de905 MV |
153 | nand->dev_ready = sc_nand_device_ready; |
154 | nand->read_byte = sc_nand_read_byte; | |
155 | nand->read_word = sc_nand_read_word; | |
156 | nand->write_buf = sc_nand_write_buf; | |
157 | nand->read_buf = sc_nand_read_buf; | |
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158 | |
159 | return 0; | |
160 | } | |
161 | ||
162 | #endif |