[people/ms/u-boot.git] / board / socrates / sdram.c

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Autodetect onboard DDR SDRAM on 85xx platforms
 *
 * NOTE: Some of the hardcoded values are hardware dependant,
 *       so this should be extended for other future boards
 *       using this routine!
 */
phys_size_t fixed_sdram(void)
{
	struct ccsr_ddr __iomem *ddr =
		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);

	/*
	 * Disable memory controller.
	 */
	ddr->cs0_config = 0;
	ddr->sdram_cfg = 0;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;

	asm ("sync;isync;msync");
	udelay(1000);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
	asm ("sync; isync; msync");
	udelay(1000);

	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
		/*
		 * OK, size detected -> all done
		 */
		return CONFIG_SYS_SDRAM_SIZE<<20;
	}

	return 0;				/* nothing found !		*/
}
#endif

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf ("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf ("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf ("SDRAM test passed.\n");
	return 0;
}
#endif
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	6	*/
5d108ac8 SP	7
5d108ac8 SP	8	#include <common.h>
	9	#include <asm/processor.h>
	10	#include <asm/immap_85xx.h>
5614e71b	11	#include <fsl_ddr_sdram.h>
5d108ac8 SP	12	#include <asm/processor.h>
	13	#include <asm/mmu.h>
	14	#include <spd_sdram.h>
	15
	16
	17	#if !defined(CONFIG_SPD_EEPROM)
	18	/*
	19	* Autodetect onboard DDR SDRAM on 85xx platforms
	20	*
	21	* NOTE: Some of the hardcoded values are hardware dependant,
	22	* so this should be extended for other future boards
	23	* using this routine!
	24	*/
38dba0c2	25	phys_size_t fixed_sdram(void)
5d108ac8	26	{
9a17eb5b YS	27	struct ccsr_ddr __iomem *ddr =
9a17eb5b YS	28	(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
5d108ac8 SP	29
	30	/*
	31	* Disable memory controller.
	32	*/
	33	ddr->cs0_config = 0;
	34	ddr->sdram_cfg = 0;
	35
6d0f6bcf JCPV	36	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	37	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	38	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	39	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	40	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	41	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	42	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	43	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
	44	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
5d108ac8 SP	45
	46	asm ("sync;isync;msync");
	47	udelay(1000);
	48
6d0f6bcf	49	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
5d108ac8 SP	50	asm ("sync; isync; msync");
	51	udelay(1000);
	52
6d0f6bcf	53	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
5d108ac8 SP	54	/*
	55	* OK, size detected -> all done
	56	*/
6d0f6bcf	57	return CONFIG_SYS_SDRAM_SIZE<<20;
5d108ac8 SP	58	}
	59
	60	return 0; /* nothing found ! */
	61	}
	62	#endif
	63
6d0f6bcf	64	#if defined(CONFIG_SYS_DRAM_TEST)
5d108ac8 SP	65	int testdram (void)
5d108ac8 SP	66	{
6d0f6bcf JCPV	67	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	68	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
5d108ac8 SP	69	uint *p;
	70
	71	printf ("SDRAM test phase 1:\n");
	72	for (p = pstart; p < pend; p++)
	73	*p = 0xaaaaaaaa;
	74
	75	for (p = pstart; p < pend; p++) {
	76	if (*p != 0xaaaaaaaa) {
	77	printf ("SDRAM test fails at: %08x\n", (uint) p);
	78	return 1;
	79	}
	80	}
	81
	82	printf ("SDRAM test phase 2:\n");
	83	for (p = pstart; p < pend; p++)
	84	*p = 0x55555555;
	85
	86	for (p = pstart; p < pend; p++) {
	87	if (*p != 0x55555555) {
	88	printf ("SDRAM test fails at: %08x\n", (uint) p);
	89	return 1;
	90	}
	91	}
	92
	93	printf ("SDRAM test passed.\n");
	94	return 0;
	95	}
	96	#endif