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[thirdparty/u-boot.git] / board / socrates / sdram.c
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1/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
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8#include <common.h>
9#include <asm/processor.h>
10#include <asm/immap_85xx.h>
be0bd823 11#include <asm/fsl_ddr_sdram.h>
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12#include <asm/processor.h>
13#include <asm/mmu.h>
14#include <spd_sdram.h>
15
16
17#if !defined(CONFIG_SPD_EEPROM)
18/*
19 * Autodetect onboard DDR SDRAM on 85xx platforms
20 *
21 * NOTE: Some of the hardcoded values are hardware dependant,
22 * so this should be extended for other future boards
23 * using this routine!
24 */
38dba0c2 25phys_size_t fixed_sdram(void)
5d108ac8 26{
e76cd5d4 27 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
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28
29 /*
30 * Disable memory controller.
31 */
32 ddr->cs0_config = 0;
33 ddr->sdram_cfg = 0;
34
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35 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
36 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
40 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
41 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
42 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
43 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
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44
45 asm ("sync;isync;msync");
46 udelay(1000);
47
6d0f6bcf 48 ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
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49 asm ("sync; isync; msync");
50 udelay(1000);
51
6d0f6bcf 52 if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
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53 /*
54 * OK, size detected -> all done
55 */
6d0f6bcf 56 return CONFIG_SYS_SDRAM_SIZE<<20;
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57 }
58
59 return 0; /* nothing found ! */
60}
61#endif
62
6d0f6bcf 63#if defined(CONFIG_SYS_DRAM_TEST)
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64int testdram (void)
65{
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66 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
67 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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68 uint *p;
69
70 printf ("SDRAM test phase 1:\n");
71 for (p = pstart; p < pend; p++)
72 *p = 0xaaaaaaaa;
73
74 for (p = pstart; p < pend; p++) {
75 if (*p != 0xaaaaaaaa) {
76 printf ("SDRAM test fails at: %08x\n", (uint) p);
77 return 1;
78 }
79 }
80
81 printf ("SDRAM test phase 2:\n");
82 for (p = pstart; p < pend; p++)
83 *p = 0x55555555;
84
85 for (p = pstart; p < pend; p++) {
86 if (*p != 0x55555555) {
87 printf ("SDRAM test fails at: %08x\n", (uint) p);
88 return 1;
89 }
90 }
91
92 printf ("SDRAM test passed.\n");
93 return 0;
94}
95#endif