[people/ms/u-boot.git] / board / socrates / socrates.c

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <i2c.h>
#include <mb862xx.h>
#include <video_fb.h>
#include "upm_table.h"

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */
extern GraphicDevice mb862xx;

void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	char buf[64];
	int f;
	int i = getenv_f("serial#", buf, sizeof(buf));
#ifdef CONFIG_PCI
	char *src;
#endif

	puts("Board: Socrates");
	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

#ifdef CONFIG_PCI
	/* Check the PCI_clk sel bit */
	if (in_be32(&gur->porpllsr) & (1<<15)) {
		src = "SYSCLK";
		f = CONFIG_SYS_CLK_FREQ;
	} else {
		src = "PCI_CLK";
		f = CONFIG_PCI_CLK_FREQ;
	}
	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
#else
	printf ("PCI1:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();
	return 0;
}

int misc_init_r (void)
{
	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
		set_lbc_br(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
	}

	/*
	 * Check if only one FLASH bank is available
	 */
	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(1, 0);
		set_lbc_br(1, 0);

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect (FLAG_PROTECT_CLEAR,
			       gd->bd->bi_flashstart, 0xffffffff,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR,
			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR_REDUND,
			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
	}

	return 0;
}

/*
 * Initialize Local Bus
 */
void local_bus_init (void)
{
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	sys_info_t sysinfo;
	uint clkdiv;
	uint lbc_mhz;
	uint lcrr = CONFIG_SYS_LBC_LCRR;

	get_sys_info (&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;

	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	if (lbc_mhz >= 66)
		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32 (&lbc->lcrr, lcrr);
	asm ("sync;isync;msync");

	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */

	/* Init UPMA for FPGA access */
	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));

	/* Init UPMB for Lime controller access */
	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY |
				     PCI_COMMAND_MASTER}},
	{}
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc85xxads_config_table,
#endif
};

#endif /* CONFIG_PCI */


void pci_init_board (void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
	udelay(200);
	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );

	return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	u32 val[12];
	int rc, i = 0;

	ft_cpu_setup(blob, bd);

	/* Fixup NOR FLASH mapping */
	val[i++] = 0;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = gd->bd->bi_flashstart;
	val[i++] = gd->bd->bi_flashsize;

	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
		/* Fixup LIME mapping */
		val[i++] = 2;			/* chip select number */
		val[i++] = 0;			/* always 0 */
		val[i++] = CONFIG_SYS_LIME_BASE;
		val[i++] = CONFIG_SYS_LIME_SIZE;
	}

	/* Fixup FPGA mapping */
	val[i++] = 3;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = CONFIG_SYS_FPGA_BASE;
	val[i++] = CONFIG_SYS_FPGA_SIZE;

	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
				  val, i * sizeof(u32), 1);
	if (rc)
		printf("Unable to update localbus ranges, err=%s\n",
		       fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

#define DEFAULT_BRIGHTNESS	25
#define BACKLIGHT_ENABLE	(1 << 31)

static const gdc_regs init_regs [] =
{
	{0x0100, 0x00010f00},
	{0x0020, 0x801901df},
	{0x0024, 0x00000000},
	{0x0028, 0x00000000},
	{0x002c, 0x00000000},
	{0x0110, 0x00000000},
	{0x0114, 0x00000000},
	{0x0118, 0x01df0320},
	{0x0004, 0x041f0000},
	{0x0008, 0x031f031f},
	{0x000c, 0x017f0349},
	{0x0010, 0x020c0000},
	{0x0014, 0x01df01e9},
	{0x0018, 0x00000000},
	{0x001c, 0x01e00320},
	{0x0100, 0x80010f00},
	{0x0, 0x0}
};

const gdc_regs *board_get_regs (void)
{
	return init_regs;
}

int lime_probe(void)
{
	uint cfg_br2;
	uint cfg_or2;
	int type;

	cfg_br2 = get_lbc_br(2);
	cfg_or2 = get_lbc_or(2);

	/* Configure GPCM for CS2 */
	set_lbc_br(2, 0);
	set_lbc_or(2, 0xfc000410);
	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);

	/* Get controller type */
	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);

	/* Restore previous CS2 configuration */
	set_lbc_br(2, 0);
	set_lbc_or(2, cfg_or2);
	set_lbc_br(2, cfg_br2);

	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}

/* Returns Lime base address */
unsigned int board_video_init (void)
{
	if (!lime_probe())
		return 0;

	mb862xx.winSizeX = 800;
	mb862xx.winSizeY = 480;
	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	mb862xx.gdfBytesPP = 2;

	return CONFIG_SYS_LIME_BASE;
}

#define W83782D_REG_CFG		0x40
#define W83782D_REG_BANK_SEL	0x4e
#define W83782D_REG_ADCCLK	0x4b
#define W83782D_REG_BEEP_CTRL	0x4d
#define W83782D_REG_BEEP_CTRL2	0x57
#define W83782D_REG_PWMOUT1	0x5b
#define W83782D_REG_VBAT	0x5d

static int w83782d_hwmon_init(void)
{
	u8 buf;

	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
		return -1;

	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);

	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
		      buf | 0x80);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);

	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
		      (buf & 0xf4) | 0x01);
	return 0;
}

static void board_backlight_brightness(int br)
{
	u32 reg;
	u8 buf;
	u8 old_buf;

	/* Select bank 0 */
	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
		goto err;
	else
		buf = old_buf & 0xf8;

	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
		goto err;

	if (br > 0) {
		/* PWMOUT1 duty cycle ctrl */
		buf = 255 / (100 / br);
		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
			goto err;

		/* LEDs on */
		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
		if (!(reg & BACKLIGHT_ENABLE));
			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
				 reg | BACKLIGHT_ENABLE);
	} else {
		buf = 0;
		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
			goto err;

		/* LEDs off */
		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
		reg &= ~BACKLIGHT_ENABLE;
		out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
	}
	/* Restore previous bank setting */
	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
		goto err;

	return;
err:
	printf("W83782G I2C access failed\n");
}

void board_backlight_switch (int flag)
{
	char * param;
	int rc;

	if (w83782d_hwmon_init())
		printf ("hwmon IC init failed\n");

	if (flag) {
		param = getenv("brightness");
		rc = param ? simple_strtol(param, NULL, 10) : -1;
		if (rc < 0)
			rc = DEFAULT_BRIGHTNESS;
	} else {
		rc = 0;
	}
	board_backlight_brightness(rc);
}

#if defined(CONFIG_CONSOLE_EXTRA_INFO)
/*
 * Return text to be printed besides the logo.
 */
void video_get_info_str (int line_number, char *info)
{
	if (line_number == 1) {
		strcpy (info, " Board: Socrates");
	} else {
		info [0] = '\0';
	}
}
#endif
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Copyright 2004 Freescale Semiconductor.
	6	* (C) Copyright 2002,2003, Motorola Inc.
	7	* Xianghua Xiao, (X.Xiao@motorola.com)
	8	*
	9	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	12	*/
	13
	14	#include <common.h>
	15	#include <pci.h>
	16	#include <asm/processor.h>
	17	#include <asm/immap_85xx.h>
	18	#include <ioports.h>
	19	#include <flash.h>
e18575d5 SP	20	#include <libfdt.h>
e18575d5 SP	21	#include <fdt_support.h>
e1eb0e25	22	#include <asm/io.h>
fb661ea4	23	#include <i2c.h>
	24	#include <mb862xx.h>
	25	#include <video_fb.h>
59abd15b	26	#include "upm_table.h"
3e79b588	27
5d108ac8 SP	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	extern flash_info_t flash_info[]; /* FLASH chips info */
fb661ea4	31	extern GraphicDevice mb862xx;
5d108ac8 SP	32
	33	void local_bus_init (void);
	34	ulong flash_get_size (ulong base, int banknum);
	35
	36	int checkboard (void)
	37	{
6d0f6bcf	38	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f0c0b3a9	39	char buf[64];
5e1882df	40	int f;
f0c0b3a9 WD	41	int i = getenv_f("serial#", buf, sizeof(buf));
	42	#ifdef CONFIG_PCI
	43	char *src;
	44	#endif
5d108ac8 SP	45
5d108ac8 SP	46	puts("Board: Socrates");
f0c0b3a9	47	if (i > 0) {
5d108ac8	48	puts(", serial# ");
f0c0b3a9	49	puts(buf);
5d108ac8 SP	50	}
	51	putc('\n');
	52
	53	#ifdef CONFIG_PCI
e1eb0e25 AF	54	/* Check the PCI_clk sel bit */
e1eb0e25 AF	55	if (in_be32(&gur->porpllsr) & (1<<15)) {
5e1882df SP	56	src = "SYSCLK";
	57	f = CONFIG_SYS_CLK_FREQ;
	58	} else {
	59	src = "PCI_CLK";
	60	f = CONFIG_PCI_CLK_FREQ;
	61	}
	62	printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
5d108ac8 SP	63	#else
	64	printf ("PCI1: disabled\n");
	65	#endif
	66
	67	/*
	68	* Initialize local bus.
	69	*/
	70	local_bus_init ();
5d108ac8 SP	71	return 0;
	72	}
	73
	74	int misc_init_r (void)
	75	{
5d108ac8 SP	76	/*
	77	* Adjust flash start and offset to detected values
	78	*/
	79	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	80	gd->bd->bi_flashoffset = 0;
	81
	82	/*
	83	* Check if boot FLASH isn't max size
	84	*/
6d0f6bcf	85	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	86	set_lbc_or(0, gd->bd->bi_flashstart \|
	87	(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
	88	set_lbc_br(0, gd->bd->bi_flashstart \|
	89	(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
5d108ac8 SP	90
	91	/*
	92	* Re-check to get correct base address
	93	*/
6d0f6bcf	94	flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
5d108ac8 SP	95	}
	96
	97	/*
	98	* Check if only one FLASH bank is available
	99	*/
6d0f6bcf	100	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	101	set_lbc_or(1, 0);
f51cdaf1 BB	102	set_lbc_br(1, 0);
5d108ac8 SP	103
	104	/*
	105	* Re-do flash protection upon new addresses
	106	*/
	107	flash_protect (FLAG_PROTECT_CLEAR,
	108	gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf	109	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	110
	111	/* Monitor protection ON by default */
	112	flash_protect (FLAG_PROTECT_SET,
6d0f6bcf JCPV	113	CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
6d0f6bcf JCPV	114	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	115
	116	/* Environment protection ON by default */
	117	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	118	CONFIG_ENV_ADDR,
0e8d1586 JCPV	119	CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	120	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	121
	122	/* Redundant environment protection ON by default */
	123	flash_protect (FLAG_PROTECT_SET,
0e8d1586	124	CONFIG_ENV_ADDR_REDUND,
dfcd7f21	125	CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	126	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	127	}
	128
	129	return 0;
	130	}
	131
	132	/*
	133	* Initialize Local Bus
	134	*/
	135	void local_bus_init (void)
	136	{
f51cdaf1	137	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	138	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
3e79b588 DZ	139	sys_info_t sysinfo;
	140	uint clkdiv;
	141	uint lbc_mhz;
6d0f6bcf	142	uint lcrr = CONFIG_SYS_LBC_LCRR;
3e79b588 DZ	143
3e79b588 DZ	144	get_sys_info (&sysinfo);
a5d212a2	145	clkdiv = lbc->lcrr & LCRR_CLKDIV;
997399fa	146	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
3e79b588 DZ	147
	148	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	149	if (lbc_mhz >= 66)
	150	lcrr &= ~LCRR_DBYP; /* DLL Enabled */
	151	else
	152	lcrr \|= LCRR_DBYP; /* DLL Bypass */
	153
	154	out_be32 (&lbc->lcrr, lcrr);
	155	asm ("sync;isync;msync");
5d108ac8	156
3e79b588 DZ	157	out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
	158	out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
	159	out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
	160	out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
5d108ac8	161
3e79b588 DZ	162	/* Init UPMA for FPGA access */
	163	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
	164	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
e64987a8	165
fb661ea4	166	/* Init UPMB for Lime controller access */
	167	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
	168	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
5d108ac8 SP	169	}
	170
	171	#if defined(CONFIG_PCI)
	172	/*
	173	* Initialize PCI Devices, report devices found.
	174	*/
	175
	176	#ifndef CONFIG_PCI_PNP
	177	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	178	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	179	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	180	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	181	PCI_ENET0_MEMADDR,
	182	PCI_COMMAND_MEMORY \|
	183	PCI_COMMAND_MASTER}},
	184	{}
	185	};
	186	#endif
	187
	188
	189	static struct pci_controller hose = {
	190	#ifndef CONFIG_PCI_PNP
	191	config_table:pci_mpc85xxads_config_table,
	192	#endif
	193	};
	194
	195	#endif /* CONFIG_PCI */
	196
	197
	198	void pci_init_board (void)
	199	{
	200	#ifdef CONFIG_PCI
	201	pci_mpc85xx_init (&hose);
	202	#endif /* CONFIG_PCI */
	203	}
	204
	205	#ifdef CONFIG_BOARD_EARLY_INIT_R
	206	int board_early_init_r (void)
	207	{
6d0f6bcf	208	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
3e79b588 DZ	209
	210	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	211	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	212	out_be32((unsigned int)&gur->gpiocr, 0x200 ); / enable GPOut */
	213	udelay(200);
	214	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
	215
5d108ac8 SP	216	return (0);
	217	}
	218	#endif /* CONFIG_BOARD_EARLY_INIT_R */
e18575d5 SP	219
	220	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	221	void
	222	ft_board_setup(void blob, bd_t bd)
	223	{
3e79b588 DZ	224	u32 val[12];
3e79b588 DZ	225	int rc, i = 0;
e18575d5 SP	226
	227	ft_cpu_setup(blob, bd);
	228
3e79b588 DZ	229	/* Fixup NOR FLASH mapping */
	230	val[i++] = 0; /* chip select number */
	231	val[i++] = 0; /* always 0 */
	232	val[i++] = gd->bd->bi_flashstart;
	233	val[i++] = gd->bd->bi_flashsize;
e18575d5	234
6d0f6bcf	235	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
e64987a8 AG	236	/* Fixup LIME mapping */
	237	val[i++] = 2; /* chip select number */
	238	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	239	val[i++] = CONFIG_SYS_LIME_BASE;
6d0f6bcf JCPV	240	val[i++] = CONFIG_SYS_LIME_SIZE;
e64987a8 AG	241	}
e64987a8 AG	242
3e79b588 DZ	243	/* Fixup FPGA mapping */
	244	val[i++] = 3; /* chip select number */
	245	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	246	val[i++] = CONFIG_SYS_FPGA_BASE;
6d0f6bcf JCPV	247	val[i++] = CONFIG_SYS_FPGA_SIZE;
a23cddde	248
3e79b588 DZ	249	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
3e79b588 DZ	250	val, i * sizeof(u32), 1);
a23cddde	251	if (rc)
3e79b588	252	printf("Unable to update localbus ranges, err=%s\n",
a23cddde	253	fdt_strerror(rc));
e18575d5 SP	254	}
e18575d5 SP	255	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
e64987a8	256
e64987a8 AG	257	#define DEFAULT_BRIGHTNESS 25
	258	#define BACKLIGHT_ENABLE (1 << 31)
	259
e64987a8 AG	260	static const gdc_regs init_regs [] =
	261	{
	262	{0x0100, 0x00010f00},
	263	{0x0020, 0x801901df},
	264	{0x0024, 0x00000000},
	265	{0x0028, 0x00000000},
	266	{0x002c, 0x00000000},
	267	{0x0110, 0x00000000},
	268	{0x0114, 0x00000000},
	269	{0x0118, 0x01df0320},
	270	{0x0004, 0x041f0000},
	271	{0x0008, 0x031f031f},
	272	{0x000c, 0x017f0349},
	273	{0x0010, 0x020c0000},
	274	{0x0014, 0x01df01e9},
	275	{0x0018, 0x00000000},
	276	{0x001c, 0x01e00320},
	277	{0x0100, 0x80010f00},
	278	{0x0, 0x0}
	279	};
	280
	281	const gdc_regs *board_get_regs (void)
	282	{
	283	return init_regs;
	284	}
	285
fb661ea4	286	int lime_probe(void)
fb661ea4	287	{
fb661ea4	288	uint cfg_br2;
fb661ea4	289	uint cfg_or2;
c28d3bbe	290	int type;
fb661ea4	291
f51cdaf1 BB	292	cfg_br2 = get_lbc_br(2);
f51cdaf1 BB	293	cfg_or2 = get_lbc_or(2);
fb661ea4	294
fb661ea4	295	/* Configure GPCM for CS2 */
f51cdaf1 BB	296	set_lbc_br(2, 0);
	297	set_lbc_or(2, 0xfc000410);
	298	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) \| 0x00001901);
fb661ea4	299
c28d3bbe WG	300	/* Get controller type */
c28d3bbe WG	301	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
fb661ea4	302
fb661ea4	303	/* Restore previous CS2 configuration */
f51cdaf1 BB	304	set_lbc_br(2, 0);
	305	set_lbc_or(2, cfg_or2);
	306	set_lbc_br(2, cfg_br2);
c28d3bbe WG	307
c28d3bbe WG	308	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
fb661ea4	309	}
fb661ea4	310
e64987a8 AG	311	/* Returns Lime base address */
	312	unsigned int board_video_init (void)
	313	{
fb661ea4	314	if (!lime_probe())
e64987a8 AG	315	return 0;
e64987a8 AG	316
c28d3bbe WG	317	mb862xx.winSizeX = 800;
c28d3bbe WG	318	mb862xx.winSizeY = 480;
e64987a8 AG	319	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	320	mb862xx.gdfBytesPP = 2;
	321
6d0f6bcf	322	return CONFIG_SYS_LIME_BASE;
e64987a8 AG	323	}
	324
	325	#define W83782D_REG_CFG 0x40
	326	#define W83782D_REG_BANK_SEL 0x4e
	327	#define W83782D_REG_ADCCLK 0x4b
	328	#define W83782D_REG_BEEP_CTRL 0x4d
	329	#define W83782D_REG_BEEP_CTRL2 0x57
	330	#define W83782D_REG_PWMOUT1 0x5b
	331	#define W83782D_REG_VBAT 0x5d
	332
	333	static int w83782d_hwmon_init(void)
	334	{
	335	u8 buf;
	336
6d0f6bcf	337	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
e64987a8 AG	338	return -1;
e64987a8 AG	339
6d0f6bcf JCPV	340	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
	341	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
	342	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
e64987a8	343
6d0f6bcf JCPV	344	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
6d0f6bcf JCPV	345	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
e64987a8	346	buf \| 0x80);
6d0f6bcf JCPV	347	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
	348	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
	349	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
e64987a8	350
6d0f6bcf JCPV	351	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
6d0f6bcf JCPV	352	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
e64987a8 AG	353	(buf & 0xf4) \| 0x01);
	354	return 0;
	355	}
	356
	357	static void board_backlight_brightness(int br)
	358	{
	359	u32 reg;
	360	u8 buf;
	361	u8 old_buf;
	362
	363	/* Select bank 0 */
6d0f6bcf	364	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
e64987a8 AG	365	goto err;
	366	else
	367	buf = old_buf & 0xf8;
	368
6d0f6bcf	369	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
e64987a8 AG	370	goto err;
	371
	372	if (br > 0) {
	373	/* PWMOUT1 duty cycle ctrl */
	374	buf = 255 / (100 / br);
6d0f6bcf	375	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
e64987a8 AG	376	goto err;
	377
	378	/* LEDs on */
6d0f6bcf	379	reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
e64987a8	380	if (!(reg & BACKLIGHT_ENABLE));
6d0f6bcf	381	out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
e64987a8 AG	382	reg \| BACKLIGHT_ENABLE);
	383	} else {
	384	buf = 0;
6d0f6bcf	385	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
e64987a8 AG	386	goto err;
	387
	388	/* LEDs off */
6d0f6bcf	389	reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
e64987a8	390	reg &= ~BACKLIGHT_ENABLE;
6d0f6bcf	391	out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
e64987a8 AG	392	}
e64987a8 AG	393	/* Restore previous bank setting */
6d0f6bcf	394	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
e64987a8 AG	395	goto err;
	396
	397	return;
	398	err:
	399	printf("W83782G I2C access failed\n");
	400	}
	401
	402	void board_backlight_switch (int flag)
	403	{
	404	char * param;
	405	int rc;
	406
	407	if (w83782d_hwmon_init())
	408	printf ("hwmon IC init failed\n");
	409
	410	if (flag) {
	411	param = getenv("brightness");
	412	rc = param ? simple_strtol(param, NULL, 10) : -1;
	413	if (rc < 0)
	414	rc = DEFAULT_BRIGHTNESS;
	415	} else {
	416	rc = 0;
	417	}
	418	board_backlight_brightness(rc);
	419	}
	420
	421	#if defined(CONFIG_CONSOLE_EXTRA_INFO)
	422	/*
	423	* Return text to be printed besides the logo.
	424	*/
	425	void video_get_info_str (int line_number, char *info)
	426	{
	427	if (line_number == 1) {
	428	strcpy (info, " Board: Socrates");
	429	} else {
	430	info [0] = '\0';
	431	}
	432	}
	433	#endif