[thirdparty/u-boot.git] / board / socrates / socrates.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 */

#include <common.h>
#include <clock_legacy.h>
#include <env.h>
#include <pci.h>
#include <uuid.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <i2c.h>
#include <mb862xx.h>
#include <video_fb.h>
#include "upm_table.h"

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */
extern GraphicDevice mb862xx;

void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	char buf[64];
	int f;
	int i = env_get_f("serial#", buf, sizeof(buf));
#ifdef CONFIG_PCI
	char *src;
#endif

	puts("Board: Socrates");
	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
	/* Check the PCI_clk sel bit */
	if (in_be32(&gur->porpllsr) & (1<<15)) {
		src = "SYSCLK";
		f = CONFIG_SYS_CLK_FREQ;
	} else {
		src = "PCI_CLK";
		f = CONFIG_PCI_CLK_FREQ;
	}
	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
#else
	printf ("PCI1:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();
	return 0;
}

int misc_init_r (void)
{
	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
		set_lbc_br(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
	}

	/*
	 * Check if only one FLASH bank is available
	 */
	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(1, 0);
		set_lbc_br(1, 0);

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect(FLAG_PROTECT_CLEAR,
			      gd->bd->bi_flashstart, 0xffffffff,
			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect(FLAG_PROTECT_SET,
			      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
			      monitor_flash_len - 1,
			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect(FLAG_PROTECT_SET,
			      CONFIG_ENV_ADDR,
			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect(FLAG_PROTECT_SET,
			      CONFIG_ENV_ADDR_REDUND,
			      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
	}

#if defined(CONFIG_DM_PCI)
	pci_init();
#endif

	return 0;
}

/*
 * Initialize Local Bus
 */
void local_bus_init (void)
{
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	sys_info_t sysinfo;
	uint clkdiv;
	uint lbc_mhz;
	uint lcrr = CONFIG_SYS_LBC_LCRR;

	get_sys_info (&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;

	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	if (lbc_mhz >= 66)
		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32 (&lbc->lcrr, lcrr);
	asm ("sync;isync;msync");

	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */

	/* Init UPMA for FPGA access */
	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));

	/* Init UPMB for Lime controller access */
	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
	upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
}

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
	udelay(200);
	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );

	return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	u32 val[12];
	int rc, i = 0;

	ft_cpu_setup(blob, bd);

	/* Fixup NOR FLASH mapping */
	val[i++] = 0;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = gd->bd->bi_flashstart;
	val[i++] = gd->bd->bi_flashsize;

#if defined(CONFIG_VIDEO_MB862xx)
	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
		/* Fixup LIME mapping */
		val[i++] = 2;			/* chip select number */
		val[i++] = 0;			/* always 0 */
		val[i++] = CONFIG_SYS_LIME_BASE;
		val[i++] = CONFIG_SYS_LIME_SIZE;
	}
#endif

	/* Fixup FPGA mapping */
	val[i++] = 3;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = CONFIG_SYS_FPGA_BASE;
	val[i++] = CONFIG_SYS_FPGA_SIZE;

	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
				  val, i * sizeof(u32), 1);
	if (rc)
		printf("Unable to update localbus ranges, err=%s\n",
		       fdt_strerror(rc));

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

#if defined(CONFIG_OF_SEPARATE)
void *board_fdt_blob_setup(void)
{
	void *fw_dtb;

	fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
		printf("DTB is not passed via %x\n", (u32)fw_dtb);
		return NULL;
	}

	return fw_dtb;
}
#endif

int get_serial_clock(void)
{
	return 333333330;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	2	/*
	3	* (C) Copyright 2008
	4	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	5	*
	6	* Copyright 2004 Freescale Semiconductor.
	7	* (C) Copyright 2002,2003, Motorola Inc.
	8	* Xianghua Xiao, (X.Xiao@motorola.com)
	9	*
	10	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5d108ac8 SP	11	*/
	12
	13	#include <common.h>
d96c2604	14	#include <clock_legacy.h>
3a7d5571	15	#include <env.h>
5d108ac8	16	#include <pci.h>
b79fdc76	17	#include <uuid.h>
5d108ac8 SP	18	#include <asm/processor.h>
	19	#include <asm/immap_85xx.h>
	20	#include <ioports.h>
	21	#include <flash.h>
b08c8c48	22	#include <linux/libfdt.h>
e18575d5	23	#include <fdt_support.h>
e1eb0e25	24	#include <asm/io.h>
fb661ea4	25	#include <i2c.h>
	26	#include <mb862xx.h>
	27	#include <video_fb.h>
59abd15b	28	#include "upm_table.h"
3e79b588	29
5d108ac8 SP	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	extern flash_info_t flash_info[]; /* FLASH chips info */
fb661ea4	33	extern GraphicDevice mb862xx;
5d108ac8 SP	34
	35	void local_bus_init (void);
	36	ulong flash_get_size (ulong base, int banknum);
	37
	38	int checkboard (void)
	39	{
6d0f6bcf	40	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f0c0b3a9	41	char buf[64];
5e1882df	42	int f;
00caae6d	43	int i = env_get_f("serial#", buf, sizeof(buf));
f0c0b3a9 WD	44	#ifdef CONFIG_PCI
	45	char *src;
	46	#endif
5d108ac8 SP	47
5d108ac8 SP	48	puts("Board: Socrates");
f0c0b3a9	49	if (i > 0) {
5d108ac8	50	puts(", serial# ");
f0c0b3a9	51	puts(buf);
5d108ac8 SP	52	}
	53	putc('\n');
	54
2a51fe01	55	#if defined(CONFIG_PCI) \|\| defined(CONFIG_DM_PCI)
e1eb0e25 AF	56	/* Check the PCI_clk sel bit */
e1eb0e25 AF	57	if (in_be32(&gur->porpllsr) & (1<<15)) {
5e1882df SP	58	src = "SYSCLK";
	59	f = CONFIG_SYS_CLK_FREQ;
	60	} else {
	61	src = "PCI_CLK";
	62	f = CONFIG_PCI_CLK_FREQ;
	63	}
	64	printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
5d108ac8 SP	65	#else
	66	printf ("PCI1: disabled\n");
	67	#endif
	68
	69	/*
	70	* Initialize local bus.
	71	*/
	72	local_bus_init ();
5d108ac8 SP	73	return 0;
	74	}
	75
	76	int misc_init_r (void)
	77	{
5d108ac8 SP	78	/*
	79	* Adjust flash start and offset to detected values
	80	*/
	81	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	82	gd->bd->bi_flashoffset = 0;
	83
	84	/*
	85	* Check if boot FLASH isn't max size
	86	*/
6d0f6bcf	87	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	88	set_lbc_or(0, gd->bd->bi_flashstart \|
	89	(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
	90	set_lbc_br(0, gd->bd->bi_flashstart \|
	91	(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
5d108ac8 SP	92
	93	/*
	94	* Re-check to get correct base address
	95	*/
6d0f6bcf	96	flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
5d108ac8 SP	97	}
	98
	99	/*
	100	* Check if only one FLASH bank is available
	101	*/
6d0f6bcf	102	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	103	set_lbc_or(1, 0);
f51cdaf1 BB	104	set_lbc_br(1, 0);
5d108ac8 SP	105
	106	/*
	107	* Re-do flash protection upon new addresses
	108	*/
a595a0e9 SG	109	flash_protect(FLAG_PROTECT_CLEAR,
	110	gd->bd->bi_flashstart, 0xffffffff,
	111	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	112
5d108ac8 SP	113	/* Monitor protection ON by default */
a595a0e9 SG	114	flash_protect(FLAG_PROTECT_SET,
	115	CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
	116	monitor_flash_len - 1,
	117	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	118
5d108ac8 SP	119	/* Environment protection ON by default */
a595a0e9 SG	120	flash_protect(FLAG_PROTECT_SET,
	121	CONFIG_ENV_ADDR,
	122	CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
	123	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	124
5d108ac8 SP	125	/* Redundant environment protection ON by default */
a595a0e9 SG	126	flash_protect(FLAG_PROTECT_SET,
	127	CONFIG_ENV_ADDR_REDUND,
	128	CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	129	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	130	}
5d108ac8 SP	131
2a51fe01 HS	132	#if defined(CONFIG_DM_PCI)
	133	pci_init();
	134	#endif
	135
5d108ac8 SP	136	return 0;
	137	}
	138
	139	/*
	140	* Initialize Local Bus
	141	*/
	142	void local_bus_init (void)
	143	{
f51cdaf1	144	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	145	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
3e79b588 DZ	146	sys_info_t sysinfo;
	147	uint clkdiv;
	148	uint lbc_mhz;
6d0f6bcf	149	uint lcrr = CONFIG_SYS_LBC_LCRR;
3e79b588 DZ	150
3e79b588 DZ	151	get_sys_info (&sysinfo);
a5d212a2	152	clkdiv = lbc->lcrr & LCRR_CLKDIV;
997399fa	153	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
3e79b588 DZ	154
	155	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	156	if (lbc_mhz >= 66)
	157	lcrr &= ~LCRR_DBYP; /* DLL Enabled */
	158	else
	159	lcrr \|= LCRR_DBYP; /* DLL Bypass */
	160
	161	out_be32 (&lbc->lcrr, lcrr);
	162	asm ("sync;isync;msync");
5d108ac8	163
3e79b588 DZ	164	out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
	165	out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
	166	out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
	167	out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
5d108ac8	168
3e79b588 DZ	169	/* Init UPMA for FPGA access */
3e79b588 DZ	170	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
6d1fdb1e	171	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
e64987a8	172
fb661ea4	173	/* Init UPMB for Lime controller access */
fb661ea4	174	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
6d1fdb1e	175	upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
5d108ac8 SP	176	}
5d108ac8 SP	177
5d108ac8 SP	178	#ifdef CONFIG_BOARD_EARLY_INIT_R
	179	int board_early_init_r (void)
	180	{
6d0f6bcf	181	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
3e79b588 DZ	182
	183	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	184	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	185	out_be32((unsigned int)&gur->gpiocr, 0x200 ); / enable GPOut */
	186	udelay(200);
	187	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
	188
5d108ac8 SP	189	return (0);
	190	}
	191	#endif /* CONFIG_BOARD_EARLY_INIT_R */
e18575d5	192
7ffe3cd6	193	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	194	int ft_board_setup(void blob, bd_t bd)
e18575d5	195	{
3e79b588 DZ	196	u32 val[12];
3e79b588 DZ	197	int rc, i = 0;
e18575d5 SP	198
	199	ft_cpu_setup(blob, bd);
	200
3e79b588 DZ	201	/* Fixup NOR FLASH mapping */
	202	val[i++] = 0; /* chip select number */
	203	val[i++] = 0; /* always 0 */
	204	val[i++] = gd->bd->bi_flashstart;
	205	val[i++] = gd->bd->bi_flashsize;
e18575d5	206
4c65a449	207	#if defined(CONFIG_VIDEO_MB862xx)
6d0f6bcf	208	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
e64987a8 AG	209	/* Fixup LIME mapping */
	210	val[i++] = 2; /* chip select number */
	211	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	212	val[i++] = CONFIG_SYS_LIME_BASE;
6d0f6bcf JCPV	213	val[i++] = CONFIG_SYS_LIME_SIZE;
e64987a8	214	}
4c65a449	215	#endif
e64987a8	216
3e79b588 DZ	217	/* Fixup FPGA mapping */
	218	val[i++] = 3; /* chip select number */
	219	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	220	val[i++] = CONFIG_SYS_FPGA_BASE;
6d0f6bcf JCPV	221	val[i++] = CONFIG_SYS_FPGA_SIZE;
a23cddde	222
3e79b588 DZ	223	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
3e79b588 DZ	224	val, i * sizeof(u32), 1);
a23cddde	225	if (rc)
3e79b588	226	printf("Unable to update localbus ranges, err=%s\n",
a23cddde	227	fdt_strerror(rc));
e895a4b0 SG	228
e895a4b0 SG	229	return 0;
e18575d5	230	}
7ffe3cd6	231	#endif /* CONFIG_OF_BOARD_SETUP */
e64987a8	232
39642abf HS	233	#if defined(CONFIG_OF_SEPARATE)
	234	void *board_fdt_blob_setup(void)
	235	{
	236	void *fw_dtb;
	237
	238	fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
	239	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
	240	printf("DTB is not passed via %x\n", (u32)fw_dtb);
	241	return NULL;
	242	}
	243
	244	return fw_dtb;
	245	}
	246	#endif
98beb60a HS	247
	248	int get_serial_clock(void)
	249	{
	250	return 333333330;
	251	}