[people/ms/u-boot.git] / board / socrates / socrates.c

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <i2c.h>
#include <mb862xx.h>
#include <video_fb.h>
#include "upm_table.h"

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */
extern GraphicDevice mb862xx;

void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	char buf[64];
	int f;
	int i = getenv_f("serial#", buf, sizeof(buf));
#ifdef CONFIG_PCI
	char *src;
#endif

	puts("Board: Socrates");
	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

#ifdef CONFIG_PCI
	/* Check the PCI_clk sel bit */
	if (in_be32(&gur->porpllsr) & (1<<15)) {
		src = "SYSCLK";
		f = CONFIG_SYS_CLK_FREQ;
	} else {
		src = "PCI_CLK";
		f = CONFIG_PCI_CLK_FREQ;
	}
	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
#else
	printf ("PCI1:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();
	return 0;
}

int misc_init_r (void)
{
	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
		set_lbc_br(0, gd->bd->bi_flashstart |
			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
	}

	/*
	 * Check if only one FLASH bank is available
	 */
	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
		set_lbc_or(1, 0);
		set_lbc_br(1, 0);

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect (FLAG_PROTECT_CLEAR,
			       gd->bd->bi_flashstart, 0xffffffff,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR,
			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR_REDUND,
			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
	}

	return 0;
}

/*
 * Initialize Local Bus
 */
void local_bus_init (void)
{
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	sys_info_t sysinfo;
	uint clkdiv;
	uint lbc_mhz;
	uint lcrr = CONFIG_SYS_LBC_LCRR;

	get_sys_info (&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	if (lbc_mhz >= 66)
		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32 (&lbc->lcrr, lcrr);
	asm ("sync;isync;msync");

	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */

	/* Init UPMA for FPGA access */
	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));

	/* Init UPMB for Lime controller access */
	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY |
				     PCI_COMMAND_MASTER}},
	{}
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc85xxads_config_table,
#endif
};

#endif /* CONFIG_PCI */


void pci_init_board (void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
	udelay(200);
	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );

	return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	u32 val[12];
	int rc, i = 0;

	ft_cpu_setup(blob, bd);

	/* Fixup NOR FLASH mapping */
	val[i++] = 0;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = gd->bd->bi_flashstart;
	val[i++] = gd->bd->bi_flashsize;

	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
		/* Fixup LIME mapping */
		val[i++] = 2;			/* chip select number */
		val[i++] = 0;			/* always 0 */
		val[i++] = CONFIG_SYS_LIME_BASE;
		val[i++] = CONFIG_SYS_LIME_SIZE;
	}

	/* Fixup FPGA mapping */
	val[i++] = 3;				/* chip select number */
	val[i++] = 0;				/* always 0 */
	val[i++] = CONFIG_SYS_FPGA_BASE;
	val[i++] = CONFIG_SYS_FPGA_SIZE;

	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
				  val, i * sizeof(u32), 1);
	if (rc)
		printf("Unable to update localbus ranges, err=%s\n",
		       fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

#define DEFAULT_BRIGHTNESS	25
#define BACKLIGHT_ENABLE	(1 << 31)

static const gdc_regs init_regs [] =
{
	{0x0100, 0x00010f00},
	{0x0020, 0x801901df},
	{0x0024, 0x00000000},
	{0x0028, 0x00000000},
	{0x002c, 0x00000000},
	{0x0110, 0x00000000},
	{0x0114, 0x00000000},
	{0x0118, 0x01df0320},
	{0x0004, 0x041f0000},
	{0x0008, 0x031f031f},
	{0x000c, 0x017f0349},
	{0x0010, 0x020c0000},
	{0x0014, 0x01df01e9},
	{0x0018, 0x00000000},
	{0x001c, 0x01e00320},
	{0x0100, 0x80010f00},
	{0x0, 0x0}
};

const gdc_regs *board_get_regs (void)
{
	return init_regs;
}

int lime_probe(void)
{
	uint cfg_br2;
	uint cfg_or2;
	int type;

	cfg_br2 = get_lbc_br(2);
	cfg_or2 = get_lbc_or(2);

	/* Configure GPCM for CS2 */
	set_lbc_br(2, 0);
	set_lbc_or(2, 0xfc000410);
	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);

	/* Get controller type */
	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);

	/* Restore previous CS2 configuration */
	set_lbc_br(2, 0);
	set_lbc_or(2, cfg_or2);
	set_lbc_br(2, cfg_br2);

	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}

/* Returns Lime base address */
unsigned int board_video_init (void)
{
	if (!lime_probe())
		return 0;

	mb862xx.winSizeX = 800;
	mb862xx.winSizeY = 480;
	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	mb862xx.gdfBytesPP = 2;

	return CONFIG_SYS_LIME_BASE;
}

#define W83782D_REG_CFG		0x40
#define W83782D_REG_BANK_SEL	0x4e
#define W83782D_REG_ADCCLK	0x4b
#define W83782D_REG_BEEP_CTRL	0x4d
#define W83782D_REG_BEEP_CTRL2	0x57
#define W83782D_REG_PWMOUT1	0x5b
#define W83782D_REG_VBAT	0x5d

static int w83782d_hwmon_init(void)
{
	u8 buf;

	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
		return -1;

	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);

	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
		      buf | 0x80);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);

	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
		      (buf & 0xf4) | 0x01);
	return 0;
}

static void board_backlight_brightness(int br)
{
	u32 reg;
	u8 buf;
	u8 old_buf;

	/* Select bank 0 */
	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
		goto err;
	else
		buf = old_buf & 0xf8;

	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
		goto err;

	if (br > 0) {
		/* PWMOUT1 duty cycle ctrl */
		buf = 255 / (100 / br);
		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
			goto err;

		/* LEDs on */
		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
		if (!(reg & BACKLIGHT_ENABLE));
			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
				 reg | BACKLIGHT_ENABLE);
	} else {
		buf = 0;
		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
			goto err;

		/* LEDs off */
		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
		reg &= ~BACKLIGHT_ENABLE;
		out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
	}
	/* Restore previous bank setting */
	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
		goto err;

	return;
err:
	printf("W83782G I2C access failed\n");
}

void board_backlight_switch (int flag)
{
	char * param;
	int rc;

	if (w83782d_hwmon_init())
		printf ("hwmon IC init failed\n");

	if (flag) {
		param = getenv("brightness");
		rc = param ? simple_strtol(param, NULL, 10) : -1;
		if (rc < 0)
			rc = DEFAULT_BRIGHTNESS;
	} else {
		rc = 0;
	}
	board_backlight_brightness(rc);
}

#if defined(CONFIG_CONSOLE_EXTRA_INFO)
/*
 * Return text to be printed besides the logo.
 */
void video_get_info_str (int line_number, char *info)
{
	if (line_number == 1) {
		strcpy (info, " Board: Socrates");
	} else {
		info [0] = '\0';
	}
}
#endif
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Copyright 2004 Freescale Semiconductor.
	6	* (C) Copyright 2002,2003, Motorola Inc.
	7	* Xianghua Xiao, (X.Xiao@motorola.com)
	8	*
	9	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <common.h>
	31	#include <pci.h>
	32	#include <asm/processor.h>
	33	#include <asm/immap_85xx.h>
	34	#include <ioports.h>
	35	#include <flash.h>
e18575d5 SP	36	#include <libfdt.h>
e18575d5 SP	37	#include <fdt_support.h>
e1eb0e25	38	#include <asm/io.h>
fb661ea4	39	#include <i2c.h>
	40	#include <mb862xx.h>
	41	#include <video_fb.h>
59abd15b	42	#include "upm_table.h"
3e79b588	43
5d108ac8 SP	44	DECLARE_GLOBAL_DATA_PTR;
	45
	46	extern flash_info_t flash_info[]; /* FLASH chips info */
fb661ea4	47	extern GraphicDevice mb862xx;
5d108ac8 SP	48
	49	void local_bus_init (void);
	50	ulong flash_get_size (ulong base, int banknum);
	51
	52	int checkboard (void)
	53	{
6d0f6bcf	54	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f0c0b3a9	55	char buf[64];
5e1882df	56	int f;
f0c0b3a9 WD	57	int i = getenv_f("serial#", buf, sizeof(buf));
	58	#ifdef CONFIG_PCI
	59	char *src;
	60	#endif
5d108ac8 SP	61
5d108ac8 SP	62	puts("Board: Socrates");
f0c0b3a9	63	if (i > 0) {
5d108ac8	64	puts(", serial# ");
f0c0b3a9	65	puts(buf);
5d108ac8 SP	66	}
	67	putc('\n');
	68
	69	#ifdef CONFIG_PCI
e1eb0e25 AF	70	/* Check the PCI_clk sel bit */
e1eb0e25 AF	71	if (in_be32(&gur->porpllsr) & (1<<15)) {
5e1882df SP	72	src = "SYSCLK";
	73	f = CONFIG_SYS_CLK_FREQ;
	74	} else {
	75	src = "PCI_CLK";
	76	f = CONFIG_PCI_CLK_FREQ;
	77	}
	78	printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
5d108ac8 SP	79	#else
	80	printf ("PCI1: disabled\n");
	81	#endif
	82
	83	/*
	84	* Initialize local bus.
	85	*/
	86	local_bus_init ();
5d108ac8 SP	87	return 0;
	88	}
	89
	90	int misc_init_r (void)
	91	{
5d108ac8 SP	92	/*
	93	* Adjust flash start and offset to detected values
	94	*/
	95	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	96	gd->bd->bi_flashoffset = 0;
	97
	98	/*
	99	* Check if boot FLASH isn't max size
	100	*/
6d0f6bcf	101	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	102	set_lbc_or(0, gd->bd->bi_flashstart \|
	103	(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
	104	set_lbc_br(0, gd->bd->bi_flashstart \|
	105	(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
5d108ac8 SP	106
	107	/*
	108	* Re-check to get correct base address
	109	*/
6d0f6bcf	110	flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
5d108ac8 SP	111	}
	112
	113	/*
	114	* Check if only one FLASH bank is available
	115	*/
6d0f6bcf	116	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
f51cdaf1 BB	117	set_lbc_or(1, 0);
f51cdaf1 BB	118	set_lbc_br(1, 0);
5d108ac8 SP	119
	120	/*
	121	* Re-do flash protection upon new addresses
	122	*/
	123	flash_protect (FLAG_PROTECT_CLEAR,
	124	gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf	125	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	126
	127	/* Monitor protection ON by default */
	128	flash_protect (FLAG_PROTECT_SET,
6d0f6bcf JCPV	129	CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
6d0f6bcf JCPV	130	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	131
	132	/* Environment protection ON by default */
	133	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	134	CONFIG_ENV_ADDR,
0e8d1586 JCPV	135	CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	136	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	137
	138	/* Redundant environment protection ON by default */
	139	flash_protect (FLAG_PROTECT_SET,
0e8d1586	140	CONFIG_ENV_ADDR_REDUND,
dfcd7f21	141	CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	142	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
5d108ac8 SP	143	}
	144
	145	return 0;
	146	}
	147
	148	/*
	149	* Initialize Local Bus
	150	*/
	151	void local_bus_init (void)
	152	{
f51cdaf1	153	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	154	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
3e79b588 DZ	155	sys_info_t sysinfo;
	156	uint clkdiv;
	157	uint lbc_mhz;
6d0f6bcf	158	uint lcrr = CONFIG_SYS_LBC_LCRR;
3e79b588 DZ	159
3e79b588 DZ	160	get_sys_info (&sysinfo);
a5d212a2	161	clkdiv = lbc->lcrr & LCRR_CLKDIV;
3e79b588 DZ	162	lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	163
	164	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
	165	if (lbc_mhz >= 66)
	166	lcrr &= ~LCRR_DBYP; /* DLL Enabled */
	167	else
	168	lcrr \|= LCRR_DBYP; /* DLL Bypass */
	169
	170	out_be32 (&lbc->lcrr, lcrr);
	171	asm ("sync;isync;msync");
5d108ac8	172
3e79b588 DZ	173	out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
	174	out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
	175	out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
	176	out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
5d108ac8	177
3e79b588 DZ	178	/* Init UPMA for FPGA access */
	179	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
	180	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
e64987a8	181
fb661ea4	182	/* Init UPMB for Lime controller access */
	183	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
	184	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
5d108ac8 SP	185	}
	186
	187	#if defined(CONFIG_PCI)
	188	/*
	189	* Initialize PCI Devices, report devices found.
	190	*/
	191
	192	#ifndef CONFIG_PCI_PNP
	193	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	194	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	195	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	196	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	197	PCI_ENET0_MEMADDR,
	198	PCI_COMMAND_MEMORY \|
	199	PCI_COMMAND_MASTER}},
	200	{}
	201	};
	202	#endif
	203
	204
	205	static struct pci_controller hose = {
	206	#ifndef CONFIG_PCI_PNP
	207	config_table:pci_mpc85xxads_config_table,
	208	#endif
	209	};
	210
	211	#endif /* CONFIG_PCI */
	212
	213
	214	void pci_init_board (void)
	215	{
	216	#ifdef CONFIG_PCI
	217	pci_mpc85xx_init (&hose);
	218	#endif /* CONFIG_PCI */
	219	}
	220
	221	#ifdef CONFIG_BOARD_EARLY_INIT_R
	222	int board_early_init_r (void)
	223	{
6d0f6bcf	224	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
3e79b588 DZ	225
	226	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
	227	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
	228	out_be32((unsigned int)&gur->gpiocr, 0x200 ); / enable GPOut */
	229	udelay(200);
	230	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
	231
5d108ac8 SP	232	return (0);
	233	}
	234	#endif /* CONFIG_BOARD_EARLY_INIT_R */
e18575d5 SP	235
	236	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	237	void
	238	ft_board_setup(void blob, bd_t bd)
	239	{
3e79b588 DZ	240	u32 val[12];
3e79b588 DZ	241	int rc, i = 0;
e18575d5 SP	242
	243	ft_cpu_setup(blob, bd);
	244
3e79b588 DZ	245	/* Fixup NOR FLASH mapping */
	246	val[i++] = 0; /* chip select number */
	247	val[i++] = 0; /* always 0 */
	248	val[i++] = gd->bd->bi_flashstart;
	249	val[i++] = gd->bd->bi_flashsize;
e18575d5	250
6d0f6bcf	251	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
e64987a8 AG	252	/* Fixup LIME mapping */
	253	val[i++] = 2; /* chip select number */
	254	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	255	val[i++] = CONFIG_SYS_LIME_BASE;
6d0f6bcf JCPV	256	val[i++] = CONFIG_SYS_LIME_SIZE;
e64987a8 AG	257	}
e64987a8 AG	258
3e79b588 DZ	259	/* Fixup FPGA mapping */
	260	val[i++] = 3; /* chip select number */
	261	val[i++] = 0; /* always 0 */
6d0f6bcf JCPV	262	val[i++] = CONFIG_SYS_FPGA_BASE;
6d0f6bcf JCPV	263	val[i++] = CONFIG_SYS_FPGA_SIZE;
a23cddde	264
3e79b588 DZ	265	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
3e79b588 DZ	266	val, i * sizeof(u32), 1);
a23cddde	267	if (rc)
3e79b588	268	printf("Unable to update localbus ranges, err=%s\n",
a23cddde	269	fdt_strerror(rc));
e18575d5 SP	270	}
e18575d5 SP	271	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
e64987a8	272
e64987a8 AG	273	#define DEFAULT_BRIGHTNESS 25
	274	#define BACKLIGHT_ENABLE (1 << 31)
	275
e64987a8 AG	276	static const gdc_regs init_regs [] =
	277	{
	278	{0x0100, 0x00010f00},
	279	{0x0020, 0x801901df},
	280	{0x0024, 0x00000000},
	281	{0x0028, 0x00000000},
	282	{0x002c, 0x00000000},
	283	{0x0110, 0x00000000},
	284	{0x0114, 0x00000000},
	285	{0x0118, 0x01df0320},
	286	{0x0004, 0x041f0000},
	287	{0x0008, 0x031f031f},
	288	{0x000c, 0x017f0349},
	289	{0x0010, 0x020c0000},
	290	{0x0014, 0x01df01e9},
	291	{0x0018, 0x00000000},
	292	{0x001c, 0x01e00320},
	293	{0x0100, 0x80010f00},
	294	{0x0, 0x0}
	295	};
	296
	297	const gdc_regs *board_get_regs (void)
	298	{
	299	return init_regs;
	300	}
	301
fb661ea4	302	int lime_probe(void)
fb661ea4	303	{
fb661ea4	304	uint cfg_br2;
fb661ea4	305	uint cfg_or2;
c28d3bbe	306	int type;
fb661ea4	307
f51cdaf1 BB	308	cfg_br2 = get_lbc_br(2);
f51cdaf1 BB	309	cfg_or2 = get_lbc_or(2);
fb661ea4	310
fb661ea4	311	/* Configure GPCM for CS2 */
f51cdaf1 BB	312	set_lbc_br(2, 0);
	313	set_lbc_or(2, 0xfc000410);
	314	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) \| 0x00001901);
fb661ea4	315
c28d3bbe WG	316	/* Get controller type */
c28d3bbe WG	317	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
fb661ea4	318
fb661ea4	319	/* Restore previous CS2 configuration */
f51cdaf1 BB	320	set_lbc_br(2, 0);
	321	set_lbc_or(2, cfg_or2);
	322	set_lbc_br(2, cfg_br2);
c28d3bbe WG	323
c28d3bbe WG	324	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
fb661ea4	325	}
fb661ea4	326
e64987a8 AG	327	/* Returns Lime base address */
	328	unsigned int board_video_init (void)
	329	{
fb661ea4	330	if (!lime_probe())
e64987a8 AG	331	return 0;
e64987a8 AG	332
c28d3bbe WG	333	mb862xx.winSizeX = 800;
c28d3bbe WG	334	mb862xx.winSizeY = 480;
e64987a8 AG	335	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	336	mb862xx.gdfBytesPP = 2;
	337
6d0f6bcf	338	return CONFIG_SYS_LIME_BASE;
e64987a8 AG	339	}
	340
	341	#define W83782D_REG_CFG 0x40
	342	#define W83782D_REG_BANK_SEL 0x4e
	343	#define W83782D_REG_ADCCLK 0x4b
	344	#define W83782D_REG_BEEP_CTRL 0x4d
	345	#define W83782D_REG_BEEP_CTRL2 0x57
	346	#define W83782D_REG_PWMOUT1 0x5b
	347	#define W83782D_REG_VBAT 0x5d
	348
	349	static int w83782d_hwmon_init(void)
	350	{
	351	u8 buf;
	352
6d0f6bcf	353	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
e64987a8 AG	354	return -1;
e64987a8 AG	355
6d0f6bcf JCPV	356	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
	357	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
	358	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
e64987a8	359
6d0f6bcf JCPV	360	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
6d0f6bcf JCPV	361	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
e64987a8	362	buf \| 0x80);
6d0f6bcf JCPV	363	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
	364	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
	365	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
e64987a8	366
6d0f6bcf JCPV	367	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
6d0f6bcf JCPV	368	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
e64987a8 AG	369	(buf & 0xf4) \| 0x01);
	370	return 0;
	371	}
	372
	373	static void board_backlight_brightness(int br)
	374	{
	375	u32 reg;
	376	u8 buf;
	377	u8 old_buf;
	378
	379	/* Select bank 0 */
6d0f6bcf	380	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
e64987a8 AG	381	goto err;
	382	else
	383	buf = old_buf & 0xf8;
	384
6d0f6bcf	385	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
e64987a8 AG	386	goto err;
	387
	388	if (br > 0) {
	389	/* PWMOUT1 duty cycle ctrl */
	390	buf = 255 / (100 / br);
6d0f6bcf	391	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
e64987a8 AG	392	goto err;
	393
	394	/* LEDs on */
6d0f6bcf	395	reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
e64987a8	396	if (!(reg & BACKLIGHT_ENABLE));
6d0f6bcf	397	out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
e64987a8 AG	398	reg \| BACKLIGHT_ENABLE);
	399	} else {
	400	buf = 0;
6d0f6bcf	401	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
e64987a8 AG	402	goto err;
	403
	404	/* LEDs off */
6d0f6bcf	405	reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
e64987a8	406	reg &= ~BACKLIGHT_ENABLE;
6d0f6bcf	407	out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
e64987a8 AG	408	}
e64987a8 AG	409	/* Restore previous bank setting */
6d0f6bcf	410	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
e64987a8 AG	411	goto err;
	412
	413	return;
	414	err:
	415	printf("W83782G I2C access failed\n");
	416	}
	417
	418	void board_backlight_switch (int flag)
	419	{
	420	char * param;
	421	int rc;
	422
	423	if (w83782d_hwmon_init())
	424	printf ("hwmon IC init failed\n");
	425
	426	if (flag) {
	427	param = getenv("brightness");
	428	rc = param ? simple_strtol(param, NULL, 10) : -1;
	429	if (rc < 0)
	430	rc = DEFAULT_BRIGHTNESS;
	431	} else {
	432	rc = 0;
	433	}
	434	board_backlight_brightness(rc);
	435	}
	436
	437	#if defined(CONFIG_CONSOLE_EXTRA_INFO)
	438	/*
	439	* Return text to be printed besides the logo.
	440	*/
	441	void video_get_info_str (int line_number, char *info)
	442	{
	443	if (line_number == 1) {
	444	strcpy (info, " Board: Socrates");
	445	} else {
	446	info [0] = '\0';
	447	}
	448	}
	449	#endif