[people/ms/u-boot.git] / board / socrates / tlb.c

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),


	/*
	 * TLB 1:	64M	Non-cacheable, guarded
	 * 0xfc000000	64M	FLASH
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 2:	256M	Non-cacheable, guarded
	 * 0x80000000	256M	PCI1 MEM First half
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 2, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 3:	256M	Non-cacheable, guarded
	 * 0x90000000	256M	PCI1 MEM Second half
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_256M, 1),

#if defined(CONFIG_SYS_FPGA_BASE)
	/*
	 * TLB 4:	1M	Non-cacheable, guarded
	 * 0xc0000000	1M	FPGA and NAND
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_1M, 1),
#endif

	/*
	 * TLB 5:	64M	Non-cacheable, guarded
	 * 0xc8000000	16M	LIME GDC framebuffer
	 * 0xc9fc0000	256K	LIME GDC MMIO
	 * (0xcbfc0000	256K	LIME GDC MMIO)
	 * MMIO is relocatable and could be at 0xcbfc0000
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 6:	64M	Non-cacheable, guarded
	 * 0xe000_0000	1M	CCSRBAR
	 * 0xe200_0000	16M	PCI1 IO
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 6, BOOKE_PAGESZ_64M, 1),

#if !defined(CONFIG_SPD_EEPROM)
	/*
	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
	 * 0x00000000  512M	DDR System memory
	 * Without SPD EEPROM configured DDR, this must be setup manually.
	 * Make sure the TLB count at the top of this table is correct.
	 * Likely it needs to be increased by two for these entries.
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 7, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 8, BOOKE_PAGESZ_256M, 1),
#endif
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Copyright 2008 Freescale Semiconductor, Inc.
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	11	*/
	12
	13	#include <common.h>
	14	#include <asm/mmu.h>
	15
	16	struct fsl_e_tlb_entry tlb_table[] = {
	17	/* TLB 0 - for temp stack in cache */
6d0f6bcf	18	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
5d108ac8 SP	19	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
5d108ac8 SP	20	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	21	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
5d108ac8 SP	22	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
5d108ac8 SP	23	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	24	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
5d108ac8 SP	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
5d108ac8 SP	26	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	27	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
5d108ac8 SP	28	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	29	0, 0, BOOKE_PAGESZ_4K, 0),
	30
	31
	32	/*
e64987a8	33	* TLB 1: 64M Non-cacheable, guarded
59abd15b	34	* 0xfc000000 64M FLASH
5d108ac8 SP	35	* Out of reset this entry is only 4K.
5d108ac8 SP	36	*/
6d0f6bcf	37	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
5d108ac8 SP	38	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
5d108ac8 SP	39	0, 1, BOOKE_PAGESZ_64M, 1),
5d108ac8 SP	40
	41	/*
	42	* TLB 2: 256M Non-cacheable, guarded
	43	* 0x80000000 256M PCI1 MEM First half
	44	*/
6d0f6bcf	45	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
5d108ac8 SP	46	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	47	0, 2, BOOKE_PAGESZ_256M, 1),
	48
	49	/*
	50	* TLB 3: 256M Non-cacheable, guarded
	51	* 0x90000000 256M PCI1 MEM Second half
	52	*/
6d0f6bcf	53	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
5d108ac8 SP	54	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	55	0, 3, BOOKE_PAGESZ_256M, 1),
	56
6d0f6bcf	57	#if defined(CONFIG_SYS_FPGA_BASE)
5d108ac8	58	/*
59abd15b SP	59	* TLB 4: 1M Non-cacheable, guarded
59abd15b SP	60	* 0xc0000000 1M FPGA and NAND
5d108ac8	61	*/
6d0f6bcf	62	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
5d108ac8	63	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
59abd15b SP	64	0, 4, BOOKE_PAGESZ_1M, 1),
59abd15b SP	65	#endif
5d108ac8	66
e64987a8 AG	67	/*
	68	* TLB 5: 64M Non-cacheable, guarded
	69	* 0xc8000000 16M LIME GDC framebuffer
	70	* 0xc9fc0000 256K LIME GDC MMIO
	71	* (0xcbfc0000 256K LIME GDC MMIO)
	72	* MMIO is relocatable and could be at 0xcbfc0000
	73	*/
6d0f6bcf	74	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
e64987a8 AG	75	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	76	0, 5, BOOKE_PAGESZ_64M, 1),
	77
5d108ac8 SP	78	/*
	79	* TLB 6: 64M Non-cacheable, guarded
	80	* 0xe000_0000 1M CCSRBAR
	81	* 0xe200_0000 16M PCI1 IO
	82	*/
6d0f6bcf	83	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
5d108ac8 SP	84	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	85	0, 6, BOOKE_PAGESZ_64M, 1),
	86
dd332e18	87	#if !defined(CONFIG_SPD_EEPROM)
5d108ac8 SP	88	/*
	89	* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
	90	* 0x00000000 512M DDR System memory
	91	* Without SPD EEPROM configured DDR, this must be setup manually.
	92	* Make sure the TLB count at the top of this table is correct.
	93	* Likely it needs to be increased by two for these entries.
	94	*/
6d0f6bcf	95	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
5d108ac8 SP	96	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	97	0, 7, BOOKE_PAGESZ_256M, 1),
	98
6d0f6bcf	99	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
5d108ac8 SP	100	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
5d108ac8 SP	101	0, 8, BOOKE_PAGESZ_256M, 1),
dd332e18	102	#endif
5d108ac8 SP	103	};
	104
	105	int num_tlb_entries = ARRAY_SIZE(tlb_table);