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566c9c16 VK |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
566c9c16 VK |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <i2c.h> | |
11 | #include <net.h> | |
0b7ff3f4 | 12 | #include <linux/mtd/st_smi.h> |
566c9c16 VK |
13 | #include <asm/io.h> |
14 | #include <asm/arch/hardware.h> | |
4bfacad4 | 15 | #include <asm/arch/spr_emi.h> |
566c9c16 VK |
16 | #include <asm/arch/spr_defs.h> |
17 | ||
18 | #define CPU 0 | |
19 | #define DDR 1 | |
20 | #define SRAM_REL 0xD2801000 | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
566c9c16 | 23 | |
8026b1e4 VK |
24 | #if defined(CONFIG_CMD_NET) |
25 | static int i2c_read_mac(uchar *buffer); | |
26 | #endif | |
27 | ||
566c9c16 VK |
28 | int dram_init(void) |
29 | { | |
5cca72f8 | 30 | /* Store complete RAM size and return */ |
a39fcfb2 | 31 | gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); |
566c9c16 | 32 | |
566c9c16 VK |
33 | return 0; |
34 | } | |
35 | ||
76b00aca | 36 | int dram_init_banksize(void) |
a39fcfb2 SH |
37 | { |
38 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
39 | gd->bd->bi_dram[0].size = gd->ram_size; | |
76b00aca SG |
40 | |
41 | return 0; | |
a39fcfb2 SH |
42 | } |
43 | ||
0b7ff3f4 AV |
44 | int board_early_init_f() |
45 | { | |
46 | #if defined(CONFIG_ST_SMI) | |
47 | smi_init(); | |
48 | #endif | |
49 | return 0; | |
50 | } | |
566c9c16 VK |
51 | int misc_init_r(void) |
52 | { | |
f92994f0 VK |
53 | #if defined(CONFIG_CMD_NET) |
54 | uchar mac_id[6]; | |
55 | ||
56 | if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) | |
fd1e959e | 57 | eth_env_set_enetaddr("ethaddr", mac_id); |
f92994f0 | 58 | #endif |
382bee57 | 59 | env_set("verify", "n"); |
566c9c16 VK |
60 | |
61 | #if defined(CONFIG_SPEAR_USBTTY) | |
382bee57 SG |
62 | env_set("stdin", "usbtty"); |
63 | env_set("stdout", "usbtty"); | |
64 | env_set("stderr", "usbtty"); | |
bda7f435 SH |
65 | |
66 | #ifndef CONFIG_SYS_NO_DCACHE | |
67 | dcache_enable(); | |
68 | #endif | |
566c9c16 VK |
69 | #endif |
70 | return 0; | |
71 | } | |
72 | ||
4bfacad4 VK |
73 | #ifdef CONFIG_SPEAR_EMI |
74 | struct cust_emi_para { | |
75 | unsigned int tap; | |
76 | unsigned int tsdp; | |
77 | unsigned int tdpw; | |
78 | unsigned int tdpr; | |
79 | unsigned int tdcs; | |
80 | }; | |
81 | ||
82 | /* EMI timing setting of m28w640hc of linux kernel */ | |
83 | const struct cust_emi_para emi_timing_m28w640hc = { | |
84 | .tap = 0x10, | |
85 | .tsdp = 0x05, | |
86 | .tdpw = 0x0a, | |
87 | .tdpr = 0x0a, | |
88 | .tdcs = 0x05, | |
89 | }; | |
90 | ||
91 | /* EMI timing setting of bootrom */ | |
92 | const struct cust_emi_para emi_timing_bootrom = { | |
93 | .tap = 0xf, | |
94 | .tsdp = 0x0, | |
95 | .tdpw = 0xff, | |
96 | .tdpr = 0x111, | |
97 | .tdcs = 0x02, | |
98 | }; | |
99 | ||
100 | void spear_emi_init(void) | |
101 | { | |
102 | const struct cust_emi_para *p = &emi_timing_m28w640hc; | |
103 | struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; | |
104 | unsigned int cs; | |
105 | unsigned int val, tmp; | |
106 | ||
107 | val = readl(CONFIG_SPEAR_RASBASE); | |
108 | ||
109 | if (val & EMI_ACKMSK) | |
110 | tmp = 0x3f; | |
111 | else | |
112 | tmp = 0x0; | |
113 | ||
114 | writel(tmp, &emi_regs_p->ack); | |
115 | ||
116 | for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { | |
117 | writel(p->tap, &emi_regs_p->bank_regs[cs].tap); | |
118 | writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); | |
119 | writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); | |
120 | writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); | |
121 | writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); | |
122 | writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), | |
123 | &emi_regs_p->bank_regs[cs].control); | |
124 | } | |
125 | } | |
126 | #endif | |
127 | ||
566c9c16 VK |
128 | int spear_board_init(ulong mach_type) |
129 | { | |
566c9c16 VK |
130 | gd->bd->bi_arch_number = mach_type; |
131 | ||
132 | /* adress of boot parameters */ | |
133 | gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; | |
134 | ||
4bfacad4 VK |
135 | #ifdef CONFIG_SPEAR_EMI |
136 | spear_emi_init(); | |
137 | #endif | |
566c9c16 VK |
138 | return 0; |
139 | } | |
140 | ||
8026b1e4 | 141 | #if defined(CONFIG_CMD_NET) |
f92994f0 VK |
142 | static int i2c_read_mac(uchar *buffer) |
143 | { | |
144 | u8 buf[2]; | |
145 | ||
146 | i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); | |
147 | ||
148 | /* Check if mac in i2c memory is valid */ | |
149 | if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { | |
150 | /* Valid mac address is saved in i2c eeprom */ | |
151 | i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | return -1; | |
156 | } | |
157 | ||
158 | static int write_mac(uchar *mac) | |
159 | { | |
160 | u8 buf[2]; | |
161 | ||
162 | buf[0] = (u8)MAGIC_BYTE0; | |
163 | buf[1] = (u8)MAGIC_BYTE1; | |
164 | i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); | |
165 | ||
166 | buf[0] = (u8)~MAGIC_BYTE0; | |
167 | buf[1] = (u8)~MAGIC_BYTE1; | |
168 | ||
169 | i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); | |
170 | ||
171 | /* check if valid MAC address is saved in I2C EEPROM or not? */ | |
172 | if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { | |
173 | i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); | |
174 | puts("I2C EEPROM written with mac address \n"); | |
175 | return 0; | |
176 | } | |
177 | ||
8026b1e4 | 178 | puts("I2C EEPROM writing failed\n"); |
f92994f0 VK |
179 | return -1; |
180 | } | |
8026b1e4 | 181 | #endif |
f92994f0 | 182 | |
54841ab5 | 183 | int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
566c9c16 VK |
184 | { |
185 | void (*sram_setfreq) (unsigned int, unsigned int); | |
8026b1e4 VK |
186 | unsigned int frequency; |
187 | #if defined(CONFIG_CMD_NET) | |
566c9c16 | 188 | unsigned char mac[6]; |
8026b1e4 | 189 | #endif |
566c9c16 | 190 | |
47e26b1b WD |
191 | if ((argc > 3) || (argc < 2)) |
192 | return cmd_usage(cmdtp); | |
566c9c16 VK |
193 | |
194 | if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) { | |
195 | ||
196 | frequency = simple_strtoul(argv[2], NULL, 0); | |
197 | ||
198 | if (frequency > 333) { | |
199 | printf("Frequency is limited to 333MHz\n"); | |
200 | return 1; | |
201 | } | |
202 | ||
203 | sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz); | |
204 | ||
205 | if (!strcmp(argv[1], "cpufreq")) { | |
206 | sram_setfreq(CPU, frequency); | |
207 | printf("CPU frequency changed to %u\n", frequency); | |
566c9c16 VK |
208 | } else { |
209 | sram_setfreq(DDR, frequency); | |
210 | printf("DDR frequency changed to %u\n", frequency); | |
566c9c16 VK |
211 | } |
212 | ||
f92994f0 | 213 | return 0; |
8026b1e4 VK |
214 | |
215 | #if defined(CONFIG_CMD_NET) | |
f92994f0 VK |
216 | } else if (!strcmp(argv[1], "ethaddr")) { |
217 | ||
8026b1e4 VK |
218 | u32 reg; |
219 | char *e, *s = argv[2]; | |
f92994f0 VK |
220 | for (reg = 0; reg < 6; ++reg) { |
221 | mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; | |
222 | if (s) | |
223 | s = (*e) ? e + 1 : e; | |
224 | } | |
225 | write_mac(mac); | |
226 | ||
566c9c16 | 227 | return 0; |
8026b1e4 | 228 | #endif |
566c9c16 | 229 | } else if (!strcmp(argv[1], "print")) { |
8026b1e4 | 230 | #if defined(CONFIG_CMD_NET) |
f92994f0 | 231 | if (!i2c_read_mac(mac)) { |
8026b1e4 | 232 | printf("Ethaddr (from i2c mem) = %pM\n", mac); |
f92994f0 VK |
233 | } else { |
234 | printf("Ethaddr (from i2c mem) = Not set\n"); | |
235 | } | |
8026b1e4 | 236 | #endif |
566c9c16 VK |
237 | return 0; |
238 | } | |
239 | ||
47e26b1b | 240 | return cmd_usage(cmdtp); |
566c9c16 VK |
241 | } |
242 | ||
243 | U_BOOT_CMD(chip_config, 3, 1, do_chip_config, | |
244 | "configure chip", | |
245 | "chip_config cpufreq/ddrfreq frequency\n" | |
8026b1e4 VK |
246 | #if defined(CONFIG_CMD_NET) |
247 | "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" | |
248 | #endif | |
566c9c16 | 249 | "chip_config print"); |