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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
9fa32b12 | 2 | /* |
1537d386 PC |
3 | * Copyright (C) 2014, STMicroelectronics - All Rights Reserved |
4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. | |
9fa32b12 VM |
5 | */ |
6 | ||
7 | #include <common.h> | |
52f24238 | 8 | #include <bootstage.h> |
9d922450 | 9 | #include <dm.h> |
691d719d | 10 | #include <init.h> |
9fa32b12 | 11 | #include <miiphy.h> |
90526e9f | 12 | #include <net.h> |
9fa32b12 VM |
13 | #include <asm/arch/stv0991_periph.h> |
14 | #include <asm/arch/stv0991_defs.h> | |
2ce4eaf4 VM |
15 | #include <asm/arch/hardware.h> |
16 | #include <asm/arch/gpio.h> | |
17 | #include <netdev.h> | |
401d1c4f | 18 | #include <asm/global_data.h> |
2ce4eaf4 | 19 | #include <asm/io.h> |
39e4795a | 20 | #include <dm/platform_data/serial_pl01x.h> |
9fa32b12 VM |
21 | |
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
2ce4eaf4 VM |
24 | struct gpio_regs *const gpioa_regs = |
25 | (struct gpio_regs *) GPIOA_BASE_ADDR; | |
26 | ||
e0320b74 | 27 | #ifndef CONFIG_OF_CONTROL |
8a8d24bd | 28 | static const struct pl01x_serial_plat serial_plat = { |
39e4795a VM |
29 | .base = 0x80406000, |
30 | .type = TYPE_PL011, | |
31 | .clock = 2700 * 1000, | |
32 | }; | |
33 | ||
20e442ab | 34 | U_BOOT_DRVINFO(stv09911_serials) = { |
39e4795a | 35 | .name = "serial_pl01x", |
8a8d24bd | 36 | .plat = &serial_plat, |
39e4795a | 37 | }; |
e0320b74 | 38 | #endif |
39e4795a | 39 | |
cb80ff20 | 40 | #if CONFIG_IS_ENABLED(BOOTSTAGE) |
9fa32b12 VM |
41 | void show_boot_progress(int progress) |
42 | { | |
43 | printf("%i\n", progress); | |
44 | } | |
45 | #endif | |
46 | ||
2ce4eaf4 VM |
47 | void enable_eth_phy(void) |
48 | { | |
49 | /* Set GPIOA_06 pad HIGH (Appli board)*/ | |
50 | writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); | |
51 | writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); | |
52 | } | |
53 | int board_eth_enable(void) | |
54 | { | |
55 | stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); | |
56 | clock_setup(ETH_CLOCK_CFG); | |
57 | enable_eth_phy(); | |
58 | return 0; | |
59 | } | |
60 | ||
54afb500 VM |
61 | int board_qspi_enable(void) |
62 | { | |
63 | stv0991_pinmux_config(QSPI_CS_CLK_PAD); | |
64 | clock_setup(QSPI_CLOCK_CFG); | |
65 | return 0; | |
66 | } | |
67 | ||
9fa32b12 VM |
68 | /* |
69 | * Miscellaneous platform dependent initialisations | |
70 | */ | |
71 | int board_init(void) | |
72 | { | |
2ce4eaf4 | 73 | board_eth_enable(); |
54afb500 | 74 | board_qspi_enable(); |
9fa32b12 VM |
75 | return 0; |
76 | } | |
77 | ||
78 | int board_uart_init(void) | |
79 | { | |
80 | stv0991_pinmux_config(UART_GPIOC_30_31); | |
81 | clock_setup(UART_CLOCK_CFG); | |
82 | return 0; | |
83 | } | |
2ce4eaf4 | 84 | |
9fa32b12 VM |
85 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
86 | int board_early_init_f(void) | |
87 | { | |
88 | board_uart_init(); | |
89 | return 0; | |
90 | } | |
91 | #endif | |
92 | ||
93 | int dram_init(void) | |
94 | { | |
95 | gd->ram_size = PHYS_SDRAM_1_SIZE; | |
96 | return 0; | |
97 | } | |
98 | ||
76b00aca | 99 | int dram_init_banksize(void) |
9fa32b12 VM |
100 | { |
101 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
102 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
76b00aca SG |
103 | |
104 | return 0; | |
9fa32b12 | 105 | } |
2ce4eaf4 VM |
106 | |
107 | #ifdef CONFIG_CMD_NET | |
b75d8dc5 | 108 | int board_eth_init(struct bd_info *bis) |
2ce4eaf4 VM |
109 | { |
110 | int ret = 0; | |
111 | ||
ef48f6dd | 112 | #if defined(CONFIG_ETH_DESIGNWARE) |
2ce4eaf4 VM |
113 | u32 interface = PHY_INTERFACE_MODE_MII; |
114 | if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) | |
115 | ret++; | |
116 | #endif | |
117 | return ret; | |
118 | } | |
119 | #endif |