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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
44d8ae5b HG |
3 | # Note only one of these may be selected at a time! But hidden choices are |
4 | # not supported by Kconfig | |
5 | config SUNXI_GEN_SUN4I | |
6 | bool | |
7 | ---help--- | |
8 | Select this for sunxi SoCs which have resets and clocks set up | |
9 | as the original A10 (mach-sun4i). | |
10 | ||
11 | config SUNXI_GEN_SUN6I | |
12 | bool | |
13 | ---help--- | |
14 | Select this for sunxi SoCs which have sun6i like periphery, like | |
15 | separate ahb reset control registers, custom pmic bus, new style | |
16 | watchdog, etc. | |
17 | ||
18 | ||
2c7e3b90 IC |
19 | choice |
20 | prompt "Sunxi SoC Variant" | |
21 | ||
c3be2793 | 22 | config MACH_SUN4I |
2c7e3b90 IC |
23 | bool "sun4i (Allwinner A10)" |
24 | select CPU_V7 | |
44d8ae5b | 25 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
26 | select SUPPORT_SPL |
27 | ||
c3be2793 | 28 | config MACH_SUN5I |
2c7e3b90 IC |
29 | bool "sun5i (Allwinner A13)" |
30 | select CPU_V7 | |
44d8ae5b | 31 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
32 | select SUPPORT_SPL |
33 | ||
c3be2793 | 34 | config MACH_SUN6I |
2c7e3b90 IC |
35 | bool "sun6i (Allwinner A31)" |
36 | select CPU_V7 | |
44d8ae5b | 37 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 38 | select SUPPORT_SPL |
2c7e3b90 | 39 | |
c3be2793 | 40 | config MACH_SUN7I |
2c7e3b90 IC |
41 | bool "sun7i (Allwinner A20)" |
42 | select CPU_V7 | |
ea624e19 HG |
43 | select CPU_V7_HAS_NONSEC |
44 | select CPU_V7_HAS_VIRT | |
44d8ae5b | 45 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 46 | select SUPPORT_SPL |
b366fb92 | 47 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 48 | |
5e6bacdb | 49 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
50 | bool "sun8i (Allwinner A23)" |
51 | select CPU_V7 | |
44d8ae5b | 52 | select SUNXI_GEN_SUN6I |
08fd1479 | 53 | select SUPPORT_SPL |
2c7e3b90 | 54 | |
8c3dacff VP |
55 | config MACH_SUN8I_A33 |
56 | bool "sun8i (Allwinner A33)" | |
57 | select CPU_V7 | |
58 | select SUNXI_GEN_SUN6I | |
59 | select SUPPORT_SPL | |
60 | ||
2c7e3b90 | 61 | endchoice |
8a6564da | 62 | |
5e6bacdb HG |
63 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
64 | config MACH_SUN8I | |
65 | bool | |
66 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 | |
67 | ||
68 | ||
37781a1a | 69 | config DRAM_CLK |
8ffc487c HG |
70 | int "sunxi dram clock speed" |
71 | default 312 if MACH_SUN6I || MACH_SUN8I | |
72 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
37781a1a HG |
73 | ---help--- |
74 | Set the dram clock speed, valid range 240 - 480, must be a multiple | |
e1a0888e | 75 | of 24. |
37781a1a | 76 | |
47e3501a SS |
77 | if MACH_SUN5I || MACH_SUN7I |
78 | config DRAM_MBUS_CLK | |
79 | int "sunxi mbus clock speed" | |
80 | default 300 | |
81 | ---help--- | |
82 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
83 | ||
84 | endif | |
85 | ||
37781a1a | 86 | config DRAM_ZQ |
8ffc487c HG |
87 | int "sunxi dram zq value" |
88 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
89 | default 127 if MACH_SUN7I | |
37781a1a | 90 | ---help--- |
e1a0888e | 91 | Set the dram zq value. |
8ffc487c HG |
92 | |
93 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
94 | config DRAM_EMR1 | |
95 | int "sunxi dram emr1 value" | |
96 | default 0 if MACH_SUN4I | |
97 | default 4 if MACH_SUN5I || MACH_SUN7I | |
98 | ---help--- | |
e1a0888e | 99 | Set the dram controller emr1 value. |
d133647a | 100 | |
47e3501a SS |
101 | config DRAM_ODT_EN |
102 | int "sunxi dram odt_en value" | |
103 | default 0 | |
104 | ---help--- | |
105 | Set the dram controller odt_en parameter. This can be used to | |
106 | enable/disable the ODT feature. | |
107 | ||
108 | config DRAM_TPR3 | |
109 | hex "sunxi dram tpr3 value" | |
110 | default 0 | |
111 | ---help--- | |
112 | Set the dram controller tpr3 parameter. This parameter configures | |
113 | the delay on the command lane and also phase shifts, which are | |
114 | applied for sampling incoming read data. The default value 0 | |
115 | means that no phase/delay adjustments are necessary. Properly | |
116 | configuring this parameter increases reliability at high DRAM | |
117 | clock speeds. | |
118 | ||
119 | config DRAM_DQS_GATING_DELAY | |
120 | hex "sunxi dram dqs_gating_delay value" | |
121 | default 0 | |
122 | ---help--- | |
123 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
124 | encodes the DQS gating delay for each byte lane. The delay | |
125 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
126 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
127 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
128 | The default value 0 means autodetection. The results of hardware | |
129 | autodetection are not very reliable and depend on the chip | |
130 | temperature (sometimes producing different results on cold start | |
131 | and warm reboot). But the accuracy of hardware autodetection | |
132 | is usually good enough, unless running at really high DRAM | |
133 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
134 | ||
d133647a SS |
135 | choice |
136 | prompt "sunxi dram timings" | |
137 | default DRAM_TIMINGS_VENDOR_MAGIC | |
138 | ---help--- | |
139 | Select the timings of the DDR3 chips. | |
140 | ||
141 | config DRAM_TIMINGS_VENDOR_MAGIC | |
142 | bool "Magic vendor timings from Android" | |
143 | ---help--- | |
144 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
145 | ||
146 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
147 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
148 | ---help--- | |
149 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
150 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
151 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
152 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
153 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
154 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
155 | uses a bit faster timings than DDR3-1333H). | |
156 | ||
157 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
158 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
159 | ---help--- | |
160 | Use the timings of the slowest possible JEDEC speed bin for the | |
161 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
162 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
163 | ||
164 | endchoice | |
165 | ||
37781a1a HG |
166 | endif |
167 | ||
e71b422b IP |
168 | config SYS_CLK_FREQ |
169 | default 912000000 if MACH_SUN7I | |
170 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
171 | ||
8a6564da | 172 | config SYS_CONFIG_NAME |
c3be2793 IC |
173 | default "sun4i" if MACH_SUN4I |
174 | default "sun5i" if MACH_SUN5I | |
175 | default "sun6i" if MACH_SUN6I | |
176 | default "sun7i" if MACH_SUN7I | |
177 | default "sun8i" if MACH_SUN8I | |
dd84058d | 178 | |
dd84058d | 179 | config SYS_BOARD |
dd84058d MY |
180 | default "sunxi" |
181 | ||
182 | config SYS_SOC | |
dd84058d MY |
183 | default "sunxi" |
184 | ||
4ce9941d IC |
185 | config SPL_FEL |
186 | bool "SPL/FEL mode support" | |
187 | depends on SPL | |
188 | default n | |
942cb0b6 SG |
189 | help |
190 | This enables support for Fast Early Loader (FEL) mode. This | |
191 | allows U-Boot to be loaded to the board over USB by the on-chip | |
192 | boot rom. U-Boot should be sent in two parts: SPL first, with | |
193 | 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with | |
194 | 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option | |
195 | shrinks the amount of SRAM available to SPL, so only enable it if | |
196 | you need FEL. Note that enabling this option only allows FEL to be | |
197 | used; it is still possible to boot U-Boot from boot media. U-Boot | |
198 | SPL detects when it is being loaded using FEL. | |
4ce9941d | 199 | |
f0ce28e9 SS |
200 | config UART0_PORT_F |
201 | bool "UART0 on MicroSD breakout board" | |
202 | depends on SPL_FEL | |
203 | default n | |
204 | ---help--- | |
205 | Repurpose the SD card slot for getting access to the UART0 serial | |
206 | console. Primarily useful only for low level u-boot debugging on | |
207 | tablets, where normal UART0 is difficult to access and requires | |
208 | device disassembly and/or soldering. As the SD card can't be used | |
209 | at the same time, the system can be only booted in the FEL mode. | |
210 | Only enable this if you really know what you are doing. | |
211 | ||
accc9e44 HG |
212 | config OLD_SUNXI_KERNEL_COMPAT |
213 | boolean "Enable workarounds for booting old kernels" | |
214 | default n | |
215 | ---help--- | |
216 | Set this to enable various workarounds for old kernels, this results in | |
217 | sub-optimal settings for newer kernels, only enable if needed. | |
218 | ||
cd82113a HG |
219 | config MMC0_CD_PIN |
220 | string "Card detect pin for mmc0" | |
221 | default "" | |
222 | ---help--- | |
223 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
224 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
225 | PH1 for pin 1 of port H. | |
226 | ||
227 | config MMC1_CD_PIN | |
228 | string "Card detect pin for mmc1" | |
229 | default "" | |
230 | ---help--- | |
231 | See MMC0_CD_PIN help text. | |
232 | ||
233 | config MMC2_CD_PIN | |
234 | string "Card detect pin for mmc2" | |
235 | default "" | |
236 | ---help--- | |
237 | See MMC0_CD_PIN help text. | |
238 | ||
239 | config MMC3_CD_PIN | |
240 | string "Card detect pin for mmc3" | |
241 | default "" | |
242 | ---help--- | |
243 | See MMC0_CD_PIN help text. | |
244 | ||
8deacca9 PK |
245 | config MMC1_PINS |
246 | string "Pins for mmc1" | |
247 | default "" | |
248 | ---help--- | |
249 | Set the pins used for mmc1, when applicable. This takes a string in the | |
250 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
251 | ||
252 | config MMC2_PINS | |
253 | string "Pins for mmc2" | |
254 | default "" | |
255 | ---help--- | |
256 | See MMC1_PINS help text. | |
257 | ||
258 | config MMC3_PINS | |
259 | string "Pins for mmc3" | |
260 | default "" | |
261 | ---help--- | |
262 | See MMC1_PINS help text. | |
263 | ||
2ccfac01 HG |
264 | config MMC_SUNXI_SLOT_EXTRA |
265 | int "mmc extra slot number" | |
266 | default -1 | |
267 | ---help--- | |
268 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
269 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
270 | support for this. | |
271 | ||
4458b7a6 HG |
272 | config USB0_VBUS_PIN |
273 | string "Vbus enable pin for usb0 (otg)" | |
274 | default "" | |
275 | ---help--- | |
276 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
277 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
278 | ||
52defe8f HG |
279 | config USB0_VBUS_DET |
280 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
281 | default "" |
282 | ---help--- | |
283 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
284 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
285 | ||
115200ce HG |
286 | config USB1_VBUS_PIN |
287 | string "Vbus enable pin for usb1 (ehci0)" | |
288 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 289 | default "PH27" if MACH_SUN6I |
115200ce HG |
290 | ---help--- |
291 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
292 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
293 | PH1 for pin 1 of port H. | |
294 | ||
295 | config USB2_VBUS_PIN | |
296 | string "Vbus enable pin for usb2 (ehci1)" | |
297 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 298 | default "PH24" if MACH_SUN6I |
115200ce HG |
299 | ---help--- |
300 | See USB1_VBUS_PIN help text. | |
301 | ||
6c739c5d PK |
302 | config I2C0_ENABLE |
303 | bool "Enable I2C/TWI controller 0" | |
304 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
305 | default n if MACH_SUN6I || MACH_SUN8I | |
306 | ---help--- | |
307 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
308 | its clock and setting up the bus. This is especially useful on devices | |
309 | with slaves connected to the bus or with pins exposed through e.g. an | |
310 | expansion port/header. | |
311 | ||
312 | config I2C1_ENABLE | |
313 | bool "Enable I2C/TWI controller 1" | |
314 | default n | |
315 | ---help--- | |
316 | See I2C0_ENABLE help text. | |
317 | ||
318 | config I2C2_ENABLE | |
319 | bool "Enable I2C/TWI controller 2" | |
320 | default n | |
321 | ---help--- | |
322 | See I2C0_ENABLE help text. | |
323 | ||
324 | if MACH_SUN6I || MACH_SUN7I | |
325 | config I2C3_ENABLE | |
326 | bool "Enable I2C/TWI controller 3" | |
327 | default n | |
328 | ---help--- | |
329 | See I2C0_ENABLE help text. | |
330 | endif | |
331 | ||
332 | if MACH_SUN7I | |
333 | config I2C4_ENABLE | |
334 | bool "Enable I2C/TWI controller 4" | |
335 | default n | |
336 | ---help--- | |
337 | See I2C0_ENABLE help text. | |
338 | endif | |
339 | ||
2fcf033d HG |
340 | config AXP_GPIO |
341 | boolean "Enable support for gpio-s on axp PMICs" | |
342 | default n | |
343 | ---help--- | |
344 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
345 | ||
7f2c521f | 346 | config VIDEO |
2dae800f | 347 | boolean "Enable graphical uboot console on HDMI, LCD or VGA" |
7f2c521f LV |
348 | default y |
349 | ---help--- | |
2dae800f HG |
350 | Say Y here to add support for using a cfb console on the HDMI, LCD |
351 | or VGA output found on most sunxi devices. See doc/README.video for | |
352 | info on how to select the video output and mode. | |
353 | ||
2fbf091a HG |
354 | config VIDEO_HDMI |
355 | boolean "HDMI output support" | |
356 | depends on VIDEO && !MACH_SUN8I | |
357 | default y | |
358 | ---help--- | |
359 | Say Y here to add support for outputting video over HDMI. | |
360 | ||
d9786d23 HG |
361 | config VIDEO_VGA |
362 | boolean "VGA output support" | |
363 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) | |
364 | default n | |
365 | ---help--- | |
366 | Say Y here to add support for outputting video over VGA. | |
367 | ||
e2bbdfb1 HG |
368 | config VIDEO_VGA_VIA_LCD |
369 | boolean "VGA via LCD controller support" | |
2583d5b1 | 370 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
371 | default n |
372 | ---help--- | |
373 | Say Y here to add support for external DACs connected to the parallel | |
374 | LCD interface driving a VGA connector, such as found on the | |
375 | Olimex A13 boards. | |
376 | ||
fb75d972 HG |
377 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
378 | boolean "Force sync active high for VGA via LCD controller support" | |
379 | depends on VIDEO_VGA_VIA_LCD | |
380 | default n | |
381 | ---help--- | |
382 | Say Y here if you've a board which uses opendrain drivers for the vga | |
383 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
384 | positive edges for a stable video output, so on boards with opendrain | |
385 | drivers the sync signals must always be active high. | |
386 | ||
507e27df CYT |
387 | config VIDEO_VGA_EXTERNAL_DAC_EN |
388 | string "LCD panel power enable pin" | |
389 | depends on VIDEO_VGA_VIA_LCD | |
390 | default "" | |
391 | ---help--- | |
392 | Set the enable pin for the external VGA DAC. This takes a string in the | |
393 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
394 | ||
2dae800f HG |
395 | config VIDEO_LCD_MODE |
396 | string "LCD panel timing details" | |
397 | depends on VIDEO | |
398 | default "" | |
399 | ---help--- | |
400 | LCD panel timing details string, leave empty if there is no LCD panel. | |
401 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
402 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
403 | ||
6515032e HG |
404 | config VIDEO_LCD_DCLK_PHASE |
405 | int "LCD panel display clock phase" | |
406 | depends on VIDEO | |
407 | default 1 | |
408 | ---help--- | |
409 | Select LCD panel display clock phase shift, range 0-3. | |
410 | ||
2dae800f HG |
411 | config VIDEO_LCD_POWER |
412 | string "LCD panel power enable pin" | |
413 | depends on VIDEO | |
414 | default "" | |
415 | ---help--- | |
416 | Set the power enable pin for the LCD panel. This takes a string in the | |
417 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
418 | ||
242e3d89 HG |
419 | config VIDEO_LCD_RESET |
420 | string "LCD panel reset pin" | |
421 | depends on VIDEO | |
422 | default "" | |
423 | ---help--- | |
424 | Set the reset pin for the LCD panel. This takes a string in the format | |
425 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
426 | ||
2dae800f HG |
427 | config VIDEO_LCD_BL_EN |
428 | string "LCD panel backlight enable pin" | |
429 | depends on VIDEO | |
430 | default "" | |
431 | ---help--- | |
432 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
433 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
434 | port H. | |
435 | ||
436 | config VIDEO_LCD_BL_PWM | |
437 | string "LCD panel backlight pwm pin" | |
438 | depends on VIDEO | |
439 | default "" | |
440 | ---help--- | |
441 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
442 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 443 | |
a7403ae8 HG |
444 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
445 | bool "LCD panel backlight pwm is inverted" | |
446 | depends on VIDEO | |
447 | default y | |
448 | ---help--- | |
449 | Set this if the backlight pwm output is active low. | |
450 | ||
55410089 HG |
451 | config VIDEO_LCD_PANEL_I2C |
452 | bool "LCD panel needs to be configured via i2c" | |
453 | depends on VIDEO | |
1fc42018 | 454 | default n |
55410089 HG |
455 | ---help--- |
456 | Say y here if the LCD panel needs to be configured via i2c. This | |
457 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
458 | ||
459 | config VIDEO_LCD_PANEL_I2C_SDA | |
460 | string "LCD panel i2c interface SDA pin" | |
461 | depends on VIDEO_LCD_PANEL_I2C | |
462 | default "PG12" | |
463 | ---help--- | |
464 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
465 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
466 | ||
467 | config VIDEO_LCD_PANEL_I2C_SCL | |
468 | string "LCD panel i2c interface SCL pin" | |
469 | depends on VIDEO_LCD_PANEL_I2C | |
470 | default "PG10" | |
471 | ---help--- | |
472 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
473 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
474 | ||
213480e1 HG |
475 | |
476 | # Note only one of these may be selected at a time! But hidden choices are | |
477 | # not supported by Kconfig | |
478 | config VIDEO_LCD_IF_PARALLEL | |
479 | bool | |
480 | ||
481 | config VIDEO_LCD_IF_LVDS | |
482 | bool | |
483 | ||
484 | ||
485 | choice | |
486 | prompt "LCD panel support" | |
487 | depends on VIDEO | |
488 | ---help--- | |
489 | Select which type of LCD panel to support. | |
490 | ||
491 | config VIDEO_LCD_PANEL_PARALLEL | |
492 | bool "Generic parallel interface LCD panel" | |
493 | select VIDEO_LCD_IF_PARALLEL | |
494 | ||
495 | config VIDEO_LCD_PANEL_LVDS | |
496 | bool "Generic lvds interface LCD panel" | |
497 | select VIDEO_LCD_IF_LVDS | |
498 | ||
97ece830 SS |
499 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
500 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
501 | select VIDEO_LCD_SSD2828 | |
502 | select VIDEO_LCD_IF_PARALLEL | |
503 | ---help--- | |
504 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 | |
505 | ||
27515b20 HG |
506 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
507 | bool "Hitachi tx18d42vm LCD panel" | |
508 | select VIDEO_LCD_HITACHI_TX18D42VM | |
509 | select VIDEO_LCD_IF_LVDS | |
510 | ---help--- | |
511 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
512 | ||
aad2ac24 HG |
513 | config VIDEO_LCD_TL059WV5C0 |
514 | bool "tl059wv5c0 LCD panel" | |
515 | select VIDEO_LCD_PANEL_I2C | |
516 | select VIDEO_LCD_IF_PARALLEL | |
517 | ---help--- | |
518 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
519 | Aigo M60/M608/M606 tablets. | |
520 | ||
213480e1 HG |
521 | endchoice |
522 | ||
523 | ||
1a800f7a HG |
524 | config USB_MUSB_SUNXI |
525 | bool "Enable sunxi OTG / DRC USB controller in host mode" | |
526 | default n | |
527 | ---help--- | |
528 | Say y here to enable support for the sunxi OTG / DRC USB controller | |
529 | used on almost all sunxi boards. Note currently u-boot can only have | |
530 | one usb host controller enabled at a time, so enabling this on boards | |
531 | which also use the ehci host controller will result in build errors. | |
532 | ||
86b49093 HG |
533 | config USB_KEYBOARD |
534 | boolean "Enable USB keyboard support" | |
535 | default y | |
536 | ---help--- | |
537 | Say Y here to add support for using a USB keyboard (typically used | |
2dae800f | 538 | in combination with a graphical console). |
86b49093 | 539 | |
c13f60d9 HG |
540 | config GMAC_TX_DELAY |
541 | int "GMAC Transmit Clock Delay Chain" | |
542 | default 0 | |
543 | ---help--- | |
544 | Set the GMAC Transmit Clock Delay Chain value. | |
545 | ||
dd84058d | 546 | endif |