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sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
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CommitLineData
2c7e3b90
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1if ARCH_SUNXI
2
44d8ae5b
HG
3# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
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19choice
20 prompt "Sunxi SoC Variant"
a26cd049 21 optional
2c7e3b90 22
c3be2793 23config MACH_SUN4I
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24 bool "sun4i (Allwinner A10)"
25 select CPU_V7
44d8ae5b 26 select SUNXI_GEN_SUN4I
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27 select SUPPORT_SPL
28
c3be2793 29config MACH_SUN5I
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30 bool "sun5i (Allwinner A13)"
31 select CPU_V7
44d8ae5b 32 select SUNXI_GEN_SUN4I
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33 select SUPPORT_SPL
34
c3be2793 35config MACH_SUN6I
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36 bool "sun6i (Allwinner A31)"
37 select CPU_V7
cc08ea4c
CYT
38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
44d8ae5b 40 select SUNXI_GEN_SUN6I
8c2c9cfa 41 select SUPPORT_SPL
cc08ea4c 42 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 43
c3be2793 44config MACH_SUN7I
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45 bool "sun7i (Allwinner A20)"
46 select CPU_V7
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47 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
44d8ae5b 49 select SUNXI_GEN_SUN4I
2c7e3b90 50 select SUPPORT_SPL
b366fb92 51 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 52
5e6bacdb 53config MACH_SUN8I_A23
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54 bool "sun8i (Allwinner A23)"
55 select CPU_V7
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56 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
44d8ae5b 58 select SUNXI_GEN_SUN6I
08fd1479 59 select SUPPORT_SPL
014414f5 60 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 61
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62config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
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65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
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VP
67 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
014414f5 69 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
8c3dacff 70
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HG
71config MACH_SUN9I
72 bool "sun9i (Allwinner A80)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
75
2c7e3b90 76endchoice
8a6564da 77
5e6bacdb
HG
78# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
79config MACH_SUN8I
80 bool
81 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
82
83
37781a1a 84config DRAM_CLK
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HG
85 int "sunxi dram clock speed"
86 default 312 if MACH_SUN6I || MACH_SUN8I
87 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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HG
88 ---help---
89 Set the dram clock speed, valid range 240 - 480, must be a multiple
e1a0888e 90 of 24.
37781a1a 91
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92if MACH_SUN5I || MACH_SUN7I
93config DRAM_MBUS_CLK
94 int "sunxi mbus clock speed"
95 default 300
96 ---help---
97 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
98
99endif
100
37781a1a 101config DRAM_ZQ
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102 int "sunxi dram zq value"
103 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
104 default 127 if MACH_SUN7I
37781a1a 105 ---help---
e1a0888e 106 Set the dram zq value.
8ffc487c 107
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108config DRAM_ODT_EN
109 bool "sunxi dram odt enable"
110 default n if !MACH_SUN8I_A23
111 default y if MACH_SUN8I_A23
112 ---help---
113 Select this to enable dram odt (on die termination).
114
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115if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
116config DRAM_EMR1
117 int "sunxi dram emr1 value"
118 default 0 if MACH_SUN4I
119 default 4 if MACH_SUN5I || MACH_SUN7I
120 ---help---
e1a0888e 121 Set the dram controller emr1 value.
d133647a 122
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123config DRAM_TPR3
124 hex "sunxi dram tpr3 value"
125 default 0
126 ---help---
127 Set the dram controller tpr3 parameter. This parameter configures
128 the delay on the command lane and also phase shifts, which are
129 applied for sampling incoming read data. The default value 0
130 means that no phase/delay adjustments are necessary. Properly
131 configuring this parameter increases reliability at high DRAM
132 clock speeds.
133
134config DRAM_DQS_GATING_DELAY
135 hex "sunxi dram dqs_gating_delay value"
136 default 0
137 ---help---
138 Set the dram controller dqs_gating_delay parmeter. Each byte
139 encodes the DQS gating delay for each byte lane. The delay
140 granularity is 1/4 cycle. For example, the value 0x05060606
141 means that the delay is 5 quarter-cycles for one lane (1.25
142 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
143 The default value 0 means autodetection. The results of hardware
144 autodetection are not very reliable and depend on the chip
145 temperature (sometimes producing different results on cold start
146 and warm reboot). But the accuracy of hardware autodetection
147 is usually good enough, unless running at really high DRAM
148 clocks speeds (up to 600MHz). If unsure, keep as 0.
149
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150choice
151 prompt "sunxi dram timings"
152 default DRAM_TIMINGS_VENDOR_MAGIC
153 ---help---
154 Select the timings of the DDR3 chips.
155
156config DRAM_TIMINGS_VENDOR_MAGIC
157 bool "Magic vendor timings from Android"
158 ---help---
159 The same DRAM timings as in the Allwinner boot0 bootloader.
160
161config DRAM_TIMINGS_DDR3_1066F_1333H
162 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
163 ---help---
164 Use the timings of the standard JEDEC DDR3-1066F speed bin for
165 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
166 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
167 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
168 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
169 that down binning to DDR3-1066F is supported (because DDR3-1066F
170 uses a bit faster timings than DDR3-1333H).
171
172config DRAM_TIMINGS_DDR3_800E_1066G_1333J
173 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
174 ---help---
175 Use the timings of the slowest possible JEDEC speed bin for the
176 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
177 DDR3-800E, DDR3-1066G or DDR3-1333J.
178
179endchoice
180
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181endif
182
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183if MACH_SUN8I_A23
184config DRAM_ODT_CORRECTION
185 int "sunxi dram odt correction value"
186 default 0
187 ---help---
188 Set the dram odt correction value (range -255 - 255). In allwinner
189 fex files, this option is found in bits 8-15 of the u32 odt_en variable
190 in the [dram] section. When bit 31 of the odt_en variable is set
191 then the correction is negative. Usually the value for this is 0.
192endif
193
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194config SYS_CLK_FREQ
195 default 912000000 if MACH_SUN7I
196 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
197
8a6564da 198config SYS_CONFIG_NAME
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199 default "sun4i" if MACH_SUN4I
200 default "sun5i" if MACH_SUN5I
201 default "sun6i" if MACH_SUN6I
202 default "sun7i" if MACH_SUN7I
203 default "sun8i" if MACH_SUN8I
1871a8ca 204 default "sun9i" if MACH_SUN9I
dd84058d 205
dd84058d 206config SYS_BOARD
dd84058d
MY
207 default "sunxi"
208
209config SYS_SOC
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MY
210 default "sunxi"
211
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212config UART0_PORT_F
213 bool "UART0 on MicroSD breakout board"
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SS
214 default n
215 ---help---
216 Repurpose the SD card slot for getting access to the UART0 serial
217 console. Primarily useful only for low level u-boot debugging on
218 tablets, where normal UART0 is difficult to access and requires
219 device disassembly and/or soldering. As the SD card can't be used
220 at the same time, the system can be only booted in the FEL mode.
221 Only enable this if you really know what you are doing.
222
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223config OLD_SUNXI_KERNEL_COMPAT
224 boolean "Enable workarounds for booting old kernels"
225 default n
226 ---help---
227 Set this to enable various workarounds for old kernels, this results in
228 sub-optimal settings for newer kernels, only enable if needed.
229
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HG
230config MMC0_CD_PIN
231 string "Card detect pin for mmc0"
232 default ""
233 ---help---
234 Set the card detect pin for mmc0, leave empty to not use cd. This
235 takes a string in the format understood by sunxi_name_to_gpio, e.g.
236 PH1 for pin 1 of port H.
237
238config MMC1_CD_PIN
239 string "Card detect pin for mmc1"
240 default ""
241 ---help---
242 See MMC0_CD_PIN help text.
243
244config MMC2_CD_PIN
245 string "Card detect pin for mmc2"
246 default ""
247 ---help---
248 See MMC0_CD_PIN help text.
249
250config MMC3_CD_PIN
251 string "Card detect pin for mmc3"
252 default ""
253 ---help---
254 See MMC0_CD_PIN help text.
255
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256config MMC1_PINS
257 string "Pins for mmc1"
258 default ""
259 ---help---
260 Set the pins used for mmc1, when applicable. This takes a string in the
261 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
262
263config MMC2_PINS
264 string "Pins for mmc2"
265 default ""
266 ---help---
267 See MMC1_PINS help text.
268
269config MMC3_PINS
270 string "Pins for mmc3"
271 default ""
272 ---help---
273 See MMC1_PINS help text.
274
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HG
275config MMC_SUNXI_SLOT_EXTRA
276 int "mmc extra slot number"
277 default -1
278 ---help---
279 sunxi builds always enable mmc0, some boards also have a second sdcard
280 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
281 support for this.
282
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283config SPL_NAND_SUPPORT
284 bool "SPL/NAND mode support"
285 depends on SPL
286 default n
287 ---help---
288 This enables support for booting from NAND internal
289 memory. U-Boot SPL doesn't detect where is it load from,
290 therefore this option is needed to properly load image from
291 flash. Option also disables MMC functionality on U-Boot due to
292 initialization errors encountered, when both controllers are
293 enabled.
294
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HG
295config USB0_VBUS_PIN
296 string "Vbus enable pin for usb0 (otg)"
297 default ""
298 ---help---
299 Set the Vbus enable pin for usb0 (otg). This takes a string in the
300 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
301
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302config USB0_VBUS_DET
303 string "Vbus detect pin for usb0 (otg)"
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HG
304 default ""
305 ---help---
306 Set the Vbus detect pin for usb0 (otg). This takes a string in the
307 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
308
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HG
309config USB1_VBUS_PIN
310 string "Vbus enable pin for usb1 (ehci0)"
311 default "PH6" if MACH_SUN4I || MACH_SUN7I
76946dfe 312 default "PH27" if MACH_SUN6I
115200ce
HG
313 ---help---
314 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
315 a string in the format understood by sunxi_name_to_gpio, e.g.
316 PH1 for pin 1 of port H.
317
318config USB2_VBUS_PIN
319 string "Vbus enable pin for usb2 (ehci1)"
320 default "PH3" if MACH_SUN4I || MACH_SUN7I
76946dfe 321 default "PH24" if MACH_SUN6I
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HG
322 ---help---
323 See USB1_VBUS_PIN help text.
324
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325config I2C0_ENABLE
326 bool "Enable I2C/TWI controller 0"
327 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
328 default n if MACH_SUN6I || MACH_SUN8I
329 ---help---
330 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
331 its clock and setting up the bus. This is especially useful on devices
332 with slaves connected to the bus or with pins exposed through e.g. an
333 expansion port/header.
334
335config I2C1_ENABLE
336 bool "Enable I2C/TWI controller 1"
337 default n
338 ---help---
339 See I2C0_ENABLE help text.
340
341config I2C2_ENABLE
342 bool "Enable I2C/TWI controller 2"
343 default n
344 ---help---
345 See I2C0_ENABLE help text.
346
347if MACH_SUN6I || MACH_SUN7I
348config I2C3_ENABLE
349 bool "Enable I2C/TWI controller 3"
350 default n
351 ---help---
352 See I2C0_ENABLE help text.
353endif
354
355if MACH_SUN7I
356config I2C4_ENABLE
357 bool "Enable I2C/TWI controller 4"
358 default n
359 ---help---
360 See I2C0_ENABLE help text.
361endif
362
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HG
363config AXP_GPIO
364 boolean "Enable support for gpio-s on axp PMICs"
365 default n
366 ---help---
367 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
368
7f2c521f 369config VIDEO
2dae800f 370 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
7f2c521f
LV
371 default y
372 ---help---
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HG
373 Say Y here to add support for using a cfb console on the HDMI, LCD
374 or VGA output found on most sunxi devices. See doc/README.video for
375 info on how to select the video output and mode.
376
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HG
377config VIDEO_HDMI
378 boolean "HDMI output support"
379 depends on VIDEO && !MACH_SUN8I
380 default y
381 ---help---
382 Say Y here to add support for outputting video over HDMI.
383
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HG
384config VIDEO_VGA
385 boolean "VGA output support"
386 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
387 default n
388 ---help---
389 Say Y here to add support for outputting video over VGA.
390
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HG
391config VIDEO_VGA_VIA_LCD
392 boolean "VGA via LCD controller support"
2583d5b1 393 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
e2bbdfb1
HG
394 default n
395 ---help---
396 Say Y here to add support for external DACs connected to the parallel
397 LCD interface driving a VGA connector, such as found on the
398 Olimex A13 boards.
399
fb75d972
HG
400config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
401 boolean "Force sync active high for VGA via LCD controller support"
402 depends on VIDEO_VGA_VIA_LCD
403 default n
404 ---help---
405 Say Y here if you've a board which uses opendrain drivers for the vga
406 hsync and vsync signals. Opendrain drivers cannot generate steep enough
407 positive edges for a stable video output, so on boards with opendrain
408 drivers the sync signals must always be active high.
409
507e27df
CYT
410config VIDEO_VGA_EXTERNAL_DAC_EN
411 string "LCD panel power enable pin"
412 depends on VIDEO_VGA_VIA_LCD
413 default ""
414 ---help---
415 Set the enable pin for the external VGA DAC. This takes a string in the
416 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
417
2dae800f
HG
418config VIDEO_LCD_MODE
419 string "LCD panel timing details"
420 depends on VIDEO
421 default ""
422 ---help---
423 LCD panel timing details string, leave empty if there is no LCD panel.
424 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
425 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
426
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HG
427config VIDEO_LCD_DCLK_PHASE
428 int "LCD panel display clock phase"
429 depends on VIDEO
430 default 1
431 ---help---
432 Select LCD panel display clock phase shift, range 0-3.
433
2dae800f
HG
434config VIDEO_LCD_POWER
435 string "LCD panel power enable pin"
436 depends on VIDEO
437 default ""
438 ---help---
439 Set the power enable pin for the LCD panel. This takes a string in the
440 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
441
242e3d89
HG
442config VIDEO_LCD_RESET
443 string "LCD panel reset pin"
444 depends on VIDEO
445 default ""
446 ---help---
447 Set the reset pin for the LCD panel. This takes a string in the format
448 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
449
2dae800f
HG
450config VIDEO_LCD_BL_EN
451 string "LCD panel backlight enable pin"
452 depends on VIDEO
453 default ""
454 ---help---
455 Set the backlight enable pin for the LCD panel. This takes a string in the
456 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
457 port H.
458
459config VIDEO_LCD_BL_PWM
460 string "LCD panel backlight pwm pin"
461 depends on VIDEO
462 default ""
463 ---help---
464 Set the backlight pwm pin for the LCD panel. This takes a string in the
465 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
7f2c521f 466
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HG
467config VIDEO_LCD_BL_PWM_ACTIVE_LOW
468 bool "LCD panel backlight pwm is inverted"
469 depends on VIDEO
470 default y
471 ---help---
472 Set this if the backlight pwm output is active low.
473
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HG
474config VIDEO_LCD_PANEL_I2C
475 bool "LCD panel needs to be configured via i2c"
476 depends on VIDEO
1fc42018 477 default n
55410089
HG
478 ---help---
479 Say y here if the LCD panel needs to be configured via i2c. This
480 will add a bitbang i2c controller using gpios to talk to the LCD.
481
482config VIDEO_LCD_PANEL_I2C_SDA
483 string "LCD panel i2c interface SDA pin"
484 depends on VIDEO_LCD_PANEL_I2C
485 default "PG12"
486 ---help---
487 Set the SDA pin for the LCD i2c interface. This takes a string in the
488 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
489
490config VIDEO_LCD_PANEL_I2C_SCL
491 string "LCD panel i2c interface SCL pin"
492 depends on VIDEO_LCD_PANEL_I2C
493 default "PG10"
494 ---help---
495 Set the SCL pin for the LCD i2c interface. This takes a string in the
496 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
497
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HG
498
499# Note only one of these may be selected at a time! But hidden choices are
500# not supported by Kconfig
501config VIDEO_LCD_IF_PARALLEL
502 bool
503
504config VIDEO_LCD_IF_LVDS
505 bool
506
507
508choice
509 prompt "LCD panel support"
510 depends on VIDEO
511 ---help---
512 Select which type of LCD panel to support.
513
514config VIDEO_LCD_PANEL_PARALLEL
515 bool "Generic parallel interface LCD panel"
516 select VIDEO_LCD_IF_PARALLEL
517
518config VIDEO_LCD_PANEL_LVDS
519 bool "Generic lvds interface LCD panel"
520 select VIDEO_LCD_IF_LVDS
521
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SS
522config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
523 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
524 select VIDEO_LCD_SSD2828
525 select VIDEO_LCD_IF_PARALLEL
526 ---help---
527 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
528
27515b20
HG
529config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
530 bool "Hitachi tx18d42vm LCD panel"
531 select VIDEO_LCD_HITACHI_TX18D42VM
532 select VIDEO_LCD_IF_LVDS
533 ---help---
534 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
535
aad2ac24
HG
536config VIDEO_LCD_TL059WV5C0
537 bool "tl059wv5c0 LCD panel"
538 select VIDEO_LCD_PANEL_I2C
539 select VIDEO_LCD_IF_PARALLEL
540 ---help---
541 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
542 Aigo M60/M608/M606 tablets.
543
213480e1
HG
544endchoice
545
546
1a800f7a
HG
547config USB_MUSB_SUNXI
548 bool "Enable sunxi OTG / DRC USB controller in host mode"
549 default n
550 ---help---
551 Say y here to enable support for the sunxi OTG / DRC USB controller
552 used on almost all sunxi boards. Note currently u-boot can only have
553 one usb host controller enabled at a time, so enabling this on boards
554 which also use the ehci host controller will result in build errors.
555
86b49093
HG
556config USB_KEYBOARD
557 boolean "Enable USB keyboard support"
558 default y
559 ---help---
560 Say Y here to add support for using a USB keyboard (typically used
2dae800f 561 in combination with a graphical console).
86b49093 562
c13f60d9
HG
563config GMAC_TX_DELAY
564 int "GMAC Transmit Clock Delay Chain"
565 default 0
566 ---help---
567 Set the GMAC Transmit Clock Delay Chain value.
568
f9b08fbf
HG
569config SYS_MALLOC_CLEAR_ON_INIT
570 default n
571
b6006baf
HG
572config NETDEVICES
573 default y
574
575config DM_ETH
576 default y
577
578config DM_SERIAL
579 default y
580
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HG
581config DM_USB
582 default y if !USB_MUSB_SUNXI
583
277af820
HG
584config CMD_SETEXPR
585 default y
586
587config CMD_NET
588 default y
589
dd84058d 590endif