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sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCs
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CommitLineData
2c7e3b90
IC
1if ARCH_SUNXI
2
44d8ae5b
HG
3# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
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19choice
20 prompt "Sunxi SoC Variant"
21
c3be2793 22config MACH_SUN4I
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23 bool "sun4i (Allwinner A10)"
24 select CPU_V7
44d8ae5b 25 select SUNXI_GEN_SUN4I
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26 select SUPPORT_SPL
27
c3be2793 28config MACH_SUN5I
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29 bool "sun5i (Allwinner A13)"
30 select CPU_V7
44d8ae5b 31 select SUNXI_GEN_SUN4I
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32 select SUPPORT_SPL
33
c3be2793 34config MACH_SUN6I
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35 bool "sun6i (Allwinner A31)"
36 select CPU_V7
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CYT
37 select CPU_V7_HAS_NONSEC
38 select CPU_V7_HAS_VIRT
44d8ae5b 39 select SUNXI_GEN_SUN6I
8c2c9cfa 40 select SUPPORT_SPL
cc08ea4c 41 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 42
c3be2793 43config MACH_SUN7I
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44 bool "sun7i (Allwinner A20)"
45 select CPU_V7
ea624e19
HG
46 select CPU_V7_HAS_NONSEC
47 select CPU_V7_HAS_VIRT
44d8ae5b 48 select SUNXI_GEN_SUN4I
2c7e3b90 49 select SUPPORT_SPL
b366fb92 50 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 51
5e6bacdb 52config MACH_SUN8I_A23
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53 bool "sun8i (Allwinner A23)"
54 select CPU_V7
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55 select CPU_V7_HAS_NONSEC
56 select CPU_V7_HAS_VIRT
44d8ae5b 57 select SUNXI_GEN_SUN6I
08fd1479 58 select SUPPORT_SPL
014414f5 59 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 60
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VP
61config MACH_SUN8I_A33
62 bool "sun8i (Allwinner A33)"
63 select CPU_V7
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CYT
64 select CPU_V7_HAS_NONSEC
65 select CPU_V7_HAS_VIRT
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VP
66 select SUNXI_GEN_SUN6I
67 select SUPPORT_SPL
014414f5 68 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
8c3dacff 69
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70config MACH_SUN8I_A83T
71 bool "sun8i (Allwinner A83T)"
72 select CPU_V7
73 select SUNXI_GEN_SUN6I
74 select SUPPORT_SPL
75
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JK
76config MACH_SUN8I_H3
77 bool "sun8i (Allwinner H3)"
78 select CPU_V7
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CYT
79 select CPU_V7_HAS_NONSEC
80 select CPU_V7_HAS_VIRT
1c27b7dc 81 select SUNXI_GEN_SUN6I
0404d53f 82 select SUPPORT_SPL
853f6d1e 83 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
1c27b7dc 84
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85config MACH_SUN9I
86 bool "sun9i (Allwinner A80)"
87 select CPU_V7
88 select SUNXI_GEN_SUN6I
89
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CYT
90config MACH_SUN50I
91 bool "sun50i (Allwinner A64)"
92 select ARM64
93 select SUNXI_GEN_SUN6I
94
2c7e3b90 95endchoice
8a6564da 96
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HG
97# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
98config MACH_SUN8I
99 bool
762e24a0 100 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
5e6bacdb 101
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102config DRAM_TYPE
103 int "sunxi dram type"
104 depends on MACH_SUN8I_A83T
105 default 3
106 ---help---
107 Set the dram type, 3: DDR3, 7: LPDDR3
5e6bacdb 108
37781a1a 109config DRAM_CLK
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HG
110 int "sunxi dram clock speed"
111 default 312 if MACH_SUN6I || MACH_SUN8I
112 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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113 ---help---
114 Set the dram clock speed, valid range 240 - 480, must be a multiple
e1a0888e 115 of 24.
37781a1a 116
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SS
117if MACH_SUN5I || MACH_SUN7I
118config DRAM_MBUS_CLK
119 int "sunxi mbus clock speed"
120 default 300
121 ---help---
122 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
123
124endif
125
37781a1a 126config DRAM_ZQ
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127 int "sunxi dram zq value"
128 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
129 default 127 if MACH_SUN7I
37781a1a 130 ---help---
e1a0888e 131 Set the dram zq value.
8ffc487c 132
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133config DRAM_ODT_EN
134 bool "sunxi dram odt enable"
135 default n if !MACH_SUN8I_A23
136 default y if MACH_SUN8I_A23
137 ---help---
138 Select this to enable dram odt (on die termination).
139
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HG
140if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
141config DRAM_EMR1
142 int "sunxi dram emr1 value"
143 default 0 if MACH_SUN4I
144 default 4 if MACH_SUN5I || MACH_SUN7I
145 ---help---
e1a0888e 146 Set the dram controller emr1 value.
d133647a 147
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SS
148config DRAM_TPR3
149 hex "sunxi dram tpr3 value"
150 default 0
151 ---help---
152 Set the dram controller tpr3 parameter. This parameter configures
153 the delay on the command lane and also phase shifts, which are
154 applied for sampling incoming read data. The default value 0
155 means that no phase/delay adjustments are necessary. Properly
156 configuring this parameter increases reliability at high DRAM
157 clock speeds.
158
159config DRAM_DQS_GATING_DELAY
160 hex "sunxi dram dqs_gating_delay value"
161 default 0
162 ---help---
163 Set the dram controller dqs_gating_delay parmeter. Each byte
164 encodes the DQS gating delay for each byte lane. The delay
165 granularity is 1/4 cycle. For example, the value 0x05060606
166 means that the delay is 5 quarter-cycles for one lane (1.25
167 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
168 The default value 0 means autodetection. The results of hardware
169 autodetection are not very reliable and depend on the chip
170 temperature (sometimes producing different results on cold start
171 and warm reboot). But the accuracy of hardware autodetection
172 is usually good enough, unless running at really high DRAM
173 clocks speeds (up to 600MHz). If unsure, keep as 0.
174
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SS
175choice
176 prompt "sunxi dram timings"
177 default DRAM_TIMINGS_VENDOR_MAGIC
178 ---help---
179 Select the timings of the DDR3 chips.
180
181config DRAM_TIMINGS_VENDOR_MAGIC
182 bool "Magic vendor timings from Android"
183 ---help---
184 The same DRAM timings as in the Allwinner boot0 bootloader.
185
186config DRAM_TIMINGS_DDR3_1066F_1333H
187 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
188 ---help---
189 Use the timings of the standard JEDEC DDR3-1066F speed bin for
190 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
191 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
192 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
193 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
194 that down binning to DDR3-1066F is supported (because DDR3-1066F
195 uses a bit faster timings than DDR3-1333H).
196
197config DRAM_TIMINGS_DDR3_800E_1066G_1333J
198 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
199 ---help---
200 Use the timings of the slowest possible JEDEC speed bin for the
201 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
202 DDR3-800E, DDR3-1066G or DDR3-1333J.
203
204endchoice
205
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HG
206endif
207
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HG
208if MACH_SUN8I_A23
209config DRAM_ODT_CORRECTION
210 int "sunxi dram odt correction value"
211 default 0
212 ---help---
213 Set the dram odt correction value (range -255 - 255). In allwinner
214 fex files, this option is found in bits 8-15 of the u32 odt_en variable
215 in the [dram] section. When bit 31 of the odt_en variable is set
216 then the correction is negative. Usually the value for this is 0.
217endif
218
e71b422b 219config SYS_CLK_FREQ
d96ebc46 220 default 816000000 if MACH_SUN50I
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IP
221 default 912000000 if MACH_SUN7I
222 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
223
8a6564da 224config SYS_CONFIG_NAME
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225 default "sun4i" if MACH_SUN4I
226 default "sun5i" if MACH_SUN5I
227 default "sun6i" if MACH_SUN6I
228 default "sun7i" if MACH_SUN7I
229 default "sun8i" if MACH_SUN8I
1871a8ca 230 default "sun9i" if MACH_SUN9I
d96ebc46 231 default "sun50i" if MACH_SUN50I
dd84058d 232
dd84058d 233config SYS_BOARD
dd84058d
MY
234 default "sunxi"
235
236config SYS_SOC
dd84058d
MY
237 default "sunxi"
238
f0ce28e9
SS
239config UART0_PORT_F
240 bool "UART0 on MicroSD breakout board"
f0ce28e9
SS
241 default n
242 ---help---
243 Repurpose the SD card slot for getting access to the UART0 serial
244 console. Primarily useful only for low level u-boot debugging on
245 tablets, where normal UART0 is difficult to access and requires
246 device disassembly and/or soldering. As the SD card can't be used
247 at the same time, the system can be only booted in the FEL mode.
248 Only enable this if you really know what you are doing.
249
accc9e44
HG
250config OLD_SUNXI_KERNEL_COMPAT
251 boolean "Enable workarounds for booting old kernels"
252 default n
253 ---help---
254 Set this to enable various workarounds for old kernels, this results in
255 sub-optimal settings for newer kernels, only enable if needed.
256
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MR
257config MMC
258 depends on !UART0_PORT_F
259 default y if ARCH_SUNXI
260
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HG
261config MMC0_CD_PIN
262 string "Card detect pin for mmc0"
acdab175 263 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
cd82113a
HG
264 default ""
265 ---help---
266 Set the card detect pin for mmc0, leave empty to not use cd. This
267 takes a string in the format understood by sunxi_name_to_gpio, e.g.
268 PH1 for pin 1 of port H.
269
270config MMC1_CD_PIN
271 string "Card detect pin for mmc1"
272 default ""
273 ---help---
274 See MMC0_CD_PIN help text.
275
276config MMC2_CD_PIN
277 string "Card detect pin for mmc2"
278 default ""
279 ---help---
280 See MMC0_CD_PIN help text.
281
282config MMC3_CD_PIN
283 string "Card detect pin for mmc3"
284 default ""
285 ---help---
286 See MMC0_CD_PIN help text.
287
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PK
288config MMC1_PINS
289 string "Pins for mmc1"
290 default ""
291 ---help---
292 Set the pins used for mmc1, when applicable. This takes a string in the
293 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
294
295config MMC2_PINS
296 string "Pins for mmc2"
297 default ""
298 ---help---
299 See MMC1_PINS help text.
300
301config MMC3_PINS
302 string "Pins for mmc3"
303 default ""
304 ---help---
305 See MMC1_PINS help text.
306
2ccfac01
HG
307config MMC_SUNXI_SLOT_EXTRA
308 int "mmc extra slot number"
309 default -1
310 ---help---
311 sunxi builds always enable mmc0, some boards also have a second sdcard
312 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
313 support for this.
314
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HG
315config INITIAL_USB_SCAN_DELAY
316 int "delay initial usb scan by x ms to allow builtin devices to init"
317 default 0
318 ---help---
319 Some boards have on board usb devices which need longer than the
320 USB spec's 1 second to connect from board powerup. Set this config
321 option to a non 0 value to add an extra delay before the first usb
322 bus scan.
323
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HG
324config USB0_VBUS_PIN
325 string "Vbus enable pin for usb0 (otg)"
326 default ""
327 ---help---
328 Set the Vbus enable pin for usb0 (otg). This takes a string in the
329 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
330
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HG
331config USB0_VBUS_DET
332 string "Vbus detect pin for usb0 (otg)"
52defe8f
HG
333 default ""
334 ---help---
335 Set the Vbus detect pin for usb0 (otg). This takes a string in the
336 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
337
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HG
338config USB0_ID_DET
339 string "ID detect pin for usb0 (otg)"
340 default ""
341 ---help---
342 Set the ID detect pin for usb0 (otg). This takes a string in the
343 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
344
115200ce
HG
345config USB1_VBUS_PIN
346 string "Vbus enable pin for usb1 (ehci0)"
347 default "PH6" if MACH_SUN4I || MACH_SUN7I
76946dfe 348 default "PH27" if MACH_SUN6I
115200ce
HG
349 ---help---
350 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
351 a string in the format understood by sunxi_name_to_gpio, e.g.
352 PH1 for pin 1 of port H.
353
354config USB2_VBUS_PIN
355 string "Vbus enable pin for usb2 (ehci1)"
356 default "PH3" if MACH_SUN4I || MACH_SUN7I
76946dfe 357 default "PH24" if MACH_SUN6I
115200ce
HG
358 ---help---
359 See USB1_VBUS_PIN help text.
360
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HG
361config USB3_VBUS_PIN
362 string "Vbus enable pin for usb3 (ehci2)"
363 default ""
364 ---help---
365 See USB1_VBUS_PIN help text.
366
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PK
367config I2C0_ENABLE
368 bool "Enable I2C/TWI controller 0"
369 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
370 default n if MACH_SUN6I || MACH_SUN8I
371 ---help---
372 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
373 its clock and setting up the bus. This is especially useful on devices
374 with slaves connected to the bus or with pins exposed through e.g. an
375 expansion port/header.
376
377config I2C1_ENABLE
378 bool "Enable I2C/TWI controller 1"
379 default n
380 ---help---
381 See I2C0_ENABLE help text.
382
383config I2C2_ENABLE
384 bool "Enable I2C/TWI controller 2"
385 default n
386 ---help---
387 See I2C0_ENABLE help text.
388
389if MACH_SUN6I || MACH_SUN7I
390config I2C3_ENABLE
391 bool "Enable I2C/TWI controller 3"
392 default n
393 ---help---
394 See I2C0_ENABLE help text.
395endif
396
0d8382ae 397if SUNXI_GEN_SUN6I
9d082687
JW
398config R_I2C_ENABLE
399 bool "Enable the PRCM I2C/TWI controller"
0d8382ae
JW
400 # This is used for the pmic on H3
401 default y if SY8106A_POWER
9d082687
JW
402 ---help---
403 Set this to y to enable the I2C controller which is part of the PRCM.
0d8382ae 404endif
9d082687 405
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PK
406if MACH_SUN7I
407config I2C4_ENABLE
408 bool "Enable I2C/TWI controller 4"
409 default n
410 ---help---
411 See I2C0_ENABLE help text.
412endif
413
2fcf033d
HG
414config AXP_GPIO
415 boolean "Enable support for gpio-s on axp PMICs"
416 default n
417 ---help---
418 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
419
7f2c521f 420config VIDEO
2dae800f 421 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
762e24a0 422 depends on !MACH_SUN8I_A83T
7f2c521f
LV
423 default y
424 ---help---
2dae800f
HG
425 Say Y here to add support for using a cfb console on the HDMI, LCD
426 or VGA output found on most sunxi devices. See doc/README.video for
427 info on how to select the video output and mode.
428
2fbf091a
HG
429config VIDEO_HDMI
430 boolean "HDMI output support"
431 depends on VIDEO && !MACH_SUN8I
432 default y
433 ---help---
434 Say Y here to add support for outputting video over HDMI.
435
d9786d23
HG
436config VIDEO_VGA
437 boolean "VGA output support"
438 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
439 default n
440 ---help---
441 Say Y here to add support for outputting video over VGA.
442
e2bbdfb1
HG
443config VIDEO_VGA_VIA_LCD
444 boolean "VGA via LCD controller support"
2583d5b1 445 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
e2bbdfb1
HG
446 default n
447 ---help---
448 Say Y here to add support for external DACs connected to the parallel
449 LCD interface driving a VGA connector, such as found on the
450 Olimex A13 boards.
451
fb75d972
HG
452config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
453 boolean "Force sync active high for VGA via LCD controller support"
454 depends on VIDEO_VGA_VIA_LCD
455 default n
456 ---help---
457 Say Y here if you've a board which uses opendrain drivers for the vga
458 hsync and vsync signals. Opendrain drivers cannot generate steep enough
459 positive edges for a stable video output, so on boards with opendrain
460 drivers the sync signals must always be active high.
461
507e27df
CYT
462config VIDEO_VGA_EXTERNAL_DAC_EN
463 string "LCD panel power enable pin"
464 depends on VIDEO_VGA_VIA_LCD
465 default ""
466 ---help---
467 Set the enable pin for the external VGA DAC. This takes a string in the
468 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
469
39920c81
HG
470config VIDEO_COMPOSITE
471 boolean "Composite video output support"
472 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
473 default n
474 ---help---
475 Say Y here to add support for outputting composite video.
476
2dae800f
HG
477config VIDEO_LCD_MODE
478 string "LCD panel timing details"
479 depends on VIDEO
480 default ""
481 ---help---
482 LCD panel timing details string, leave empty if there is no LCD panel.
483 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
484 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
8addd3ed 485 Also see: http://linux-sunxi.org/LCD
2dae800f 486
6515032e
HG
487config VIDEO_LCD_DCLK_PHASE
488 int "LCD panel display clock phase"
489 depends on VIDEO
490 default 1
491 ---help---
492 Select LCD panel display clock phase shift, range 0-3.
493
2dae800f
HG
494config VIDEO_LCD_POWER
495 string "LCD panel power enable pin"
496 depends on VIDEO
497 default ""
498 ---help---
499 Set the power enable pin for the LCD panel. This takes a string in the
500 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
501
242e3d89
HG
502config VIDEO_LCD_RESET
503 string "LCD panel reset pin"
504 depends on VIDEO
505 default ""
506 ---help---
507 Set the reset pin for the LCD panel. This takes a string in the format
508 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
509
2dae800f
HG
510config VIDEO_LCD_BL_EN
511 string "LCD panel backlight enable pin"
512 depends on VIDEO
513 default ""
514 ---help---
515 Set the backlight enable pin for the LCD panel. This takes a string in the
516 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
517 port H.
518
519config VIDEO_LCD_BL_PWM
520 string "LCD panel backlight pwm pin"
521 depends on VIDEO
522 default ""
523 ---help---
524 Set the backlight pwm pin for the LCD panel. This takes a string in the
525 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
7f2c521f 526
a7403ae8
HG
527config VIDEO_LCD_BL_PWM_ACTIVE_LOW
528 bool "LCD panel backlight pwm is inverted"
529 depends on VIDEO
530 default y
531 ---help---
532 Set this if the backlight pwm output is active low.
533
55410089
HG
534config VIDEO_LCD_PANEL_I2C
535 bool "LCD panel needs to be configured via i2c"
536 depends on VIDEO
1fc42018 537 default n
55410089
HG
538 ---help---
539 Say y here if the LCD panel needs to be configured via i2c. This
540 will add a bitbang i2c controller using gpios to talk to the LCD.
541
542config VIDEO_LCD_PANEL_I2C_SDA
543 string "LCD panel i2c interface SDA pin"
544 depends on VIDEO_LCD_PANEL_I2C
545 default "PG12"
546 ---help---
547 Set the SDA pin for the LCD i2c interface. This takes a string in the
548 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
549
550config VIDEO_LCD_PANEL_I2C_SCL
551 string "LCD panel i2c interface SCL pin"
552 depends on VIDEO_LCD_PANEL_I2C
553 default "PG10"
554 ---help---
555 Set the SCL pin for the LCD i2c interface. This takes a string in the
556 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
557
213480e1
HG
558
559# Note only one of these may be selected at a time! But hidden choices are
560# not supported by Kconfig
561config VIDEO_LCD_IF_PARALLEL
562 bool
563
564config VIDEO_LCD_IF_LVDS
565 bool
566
567
568choice
569 prompt "LCD panel support"
570 depends on VIDEO
571 ---help---
572 Select which type of LCD panel to support.
573
574config VIDEO_LCD_PANEL_PARALLEL
575 bool "Generic parallel interface LCD panel"
576 select VIDEO_LCD_IF_PARALLEL
577
578config VIDEO_LCD_PANEL_LVDS
579 bool "Generic lvds interface LCD panel"
580 select VIDEO_LCD_IF_LVDS
581
97ece830
SS
582config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
583 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
584 select VIDEO_LCD_SSD2828
585 select VIDEO_LCD_IF_PARALLEL
586 ---help---
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587 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
588
589config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
590 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
591 select VIDEO_LCD_ANX9804
592 select VIDEO_LCD_IF_PARALLEL
593 select VIDEO_LCD_PANEL_I2C
594 ---help---
595 Select this for eDP LCD panels with 4 lanes running at 1.62G,
596 connected via an ANX9804 bridge chip.
97ece830 597
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598config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
599 bool "Hitachi tx18d42vm LCD panel"
600 select VIDEO_LCD_HITACHI_TX18D42VM
601 select VIDEO_LCD_IF_LVDS
602 ---help---
603 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
604
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605config VIDEO_LCD_TL059WV5C0
606 bool "tl059wv5c0 LCD panel"
607 select VIDEO_LCD_PANEL_I2C
608 select VIDEO_LCD_IF_PARALLEL
609 ---help---
610 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
611 Aigo M60/M608/M606 tablets.
612
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613endchoice
614
615
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616config GMAC_TX_DELAY
617 int "GMAC Transmit Clock Delay Chain"
618 default 0
619 ---help---
620 Set the GMAC Transmit Clock Delay Chain value.
621
ff42d107 622config SPL_STACK_R_ADDR
d96ebc46 623 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
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624 default 0x2fe00000 if MACH_SUN9I
625
dd84058d 626endif