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cba69eee IC |
1 | /* |
2 | * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> | |
4 | * | |
5 | * (C) Copyright 2007-2011 | |
6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
7 | * Tom Cubie <tangliang@allwinnertech.com> | |
8 | * | |
9 | * Some board init for the Allwinner A10-evb board. | |
10 | * | |
11 | * SPDX-License-Identifier: GPL-2.0+ | |
12 | */ | |
13 | ||
14 | #include <common.h> | |
e79c7c88 | 15 | #include <mmc.h> |
6944aff1 | 16 | #include <axp_pmic.h> |
cba69eee | 17 | #include <asm/arch/clock.h> |
b41d7d05 | 18 | #include <asm/arch/cpu.h> |
2d7a084b | 19 | #include <asm/arch/display.h> |
cba69eee | 20 | #include <asm/arch/dram.h> |
e24ea55c IC |
21 | #include <asm/arch/gpio.h> |
22 | #include <asm/arch/mmc.h> | |
4a8c7c1f | 23 | #include <asm/arch/spl.h> |
2aacc423 | 24 | #include <asm/arch/usb_phy.h> |
d96ebc46 SS |
25 | #ifndef CONFIG_ARM64 |
26 | #include <asm/armv7.h> | |
27 | #endif | |
4f7e01c9 | 28 | #include <asm/gpio.h> |
b41d7d05 | 29 | #include <asm/io.h> |
3f8ea3b0 | 30 | #include <crc.h> |
4a8c7c1f | 31 | #include <environment.h> |
f221961e | 32 | #include <libfdt.h> |
f62bfa56 | 33 | #include <nand.h> |
b41d7d05 | 34 | #include <net.h> |
0d8382ae | 35 | #include <sy8106a.h> |
cba69eee | 36 | |
55410089 HG |
37 | #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) |
38 | /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ | |
39 | int soft_i2c_gpio_sda; | |
40 | int soft_i2c_gpio_scl; | |
4f7e01c9 HG |
41 | |
42 | static int soft_i2c_board_init(void) | |
43 | { | |
44 | int ret; | |
45 | ||
46 | soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); | |
47 | if (soft_i2c_gpio_sda < 0) { | |
48 | printf("Error invalid soft i2c sda pin: '%s', err %d\n", | |
49 | CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); | |
50 | return soft_i2c_gpio_sda; | |
51 | } | |
52 | ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); | |
53 | if (ret) { | |
54 | printf("Error requesting soft i2c sda pin: '%s', err %d\n", | |
55 | CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); | |
56 | return ret; | |
57 | } | |
58 | ||
59 | soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); | |
60 | if (soft_i2c_gpio_scl < 0) { | |
61 | printf("Error invalid soft i2c scl pin: '%s', err %d\n", | |
62 | CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); | |
63 | return soft_i2c_gpio_scl; | |
64 | } | |
65 | ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); | |
66 | if (ret) { | |
67 | printf("Error requesting soft i2c scl pin: '%s', err %d\n", | |
68 | CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); | |
69 | return ret; | |
70 | } | |
71 | ||
72 | return 0; | |
73 | } | |
74 | #else | |
75 | static int soft_i2c_board_init(void) { return 0; } | |
55410089 HG |
76 | #endif |
77 | ||
cba69eee IC |
78 | DECLARE_GLOBAL_DATA_PTR; |
79 | ||
80 | /* add board specific code here */ | |
81 | int board_init(void) | |
82 | { | |
d96ebc46 | 83 | __maybe_unused int id_pfr1, ret; |
cba69eee IC |
84 | |
85 | gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); | |
86 | ||
d96ebc46 | 87 | #ifndef CONFIG_ARM64 |
cba69eee IC |
88 | asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); |
89 | debug("id_pfr1: 0x%08x\n", id_pfr1); | |
90 | /* Generic Timer Extension available? */ | |
d96ebc46 SS |
91 | if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { |
92 | uint32_t freq; | |
93 | ||
cba69eee | 94 | debug("Setting CNTFRQ\n"); |
d96ebc46 SS |
95 | |
96 | /* | |
97 | * CNTFRQ is a secure register, so we will crash if we try to | |
98 | * write this from the non-secure world (read is OK, though). | |
99 | * In case some bootcode has already set the correct value, | |
100 | * we avoid the risk of writing to it. | |
101 | */ | |
102 | asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); | |
103 | if (freq != CONFIG_TIMER_CLK_FREQ) { | |
104 | debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", | |
105 | freq, CONFIG_TIMER_CLK_FREQ); | |
106 | #ifdef CONFIG_NON_SECURE | |
107 | printf("arch timer frequency is wrong, but cannot adjust it\n"); | |
108 | #else | |
109 | asm volatile("mcr p15, 0, %0, c14, c0, 0" | |
110 | : : "r"(CONFIG_TIMER_CLK_FREQ)); | |
111 | #endif | |
112 | } | |
cba69eee | 113 | } |
d96ebc46 | 114 | #endif /* !CONFIG_ARM64 */ |
cba69eee | 115 | |
2fcf033d HG |
116 | ret = axp_gpio_init(); |
117 | if (ret) | |
118 | return ret; | |
119 | ||
9fbb0c3a HG |
120 | #ifdef CONFIG_SATAPWR |
121 | gpio_request(CONFIG_SATAPWR, "satapwr"); | |
122 | gpio_direction_output(CONFIG_SATAPWR, 1); | |
123 | #endif | |
fc8991c6 HG |
124 | #ifdef CONFIG_MACPWR |
125 | gpio_request(CONFIG_MACPWR, "macpwr"); | |
126 | gpio_direction_output(CONFIG_MACPWR, 1); | |
127 | #endif | |
128 | ||
4f7e01c9 HG |
129 | /* Uses dm gpio code so do this here and not in i2c_init_board() */ |
130 | return soft_i2c_board_init(); | |
cba69eee IC |
131 | } |
132 | ||
133 | int dram_init(void) | |
134 | { | |
135 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
4ccae81c | 140 | #if defined(CONFIG_NAND_SUNXI) |
ad008299 KG |
141 | static void nand_pinmux_setup(void) |
142 | { | |
143 | unsigned int pin; | |
ad008299 | 144 | |
022a99d8 | 145 | for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) |
ad008299 KG |
146 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); |
147 | ||
022a99d8 HG |
148 | #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I |
149 | for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) | |
150 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); | |
151 | #endif | |
152 | /* sun4i / sun7i do have a PC23, but it is not used for nand, | |
153 | * only sun7i has a PC24 */ | |
154 | #ifdef CONFIG_MACH_SUN7I | |
ad008299 | 155 | sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); |
022a99d8 | 156 | #endif |
ad008299 KG |
157 | } |
158 | ||
159 | static void nand_clock_setup(void) | |
160 | { | |
161 | struct sunxi_ccm_reg *const ccm = | |
162 | (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; | |
31c21471 | 163 | |
ad008299 | 164 | setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); |
31c21471 HG |
165 | #ifdef CONFIG_MACH_SUN9I |
166 | setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); | |
167 | #else | |
168 | setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); | |
169 | #endif | |
ad008299 KG |
170 | setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); |
171 | } | |
f62bfa56 HG |
172 | |
173 | void board_nand_init(void) | |
174 | { | |
175 | nand_pinmux_setup(); | |
176 | nand_clock_setup(); | |
4ccae81c BB |
177 | #ifndef CONFIG_SPL_BUILD |
178 | sunxi_nand_init(); | |
179 | #endif | |
f62bfa56 | 180 | } |
ad008299 KG |
181 | #endif |
182 | ||
e24ea55c IC |
183 | #ifdef CONFIG_GENERIC_MMC |
184 | static void mmc_pinmux_setup(int sdc) | |
185 | { | |
186 | unsigned int pin; | |
8deacca9 | 187 | __maybe_unused int pins; |
e24ea55c IC |
188 | |
189 | switch (sdc) { | |
190 | case 0: | |
8deacca9 | 191 | /* SDC0: PF0-PF5 */ |
e24ea55c | 192 | for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { |
487b3277 | 193 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); |
e24ea55c IC |
194 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); |
195 | sunxi_gpio_set_drv(pin, 2); | |
196 | } | |
197 | break; | |
198 | ||
199 | case 1: | |
8deacca9 PK |
200 | pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); |
201 | ||
202 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
203 | if (pins == SUNXI_GPIO_H) { | |
204 | /* SDC1: PH22-PH-27 */ | |
205 | for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { | |
206 | sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); | |
207 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
208 | sunxi_gpio_set_drv(pin, 2); | |
209 | } | |
210 | } else { | |
211 | /* SDC1: PG0-PG5 */ | |
212 | for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { | |
213 | sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); | |
214 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
215 | sunxi_gpio_set_drv(pin, 2); | |
216 | } | |
217 | } | |
218 | #elif defined(CONFIG_MACH_SUN5I) | |
219 | /* SDC1: PG3-PG8 */ | |
bbff84b3 | 220 | for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { |
487b3277 | 221 | sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); |
e24ea55c IC |
222 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); |
223 | sunxi_gpio_set_drv(pin, 2); | |
224 | } | |
8deacca9 PK |
225 | #elif defined(CONFIG_MACH_SUN6I) |
226 | /* SDC1: PG0-PG5 */ | |
227 | for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { | |
228 | sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); | |
229 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
230 | sunxi_gpio_set_drv(pin, 2); | |
231 | } | |
232 | #elif defined(CONFIG_MACH_SUN8I) | |
233 | if (pins == SUNXI_GPIO_D) { | |
234 | /* SDC1: PD2-PD7 */ | |
235 | for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { | |
236 | sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); | |
237 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
238 | sunxi_gpio_set_drv(pin, 2); | |
239 | } | |
240 | } else { | |
241 | /* SDC1: PG0-PG5 */ | |
242 | for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { | |
243 | sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); | |
244 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
245 | sunxi_gpio_set_drv(pin, 2); | |
246 | } | |
247 | } | |
248 | #endif | |
e24ea55c IC |
249 | break; |
250 | ||
251 | case 2: | |
8deacca9 PK |
252 | pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); |
253 | ||
254 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
255 | /* SDC2: PC6-PC11 */ | |
e24ea55c | 256 | for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { |
487b3277 | 257 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); |
e24ea55c IC |
258 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); |
259 | sunxi_gpio_set_drv(pin, 2); | |
260 | } | |
8deacca9 PK |
261 | #elif defined(CONFIG_MACH_SUN5I) |
262 | if (pins == SUNXI_GPIO_E) { | |
263 | /* SDC2: PE4-PE9 */ | |
264 | for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { | |
265 | sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); | |
266 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
267 | sunxi_gpio_set_drv(pin, 2); | |
268 | } | |
269 | } else { | |
270 | /* SDC2: PC6-PC15 */ | |
271 | for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { | |
272 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); | |
273 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
274 | sunxi_gpio_set_drv(pin, 2); | |
275 | } | |
276 | } | |
277 | #elif defined(CONFIG_MACH_SUN6I) | |
278 | if (pins == SUNXI_GPIO_A) { | |
279 | /* SDC2: PA9-PA14 */ | |
280 | for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { | |
281 | sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); | |
282 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
283 | sunxi_gpio_set_drv(pin, 2); | |
284 | } | |
285 | } else { | |
286 | /* SDC2: PC6-PC15, PC24 */ | |
287 | for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { | |
288 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); | |
289 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
290 | sunxi_gpio_set_drv(pin, 2); | |
291 | } | |
292 | ||
293 | sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); | |
294 | sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); | |
295 | sunxi_gpio_set_drv(SUNXI_GPC(24), 2); | |
296 | } | |
d96ebc46 | 297 | #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) |
8deacca9 PK |
298 | /* SDC2: PC5-PC6, PC8-PC16 */ |
299 | for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { | |
300 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); | |
301 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
302 | sunxi_gpio_set_drv(pin, 2); | |
303 | } | |
304 | ||
305 | for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { | |
306 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); | |
307 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
308 | sunxi_gpio_set_drv(pin, 2); | |
309 | } | |
3ebb4567 PT |
310 | #elif defined(CONFIG_MACH_SUN9I) |
311 | /* SDC2: PC6-PC16 */ | |
312 | for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { | |
313 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); | |
314 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
315 | sunxi_gpio_set_drv(pin, 2); | |
316 | } | |
8deacca9 | 317 | #endif |
e24ea55c IC |
318 | break; |
319 | ||
320 | case 3: | |
8deacca9 PK |
321 | pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); |
322 | ||
323 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
324 | /* SDC3: PI4-PI9 */ | |
e24ea55c | 325 | for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { |
8deacca9 | 326 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); |
e24ea55c IC |
327 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); |
328 | sunxi_gpio_set_drv(pin, 2); | |
329 | } | |
8deacca9 PK |
330 | #elif defined(CONFIG_MACH_SUN6I) |
331 | if (pins == SUNXI_GPIO_A) { | |
332 | /* SDC3: PA9-PA14 */ | |
333 | for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { | |
334 | sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); | |
335 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
336 | sunxi_gpio_set_drv(pin, 2); | |
337 | } | |
338 | } else { | |
339 | /* SDC3: PC6-PC15, PC24 */ | |
340 | for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { | |
341 | sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); | |
342 | sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); | |
343 | sunxi_gpio_set_drv(pin, 2); | |
344 | } | |
345 | ||
346 | sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); | |
347 | sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); | |
348 | sunxi_gpio_set_drv(SUNXI_GPC(24), 2); | |
349 | } | |
350 | #endif | |
e24ea55c IC |
351 | break; |
352 | ||
353 | default: | |
354 | printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); | |
355 | break; | |
356 | } | |
357 | } | |
358 | ||
359 | int board_mmc_init(bd_t *bis) | |
360 | { | |
e79c7c88 HG |
361 | __maybe_unused struct mmc *mmc0, *mmc1; |
362 | __maybe_unused char buf[512]; | |
363 | ||
e24ea55c | 364 | mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); |
e79c7c88 HG |
365 | mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); |
366 | if (!mmc0) | |
367 | return -1; | |
368 | ||
2ccfac01 | 369 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
e24ea55c | 370 | mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); |
e79c7c88 HG |
371 | mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); |
372 | if (!mmc1) | |
373 | return -1; | |
374 | #endif | |
375 | ||
bf5b9b10 | 376 | #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 |
e79c7c88 | 377 | /* |
bf5b9b10 DK |
378 | * On systems with an emmc (mmc2), figure out if we are booting from |
379 | * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. | |
380 | * are searched there first. Note we only do this for u-boot proper, | |
381 | * not for the SPL, see spl_boot_device(). | |
e79c7c88 | 382 | */ |
ef36d9ae | 383 | if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { |
bf5b9b10 | 384 | /* Booting from emmc / mmc2, swap */ |
bcce53d0 SG |
385 | mmc0->block_dev.devnum = 1; |
386 | mmc1->block_dev.devnum = 0; | |
bf5b9b10 | 387 | } |
e24ea55c IC |
388 | #endif |
389 | ||
390 | return 0; | |
391 | } | |
392 | #endif | |
393 | ||
6620377e HG |
394 | void i2c_init_board(void) |
395 | { | |
6c739c5d PK |
396 | #ifdef CONFIG_I2C0_ENABLE |
397 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) | |
398 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); | |
399 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); | |
6620377e | 400 | clock_twi_onoff(0, 1); |
6c739c5d PK |
401 | #elif defined(CONFIG_MACH_SUN6I) |
402 | sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); | |
403 | sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); | |
404 | clock_twi_onoff(0, 1); | |
405 | #elif defined(CONFIG_MACH_SUN8I) | |
406 | sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); | |
407 | sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); | |
408 | clock_twi_onoff(0, 1); | |
409 | #endif | |
410 | #endif | |
411 | ||
412 | #ifdef CONFIG_I2C1_ENABLE | |
413 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
414 | sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); | |
415 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); | |
416 | clock_twi_onoff(1, 1); | |
417 | #elif defined(CONFIG_MACH_SUN5I) | |
418 | sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); | |
419 | sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); | |
420 | clock_twi_onoff(1, 1); | |
421 | #elif defined(CONFIG_MACH_SUN6I) | |
422 | sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); | |
423 | sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); | |
424 | clock_twi_onoff(1, 1); | |
425 | #elif defined(CONFIG_MACH_SUN8I) | |
426 | sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); | |
427 | sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); | |
428 | clock_twi_onoff(1, 1); | |
429 | #endif | |
430 | #endif | |
431 | ||
432 | #ifdef CONFIG_I2C2_ENABLE | |
433 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
434 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); | |
435 | sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); | |
436 | clock_twi_onoff(2, 1); | |
437 | #elif defined(CONFIG_MACH_SUN5I) | |
438 | sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); | |
439 | sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); | |
440 | clock_twi_onoff(2, 1); | |
441 | #elif defined(CONFIG_MACH_SUN6I) | |
442 | sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); | |
443 | sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); | |
444 | clock_twi_onoff(2, 1); | |
445 | #elif defined(CONFIG_MACH_SUN8I) | |
446 | sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); | |
447 | sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); | |
448 | clock_twi_onoff(2, 1); | |
449 | #endif | |
450 | #endif | |
451 | ||
452 | #ifdef CONFIG_I2C3_ENABLE | |
453 | #if defined(CONFIG_MACH_SUN6I) | |
454 | sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); | |
455 | sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); | |
456 | clock_twi_onoff(3, 1); | |
457 | #elif defined(CONFIG_MACH_SUN7I) | |
458 | sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); | |
459 | sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); | |
460 | clock_twi_onoff(3, 1); | |
461 | #endif | |
462 | #endif | |
463 | ||
464 | #ifdef CONFIG_I2C4_ENABLE | |
465 | #if defined(CONFIG_MACH_SUN7I) | |
466 | sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); | |
467 | sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); | |
468 | clock_twi_onoff(4, 1); | |
469 | #endif | |
470 | #endif | |
9d082687 JW |
471 | |
472 | #ifdef CONFIG_R_I2C_ENABLE | |
473 | clock_twi_onoff(5, 1); | |
474 | sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); | |
475 | sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); | |
476 | #endif | |
6620377e HG |
477 | } |
478 | ||
cba69eee IC |
479 | #ifdef CONFIG_SPL_BUILD |
480 | void sunxi_board_init(void) | |
481 | { | |
14bc66bd | 482 | int power_failed = 0; |
cba69eee IC |
483 | unsigned long ramsize; |
484 | ||
0d8382ae JW |
485 | #ifdef CONFIG_SY8106A_POWER |
486 | power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); | |
487 | #endif | |
488 | ||
95ab8fee | 489 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ |
795857df CYT |
490 | defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ |
491 | defined CONFIG_AXP818_POWER | |
6944aff1 HG |
492 | power_failed = axp_init(); |
493 | ||
795857df CYT |
494 | #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ |
495 | defined CONFIG_AXP818_POWER | |
6944aff1 | 496 | power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); |
24289208 | 497 | #endif |
6944aff1 HG |
498 | power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); |
499 | power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); | |
95ab8fee | 500 | #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) |
6944aff1 | 501 | power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); |
5c7f10fd | 502 | #endif |
795857df CYT |
503 | #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ |
504 | defined CONFIG_AXP818_POWER | |
6944aff1 | 505 | power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); |
14bc66bd HN |
506 | #endif |
507 | ||
795857df CYT |
508 | #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ |
509 | defined CONFIG_AXP818_POWER | |
6944aff1 HG |
510 | power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); |
511 | #endif | |
512 | power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); | |
f3c5045a | 513 | #if !defined(CONFIG_AXP152_POWER) |
6944aff1 HG |
514 | power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); |
515 | #endif | |
516 | #ifdef CONFIG_AXP209_POWER | |
517 | power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); | |
518 | #endif | |
519 | ||
795857df CYT |
520 | #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ |
521 | defined(CONFIG_AXP818_POWER) | |
3517a27d CYT |
522 | power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); |
523 | power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); | |
795857df | 524 | #if !defined CONFIG_AXP809_POWER |
3517a27d CYT |
525 | power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); |
526 | power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); | |
795857df | 527 | #endif |
6944aff1 HG |
528 | power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); |
529 | power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); | |
530 | power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); | |
531 | #endif | |
38491d9c CYT |
532 | |
533 | #ifdef CONFIG_AXP818_POWER | |
534 | power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); | |
535 | power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); | |
536 | power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); | |
795857df CYT |
537 | #endif |
538 | ||
539 | #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER | |
15278ccb | 540 | power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); |
38491d9c | 541 | #endif |
6944aff1 | 542 | #endif |
cba69eee IC |
543 | printf("DRAM:"); |
544 | ramsize = sunxi_dram_init(); | |
cd8b35d2 | 545 | printf(" %d MiB\n", (int)(ramsize >> 20)); |
cba69eee IC |
546 | if (!ramsize) |
547 | hang(); | |
14bc66bd HN |
548 | |
549 | /* | |
550 | * Only clock up the CPU to full speed if we are reasonably | |
551 | * assured it's being powered with suitable core voltage | |
552 | */ | |
553 | if (!power_failed) | |
e71b422b | 554 | clock_set_pll1(CONFIG_SYS_CLK_FREQ); |
14bc66bd HN |
555 | else |
556 | printf("Failed to set core voltage! Can't set CPU frequency\n"); | |
cba69eee IC |
557 | } |
558 | #endif | |
b41d7d05 | 559 | |
f1df758d PK |
560 | #ifdef CONFIG_USB_GADGET |
561 | int g_dnl_board_usb_cable_connected(void) | |
562 | { | |
5bfdca0d | 563 | return sunxi_usb_phy_vbus_detect(0); |
f1df758d PK |
564 | } |
565 | #endif | |
566 | ||
9f852211 PK |
567 | #ifdef CONFIG_SERIAL_TAG |
568 | void get_board_serial(struct tag_serialnr *serialnr) | |
569 | { | |
570 | char *serial_string; | |
571 | unsigned long long serial; | |
572 | ||
573 | serial_string = getenv("serial#"); | |
574 | ||
575 | if (serial_string) { | |
576 | serial = simple_strtoull(serial_string, NULL, 16); | |
577 | ||
578 | serialnr->high = (unsigned int) (serial >> 32); | |
579 | serialnr->low = (unsigned int) (serial & 0xffffffff); | |
580 | } else { | |
581 | serialnr->high = 0; | |
582 | serialnr->low = 0; | |
583 | } | |
584 | } | |
585 | #endif | |
586 | ||
af654d14 BN |
587 | /* |
588 | * Check the SPL header for the "sunxi" variant. If found: parse values | |
589 | * that might have been passed by the loader ("fel" utility), and update | |
590 | * the environment accordingly. | |
591 | */ | |
592 | static void parse_spl_header(const uint32_t spl_addr) | |
593 | { | |
d96ebc46 | 594 | struct boot_file_head *spl = (void *)(ulong)spl_addr; |
320e0570 BN |
595 | if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) |
596 | return; /* signature mismatch, no usable header */ | |
597 | ||
598 | uint8_t spl_header_version = spl->spl_signature[3]; | |
599 | if (spl_header_version != SPL_HEADER_VERSION) { | |
af654d14 BN |
600 | printf("sunxi SPL version mismatch: expected %u, got %u\n", |
601 | SPL_HEADER_VERSION, spl_header_version); | |
320e0570 BN |
602 | return; |
603 | } | |
604 | if (!spl->fel_script_address) | |
605 | return; | |
606 | ||
607 | if (spl->fel_uEnv_length != 0) { | |
608 | /* | |
609 | * data is expected in uEnv.txt compatible format, so "env | |
610 | * import -t" the string(s) at fel_script_address right away. | |
611 | */ | |
5a74a391 | 612 | himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, |
320e0570 BN |
613 | spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); |
614 | return; | |
af654d14 | 615 | } |
320e0570 BN |
616 | /* otherwise assume .scr format (mkimage-type script) */ |
617 | setenv_hex("fel_scriptaddr", spl->fel_script_address); | |
af654d14 | 618 | } |
af654d14 | 619 | |
f221961e HG |
620 | /* |
621 | * Note this function gets called multiple times. | |
622 | * It must not make any changes to env variables which already exist. | |
623 | */ | |
624 | static void setup_environment(const void *fdt) | |
b41d7d05 | 625 | { |
8c816573 | 626 | char serial_string[17] = { 0 }; |
cac5b1cc | 627 | unsigned int sid[4]; |
8c816573 | 628 | uint8_t mac_addr[6]; |
f221961e HG |
629 | char ethaddr[16]; |
630 | int i, ret; | |
af654d14 | 631 | |
8c816573 | 632 | ret = sunxi_get_sid(sid); |
3f8ea3b0 HG |
633 | if (ret == 0 && sid[0] != 0) { |
634 | /* | |
635 | * The single words 1 - 3 of the SID have quite a few bits | |
636 | * which are the same on many models, so we take a crc32 | |
637 | * of all 3 words, to get a more unique value. | |
638 | * | |
639 | * Note we only do this on newer SoCs as we cannot change | |
640 | * the algorithm on older SoCs since those have been using | |
641 | * fixed mac-addresses based on only using word 3 for a | |
642 | * long time and changing a fixed mac-address with an | |
643 | * u-boot update is not good. | |
644 | */ | |
645 | #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ | |
646 | !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ | |
647 | !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) | |
648 | sid[3] = crc32(0, (unsigned char *)&sid[1], 12); | |
649 | #endif | |
650 | ||
97322c3e HG |
651 | /* Ensure the NIC specific bytes of the mac are not all 0 */ |
652 | if ((sid[3] & 0xffffff) == 0) | |
653 | sid[3] |= 0x800000; | |
654 | ||
f221961e HG |
655 | for (i = 0; i < 4; i++) { |
656 | sprintf(ethaddr, "ethernet%d", i); | |
657 | if (!fdt_get_alias(fdt, ethaddr)) | |
658 | continue; | |
659 | ||
660 | if (i == 0) | |
661 | strcpy(ethaddr, "ethaddr"); | |
662 | else | |
663 | sprintf(ethaddr, "eth%daddr", i); | |
664 | ||
665 | if (getenv(ethaddr)) | |
666 | continue; | |
667 | ||
8c816573 | 668 | /* Non OUI / registered MAC address */ |
f221961e | 669 | mac_addr[0] = (i << 4) | 0x02; |
8c816573 PK |
670 | mac_addr[1] = (sid[0] >> 0) & 0xff; |
671 | mac_addr[2] = (sid[3] >> 24) & 0xff; | |
672 | mac_addr[3] = (sid[3] >> 16) & 0xff; | |
673 | mac_addr[4] = (sid[3] >> 8) & 0xff; | |
674 | mac_addr[5] = (sid[3] >> 0) & 0xff; | |
675 | ||
f221961e | 676 | eth_setenv_enetaddr(ethaddr, mac_addr); |
8c816573 | 677 | } |
b41d7d05 | 678 | |
8c816573 PK |
679 | if (!getenv("serial#")) { |
680 | snprintf(serial_string, sizeof(serial_string), | |
681 | "%08x%08x", sid[0], sid[3]); | |
b41d7d05 | 682 | |
8c816573 PK |
683 | setenv("serial#", serial_string); |
684 | } | |
b41d7d05 | 685 | } |
f221961e HG |
686 | } |
687 | ||
f221961e HG |
688 | int misc_init_r(void) |
689 | { | |
690 | __maybe_unused int ret; | |
691 | ||
f221961e HG |
692 | setenv("fel_booted", NULL); |
693 | setenv("fel_scriptaddr", NULL); | |
694 | /* determine if we are running in FEL mode */ | |
695 | if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ | |
696 | setenv("fel_booted", "1"); | |
697 | parse_spl_header(SPL_ADDR); | |
698 | } | |
f221961e HG |
699 | |
700 | setup_environment(gd->fdt_blob); | |
b41d7d05 | 701 | |
1871a8ca | 702 | #ifndef CONFIG_MACH_SUN9I |
e13afeef HG |
703 | ret = sunxi_usb_phy_probe(); |
704 | if (ret) | |
705 | return ret; | |
1871a8ca | 706 | #endif |
d42faf31 HG |
707 | sunxi_musb_board_init(); |
708 | ||
b41d7d05 JL |
709 | return 0; |
710 | } | |
2d7a084b | 711 | |
2d7a084b LV |
712 | int ft_board_setup(void *blob, bd_t *bd) |
713 | { | |
d75111a7 HG |
714 | int __maybe_unused r; |
715 | ||
f221961e HG |
716 | /* |
717 | * Call setup_environment again in case the boot fdt has | |
718 | * ethernet aliases the u-boot copy does not have. | |
719 | */ | |
720 | setup_environment(blob); | |
721 | ||
2d7a084b | 722 | #ifdef CONFIG_VIDEO_DT_SIMPLEFB |
d75111a7 HG |
723 | r = sunxi_simplefb_setup(blob); |
724 | if (r) | |
725 | return r; | |
2d7a084b | 726 | #endif |
d75111a7 | 727 | return 0; |
2d7a084b | 728 | } |