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09f95102 HG |
1 | #include <common.h> |
2 | #include <asm/arch/dram.h> | |
3 | ||
4 | static struct dram_para dram_para = { | |
8ffc487c | 5 | .clock = CONFIG_DRAM_CLK, |
09f95102 HG |
6 | .type = 3, |
7 | .rank_num = 1, | |
8ffc487c HG |
8 | .density = 0, |
9 | .io_width = 0, | |
10 | .bus_width = 0, | |
8ffc487c | 11 | .zq = CONFIG_DRAM_ZQ, |
8975cdf4 | 12 | .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), |
8ffc487c | 13 | .size = 0, |
d133647a SS |
14 | #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC |
15 | .cas = 6, | |
09f95102 HG |
16 | .tpr0 = 0x30926692, |
17 | .tpr1 = 0x1090, | |
18 | .tpr2 = 0x1a0c8, | |
d133647a SS |
19 | .emr2 = 0, |
20 | #else | |
21 | # include "dram_timings_sun4i.h" | |
47e3501a | 22 | .active_windowing = 1, |
d133647a | 23 | #endif |
47e3501a | 24 | .tpr3 = CONFIG_DRAM_TPR3, |
09f95102 HG |
25 | .tpr4 = 0, |
26 | .tpr5 = 0, | |
8ffc487c | 27 | .emr1 = CONFIG_DRAM_EMR1, |
09f95102 | 28 | .emr3 = 0, |
47e3501a | 29 | .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, |
09f95102 HG |
30 | }; |
31 | ||
32 | unsigned long sunxi_dram_init(void) | |
33 | { | |
34 | return dramc_init(&dram_para); | |
35 | } |