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56333be9 | 1 | /* DRAM parameters for auto dram configuration on sun5i and sun7i */ |
6c46c8e8 HG |
2 | |
3 | #include <common.h> | |
4 | #include <asm/arch/dram.h> | |
5 | ||
6 | static struct dram_para dram_para = { | |
7 | .clock = CONFIG_DRAM_CLK, | |
47e3501a | 8 | .mbus_clock = CONFIG_DRAM_MBUS_CLK, |
6c46c8e8 HG |
9 | .type = 3, |
10 | .rank_num = 1, | |
11 | .density = 0, | |
12 | .io_width = 0, | |
13 | .bus_width = 0, | |
6c46c8e8 | 14 | .zq = CONFIG_DRAM_ZQ, |
8975cdf4 | 15 | .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), |
6c46c8e8 | 16 | .size = 0, |
d133647a SS |
17 | #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC |
18 | .cas = 9, | |
6c46c8e8 HG |
19 | .tpr0 = 0x42d899b7, |
20 | .tpr1 = 0xa090, | |
21 | .tpr2 = 0x22a00, | |
d133647a SS |
22 | .emr2 = 0x10, |
23 | #else | |
24 | # include "dram_timings_sun4i.h" | |
47e3501a | 25 | .active_windowing = 1, |
d133647a | 26 | #endif |
8d6e18df | 27 | .tpr3 = CONFIG_DRAM_TPR3, |
6c46c8e8 HG |
28 | .tpr4 = 0, |
29 | .tpr5 = 0, | |
30 | .emr1 = CONFIG_DRAM_EMR1, | |
6c46c8e8 | 31 | .emr3 = 0, |
47e3501a | 32 | .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, |
6c46c8e8 HG |
33 | }; |
34 | ||
35 | unsigned long sunxi_dram_init(void) | |
36 | { | |
37 | return dramc_init(&dram_para); | |
38 | } |