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dc7c9a1a WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc8xx.h> | |
26 | ||
27 | /* ------------------------------------------------------------------------- */ | |
28 | const uint sdram_table[] = | |
29 | { | |
30 | /*----------------- | |
31 | UPM A contents: | |
32 | ----------------- */ | |
33 | /*--------------------------------------------------- | |
34 | Read Single Beat Cycle. Offset 0 in the RAM array. | |
35 | ---------------------------------------------------- */ | |
36 | 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , | |
37 | 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , | |
38 | /*------------------------------------------------ | |
39 | Read Burst Cycle. Offset 0x8 in the RAM array. | |
40 | ------------------------------------------------ */ | |
41 | 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, | |
42 | 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, | |
43 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, | |
44 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, | |
45 | /*------------------------------------------------------- | |
46 | Write Single Beat Cycle. Offset 0x18 in the RAM array | |
47 | ------------------------------------------------------- */ | |
48 | 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , | |
49 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , | |
50 | /*------------------------------------------------- | |
51 | Write Burst Cycle. Offset 0x20 in the RAM array | |
52 | ------------------------------------------------- */ | |
53 | 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, | |
54 | 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, | |
55 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , | |
56 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , | |
57 | /*------------------------------------------------------------------------ | |
58 | Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array | |
59 | ------------------------------------------------------------------------ */ | |
60 | 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, | |
61 | 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, | |
62 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , | |
63 | /*----------- | |
64 | * Exception: | |
65 | * ----------- */ | |
66 | 0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , | |
67 | }; | |
68 | ||
69 | /* ------------------------------------------------------------------------- */ | |
70 | /* | |
71 | * Check Board Identity: | |
72 | * | |
73 | * Test ID string (SVM8...) | |
74 | * | |
75 | * Return 1 for "SC8xx" type, 0 else. | |
76 | */ | |
77 | ||
f0c0b3a9 | 78 | int checkboard(void) |
dc7c9a1a | 79 | { |
f0c0b3a9 WD |
80 | char buf[64]; |
81 | int i; | |
82 | int l = getenv_f("serial#", buf, sizeof(buf)); | |
83 | int board_type; | |
dc7c9a1a | 84 | |
f0c0b3a9 WD |
85 | if (l < 0 || strncmp(buf, "SVM8", 4)) { |
86 | printf("### No HW ID - assuming SVM SC8xx\n"); | |
87 | return (0); | |
88 | } | |
dc7c9a1a | 89 | |
f0c0b3a9 | 90 | board_type = 1; |
dc7c9a1a | 91 | |
f0c0b3a9 WD |
92 | for (i = 0; i < l; ++i) { |
93 | if (buf[i] == ' ') | |
94 | break; | |
95 | putc(buf[i]); | |
96 | } | |
dc7c9a1a | 97 | |
f0c0b3a9 | 98 | putc('\n'); |
dc7c9a1a | 99 | |
f0c0b3a9 | 100 | return (0); |
dc7c9a1a WD |
101 | } |
102 | ||
103 | /* ------------------------------------------------------------------------- */ | |
104 | ||
9973e3c6 | 105 | phys_size_t initdram (int board_type) |
8bde7f77 | 106 | { |
6d0f6bcf | 107 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
dc7c9a1a WD |
108 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
109 | long int size_b0 = 0; | |
110 | ||
111 | upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); | |
112 | ||
6d0f6bcf | 113 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
dc7c9a1a | 114 | #if defined (CONFIG_SDRAM_16M) |
6d0f6bcf | 115 | memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; |
dc7c9a1a WD |
116 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
117 | udelay(1); | |
118 | memctl->memc_mcr = 0x80002830; | |
119 | udelay(1); | |
120 | memctl->memc_mar = 0x00000088; | |
121 | udelay(1); | |
122 | memctl->memc_mcr = 0x80002106; | |
123 | udelay(1); | |
124 | memctl->memc_or1 = 0xff000a00; | |
125 | size_b0 = 0x01000000; | |
126 | #elif defined (CONFIG_SDRAM_32M) | |
6d0f6bcf | 127 | memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; |
dc7c9a1a WD |
128 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
129 | udelay(1); | |
130 | memctl->memc_mcr = 0x80002830; | |
131 | udelay(1); | |
132 | memctl->memc_mar = 0x00000088; | |
133 | udelay(1); | |
134 | memctl->memc_mcr = 0x80002106; | |
135 | udelay(1); | |
136 | memctl->memc_or1 = 0xfe000a00; | |
137 | size_b0 = 0x02000000; | |
138 | #elif defined (CONFIG_SDRAM_64M) | |
6d0f6bcf | 139 | memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; |
dc7c9a1a WD |
140 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
141 | udelay(1); | |
142 | memctl->memc_mcr = 0x80002830; | |
143 | udelay(1); | |
144 | memctl->memc_mar = 0x00000088; | |
145 | udelay(1); | |
146 | memctl->memc_mcr = 0x80002106; | |
147 | udelay(1); | |
148 | memctl->memc_or1 = 0xfc000a00; | |
149 | size_b0 = 0x04000000; | |
8bde7f77 | 150 | #else |
dc7c9a1a WD |
151 | #error SDRAM size configuration missing. |
152 | #endif | |
153 | memctl->memc_br1 = 0x00000081; | |
154 | udelay(200); | |
155 | return (size_b0 ); | |
156 | } | |
157 | ||
ab3abcba | 158 | #if defined(CONFIG_CMD_DOC) |
dc7c9a1a WD |
159 | void doc_init (void) |
160 | { | |
6d0f6bcf | 161 | doc_probe (CONFIG_SYS_DOC_BASE); |
dc7c9a1a WD |
162 | } |
163 | #endif |