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Commit | Line | Data |
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2c3f9261 AB |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright (C) 2018 Synopsys, Inc. All rights reserved. | |
4 | */ | |
5 | ||
09140113 | 6 | #include <command.h> |
9a3b4ceb | 7 | #include <cpu_func.h> |
2c3f9261 | 8 | #include <dwmmc.h> |
691d719d | 9 | #include <init.h> |
2c3f9261 | 10 | #include <malloc.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
cd93d625 | 12 | #include <linux/bitops.h> |
2c3f9261 | 13 | |
4e86c7e3 AB |
14 | #include <asm/arcregs.h> |
15 | ||
2c3f9261 AB |
16 | DECLARE_GLOBAL_DATA_PTR; |
17 | ||
4e86c7e3 AB |
18 | #define ARC_PERIPHERAL_BASE 0xF0000000 |
19 | ||
20 | #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84) | |
21 | #define CGU_ARC_FMEAS_ARC_START BIT(31) | |
22 | #define CGU_ARC_FMEAS_ARC_DONE BIT(30) | |
23 | #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0) | |
24 | #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0 | |
25 | #define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15 | |
26 | ||
27 | #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000) | |
28 | ||
29 | int mach_cpu_init(void) | |
30 | { | |
31 | int rcnt, fcnt; | |
32 | u32 data; | |
33 | ||
34 | /* Start frequency measurement */ | |
35 | writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC); | |
36 | ||
37 | /* Poll DONE bit */ | |
38 | do { | |
39 | data = readl(CGU_ARC_FMEAS_ARC); | |
40 | } while (!(data & CGU_ARC_FMEAS_ARC_DONE)); | |
41 | ||
42 | /* Amount of reference 100 MHz clocks */ | |
43 | rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) & | |
44 | CGU_ARC_FMEAS_ARC_CNT_MASK); | |
45 | ||
46 | /* Amount of CPU clocks */ | |
47 | fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) & | |
48 | CGU_ARC_FMEAS_ARC_CNT_MASK); | |
49 | ||
50 | gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000; | |
51 | ||
52 | return 0; | |
53 | } | |
2c3f9261 | 54 | |
9ddaf1d5 AB |
55 | int board_early_init_r(void) |
56 | { | |
57 | #define EMSDP_PSRAM_BASE 0xf2001000 | |
58 | #define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10) | |
59 | #define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14) | |
60 | #define CRE_ENABLE BIT(31) | |
61 | #define CRE_DRIVE_CMD BIT(6) | |
62 | ||
63 | #define PSRAM_RCR_DPD BIT(1) | |
64 | #define PSRAM_RCR_PAGE_MODE BIT(7) | |
65 | ||
66 | /* | |
67 | * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash, | |
68 | * thus "<< 1". | |
69 | */ | |
70 | #define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1) | |
71 | ||
72 | // Switch PSRAM controller to command mode | |
73 | writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0); | |
74 | // Program Refresh Configuration Register (RCR) for BANK0 | |
75 | writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP)); | |
76 | // Switch PSRAM controller back to memory mode | |
77 | writel(0, PSRAM_FLASH_CONFIG_REG_0); | |
78 | ||
79 | ||
80 | // Switch PSRAM controller to command mode | |
81 | writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1); | |
82 | // Program Refresh Configuration Register (RCR) for BANK1 | |
83 | writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP)); | |
84 | // Switch PSRAM controller back to memory mode | |
85 | writel(0, PSRAM_FLASH_CONFIG_REG_1); | |
86 | ||
87 | printf("PSRAM initialized.\n"); | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
2c3f9261 | 92 | #define CREG_BASE 0xF0001000 |
fb9a46a2 AB |
93 | #define CREG_BOOT (void *)(CREG_BASE + 0x0FF0) |
94 | #define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0) | |
6ef705b1 | 95 | #define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8) |
2c3f9261 | 96 | |
fb9a46a2 AB |
97 | /* Bits in CREG_BOOT register */ |
98 | #define CREG_BOOT_WP_BIT BIT(8) | |
2c3f9261 | 99 | |
35b65dd8 | 100 | void reset_cpu(void) |
2c3f9261 | 101 | { |
fb9a46a2 | 102 | writel(1, CREG_IP_SW_RESET); |
2c3f9261 AB |
103 | while (1) |
104 | ; /* loop forever till reset */ | |
105 | } | |
106 | ||
09140113 SG |
107 | static int do_emsdp_rom(struct cmd_tbl *cmdtp, int flag, int argc, |
108 | char *const argv[]) | |
2c3f9261 | 109 | { |
fb9a46a2 | 110 | u32 creg_boot = readl(CREG_BOOT); |
2c3f9261 AB |
111 | |
112 | if (!strcmp(argv[1], "unlock")) | |
fb9a46a2 | 113 | creg_boot &= ~CREG_BOOT_WP_BIT; |
2c3f9261 | 114 | else if (!strcmp(argv[1], "lock")) |
fb9a46a2 | 115 | creg_boot |= CREG_BOOT_WP_BIT; |
2c3f9261 AB |
116 | else |
117 | return CMD_RET_USAGE; | |
118 | ||
fb9a46a2 | 119 | writel(creg_boot, CREG_BOOT); |
2c3f9261 AB |
120 | |
121 | return CMD_RET_SUCCESS; | |
122 | } | |
123 | ||
09140113 | 124 | struct cmd_tbl cmd_emsdp[] = { |
adc9b09a | 125 | U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""), |
2c3f9261 AB |
126 | }; |
127 | ||
09140113 SG |
128 | static int do_emsdp(struct cmd_tbl *cmdtp, int flag, int argc, |
129 | char *const argv[]) | |
2c3f9261 | 130 | { |
09140113 | 131 | struct cmd_tbl *c; |
2c3f9261 | 132 | |
adc9b09a | 133 | c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp)); |
2c3f9261 | 134 | |
adc9b09a | 135 | /* Strip off leading 'emsdp' command */ |
2c3f9261 AB |
136 | argc--; |
137 | argv++; | |
138 | ||
139 | if (c == NULL || argc > c->maxargs) | |
140 | return CMD_RET_USAGE; | |
141 | ||
142 | return c->cmd(cmdtp, flag, argc, argv); | |
143 | } | |
144 | ||
145 | U_BOOT_CMD( | |
adc9b09a AB |
146 | emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp, |
147 | "Synopsys EMSDP specific commands", | |
2c3f9261 | 148 | "rom unlock - Unlock non-volatile memory for writing\n" |
adc9b09a | 149 | "emsdp rom lock - Lock non-volatile memory to prevent writing\n" |
2c3f9261 | 150 | ); |
6ef705b1 AB |
151 | |
152 | int checkboard(void) | |
153 | { | |
154 | int version = readl(CREG_IP_VERSION); | |
155 | ||
156 | printf("Board: ARC EM Software Development Platform v%d.%d\n", | |
157 | (version >> 16) & 0xff, version & 0xff); | |
158 | return 0; | |
159 | }; |