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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
67482f57 | 2 | /* |
ada8affd EP |
3 | * Copyright (C) 2018 Synopsys, Inc. All rights reserved. |
4 | * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | |
67482f57 AB |
5 | */ |
6 | ||
09140113 | 7 | #include <command.h> |
ada8affd | 8 | #include <config.h> |
9edefc27 | 9 | #include <cpu_func.h> |
168068fb | 10 | #include <env.h> |
4d72caa5 | 11 | #include <image.h> |
5255932f | 12 | #include <init.h> |
36bf446b | 13 | #include <irq_func.h> |
f7ae49fc | 14 | #include <log.h> |
90526e9f | 15 | #include <asm/cache.h> |
401d1c4f | 16 | #include <asm/global_data.h> |
cd93d625 | 17 | #include <linux/bitops.h> |
c05ed00a | 18 | #include <linux/delay.h> |
ada8affd EP |
19 | #include <linux/printk.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/io.h> | |
22 | #include <asm/arcregs.h> | |
23 | #include <fdt_support.h> | |
67482f57 AB |
24 | #include <dwmmc.h> |
25 | #include <malloc.h> | |
ada8affd EP |
26 | #include <usb.h> |
27 | ||
28 | #include "clk-lib.h" | |
29 | #include "env-lib.h" | |
67482f57 AB |
30 | |
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
ada8affd EP |
33 | #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0) |
34 | #define MASTER_CPU_ID 0 | |
35 | #define APERTURE_SHIFT 28 | |
36 | #define NO_CCM 0x10 | |
37 | #define SLAVE_CPU_READY 0x12345678 | |
38 | #define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */ | |
39 | #define BOOTSTAGE_2 2 /* after HW init, before self halt */ | |
40 | #define BOOTSTAGE_3 3 /* after self halt */ | |
41 | #define BOOTSTAGE_4 4 /* before app launch */ | |
42 | #define BOOTSTAGE_5 5 /* after app launch, unreachable */ | |
67482f57 | 43 | |
ada8affd EP |
44 | #define RESET_VECTOR_ADDR 0x0 |
45 | ||
46 | #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) | |
47 | #define CREG_CPU_START (CREG_BASE + 0x400) | |
48 | #define CREG_CPU_START_MASK 0xF | |
4b4da7ff | 49 | #define CREG_CPU_START_POL BIT(4) |
ada8affd | 50 | |
a8eb9b26 EP |
51 | #define CREG_CORE_BOOT_IMAGE GENMASK(5, 4) |
52 | ||
25998aed EP |
53 | #define CREG_CPU_0_ENTRY (CREG_BASE + 0x404) |
54 | ||
ada8affd EP |
55 | #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000) |
56 | #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108) | |
57 | #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30) | |
58 | ||
59 | /* Uncached access macros */ | |
60 | #define arc_read_uncached_32(ptr) \ | |
61 | ({ \ | |
62 | unsigned int __ret; \ | |
63 | __asm__ __volatile__( \ | |
64 | " ld.di %0, [%1] \n" \ | |
65 | : "=r"(__ret) \ | |
66 | : "r"(ptr)); \ | |
67 | __ret; \ | |
68 | }) | |
69 | ||
70 | #define arc_write_uncached_32(ptr, data)\ | |
71 | ({ \ | |
72 | __asm__ __volatile__( \ | |
73 | " st.di %0, [%1] \n" \ | |
74 | : \ | |
75 | : "r"(data), "r"(ptr)); \ | |
76 | }) | |
77 | ||
78 | struct hsdk_env_core_ctl { | |
79 | u32_env entry[NR_CPUS]; | |
80 | u32_env iccm[NR_CPUS]; | |
81 | u32_env dccm[NR_CPUS]; | |
82 | }; | |
83 | ||
84 | struct hsdk_env_common_ctl { | |
85 | bool halt_on_boot; | |
86 | u32_env core_mask; | |
87 | u32_env cpu_freq; | |
88 | u32_env axi_freq; | |
89 | u32_env tun_freq; | |
90 | u32_env nvlim; | |
91 | u32_env icache; | |
92 | u32_env dcache; | |
6917a9db | 93 | u32_env csm_location; |
1d897d1a | 94 | u32_env l2_cache; |
32ac4ee6 | 95 | u32_env haps_apb; |
ada8affd EP |
96 | }; |
97 | ||
98 | /* | |
99 | * Uncached cross-cpu structure. All CPUs must access to this structure fields | |
100 | * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which | |
101 | * implement ld.di / st.di instructions). Simultaneous cached and uncached | |
102 | * access to this area will lead to data loss. | |
103 | * We flush all data caches in board_early_init_r() as we don't want to have | |
104 | * any dirty line in L1d$ or SL$ in this area. | |
105 | */ | |
106 | struct hsdk_cross_cpu { | |
107 | /* slave CPU ready flag */ | |
108 | u32 ready_flag; | |
109 | /* address of the area, which can be used for stack by slave CPU */ | |
110 | u32 stack_ptr; | |
111 | /* slave CPU status - bootstage number */ | |
112 | s32 status[NR_CPUS]; | |
113 | ||
114 | /* | |
115 | * Slave CPU data - it is copy of corresponding fields in | |
116 | * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are | |
117 | * required for slave CPUs initialization. | |
118 | * This fields can be populated by copying from hsdk_env_core_ctl | |
119 | * and hsdk_env_common_ctl structures with sync_cross_cpu_data() | |
120 | * function. | |
121 | */ | |
122 | u32 entry[NR_CPUS]; | |
123 | u32 iccm[NR_CPUS]; | |
124 | u32 dccm[NR_CPUS]; | |
125 | ||
126 | u32 core_mask; | |
127 | u32 icache; | |
128 | u32 dcache; | |
129 | ||
130 | u8 cache_padding[ARCH_DMA_MINALIGN]; | |
131 | } __aligned(ARCH_DMA_MINALIGN); | |
132 | ||
133 | /* Place for slave CPUs temporary stack */ | |
134 | static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN); | |
135 | ||
136 | static struct hsdk_env_common_ctl env_common = {}; | |
137 | static struct hsdk_env_core_ctl env_core = {}; | |
138 | static struct hsdk_cross_cpu cross_cpu_data; | |
139 | ||
140 | static const struct env_map_common env_map_common[] = { | |
141 | { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask }, | |
142 | { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim }, | |
143 | { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache }, | |
144 | { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache }, | |
1d897d1a EP |
145 | #if defined(CONFIG_BOARD_HSDK_4XD) |
146 | { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache }, | |
6917a9db | 147 | { "csm_location", ENV_HEX, true, 0, NO_CCM, &env_common.csm_location }, |
32ac4ee6 | 148 | { "haps_apb_location", ENV_HEX, true, 0, 1, &env_common.haps_apb }, |
1d897d1a | 149 | #endif /* CONFIG_BOARD_HSDK_4XD */ |
ada8affd EP |
150 | {} |
151 | }; | |
152 | ||
153 | static const struct env_map_common env_map_clock[] = { | |
154 | { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq }, | |
155 | { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq }, | |
156 | { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq }, | |
157 | {} | |
158 | }; | |
159 | ||
160 | static const struct env_map_percpu env_map_core[] = { | |
161 | { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm }, | |
162 | { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm }, | |
163 | {} | |
164 | }; | |
165 | ||
166 | static const struct env_map_common env_map_mask[] = { | |
167 | { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask }, | |
168 | {} | |
169 | }; | |
170 | ||
171 | static const struct env_map_percpu env_map_go[] = { | |
172 | { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry }, | |
173 | {} | |
174 | }; | |
175 | ||
f0f84efe EP |
176 | enum board_type { |
177 | T_BOARD_NONE, | |
178 | T_BOARD_HSDK, | |
179 | T_BOARD_HSDK_4XD | |
180 | }; | |
181 | ||
182 | static inline enum board_type get_board_type_runtime(void) | |
183 | { | |
184 | u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF; | |
185 | ||
186 | if (arc_id == 0x52) | |
187 | return T_BOARD_HSDK; | |
188 | else if (arc_id == 0x54) | |
189 | return T_BOARD_HSDK_4XD; | |
190 | else | |
191 | return T_BOARD_NONE; | |
192 | } | |
193 | ||
194 | static inline enum board_type get_board_type_config(void) | |
195 | { | |
196 | if (IS_ENABLED(CONFIG_BOARD_HSDK)) | |
197 | return T_BOARD_HSDK; | |
198 | else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD)) | |
199 | return T_BOARD_HSDK_4XD; | |
200 | else | |
201 | return T_BOARD_NONE; | |
202 | } | |
203 | ||
204 | static bool is_board_match_runtime(enum board_type type_req) | |
205 | { | |
206 | return get_board_type_runtime() == type_req; | |
207 | } | |
208 | ||
1d897d1a EP |
209 | static bool is_board_match_config(enum board_type type_req) |
210 | { | |
211 | return get_board_type_config() == type_req; | |
212 | } | |
213 | ||
f0f84efe EP |
214 | static const char * board_name(enum board_type type) |
215 | { | |
216 | switch (type) { | |
217 | case T_BOARD_HSDK: | |
218 | return "ARC HS Development Kit"; | |
219 | case T_BOARD_HSDK_4XD: | |
220 | return "ARC HS4x/HS4xD Development Kit"; | |
221 | default: | |
222 | return "?"; | |
223 | } | |
224 | } | |
225 | ||
226 | static bool board_mismatch(void) | |
227 | { | |
228 | return get_board_type_config() != get_board_type_runtime(); | |
229 | } | |
230 | ||
ada8affd EP |
231 | static void sync_cross_cpu_data(void) |
232 | { | |
233 | u32 value; | |
234 | ||
235 | for (u32 i = 0; i < NR_CPUS; i++) { | |
236 | value = env_core.entry[i].val; | |
237 | arc_write_uncached_32(&cross_cpu_data.entry[i], value); | |
238 | } | |
239 | ||
240 | for (u32 i = 0; i < NR_CPUS; i++) { | |
241 | value = env_core.iccm[i].val; | |
242 | arc_write_uncached_32(&cross_cpu_data.iccm[i], value); | |
243 | } | |
244 | ||
245 | for (u32 i = 0; i < NR_CPUS; i++) { | |
246 | value = env_core.dccm[i].val; | |
247 | arc_write_uncached_32(&cross_cpu_data.dccm[i], value); | |
248 | } | |
249 | ||
250 | value = env_common.core_mask.val; | |
251 | arc_write_uncached_32(&cross_cpu_data.core_mask, value); | |
252 | ||
253 | value = env_common.icache.val; | |
254 | arc_write_uncached_32(&cross_cpu_data.icache, value); | |
255 | ||
256 | value = env_common.dcache.val; | |
257 | arc_write_uncached_32(&cross_cpu_data.dcache, value); | |
258 | } | |
259 | ||
260 | /* Can be used only on master CPU */ | |
261 | static bool is_cpu_used(u32 cpu_id) | |
67482f57 | 262 | { |
ada8affd EP |
263 | return !!(env_common.core_mask.val & BIT(cpu_id)); |
264 | } | |
67482f57 | 265 | |
ada8affd EP |
266 | /* TODO: add ICCM BCR and DCCM BCR runtime check */ |
267 | static void init_slave_cpu_func(u32 core) | |
268 | { | |
269 | u32 val; | |
270 | ||
271 | /* Remap ICCM to another memory region if it exists */ | |
272 | val = arc_read_uncached_32(&cross_cpu_data.iccm[core]); | |
273 | if (val != NO_CCM) | |
274 | write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT); | |
275 | ||
276 | /* Remap DCCM to another memory region if it exists */ | |
277 | val = arc_read_uncached_32(&cross_cpu_data.dccm[core]); | |
278 | if (val != NO_CCM) | |
279 | write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT); | |
280 | ||
281 | if (arc_read_uncached_32(&cross_cpu_data.icache)) | |
282 | icache_enable(); | |
283 | else | |
284 | icache_disable(); | |
285 | ||
286 | if (arc_read_uncached_32(&cross_cpu_data.dcache)) | |
287 | dcache_enable(); | |
288 | else | |
289 | dcache_disable(); | |
290 | } | |
291 | ||
292 | static void init_cluster_nvlim(void) | |
293 | { | |
294 | u32 val = env_common.nvlim.val << APERTURE_SHIFT; | |
295 | ||
296 | flush_dcache_all(); | |
297 | write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val); | |
f0f84efe EP |
298 | /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */ |
299 | if (is_board_match_runtime(T_BOARD_HSDK)) | |
300 | write_aux_reg(AUX_AUX_CACHE_LIMIT, val); | |
ada8affd EP |
301 | flush_n_invalidate_dcache_all(); |
302 | } | |
303 | ||
1d897d1a EP |
304 | static void init_cluster_slc(void) |
305 | { | |
306 | /* ARC HS38 doesn't support SLC disabling */ | |
307 | if (!is_board_match_config(T_BOARD_HSDK_4XD)) | |
308 | return; | |
309 | ||
310 | if (env_common.l2_cache.val) | |
311 | slc_enable(); | |
312 | else | |
313 | slc_disable(); | |
314 | } | |
315 | ||
6917a9db EP |
316 | #define CREG_CSM_BASE (CREG_BASE + 0x210) |
317 | ||
318 | static void init_cluster_csm(void) | |
319 | { | |
320 | /* ARC HS38 in HSDK SoC doesn't include CSM */ | |
321 | if (!is_board_match_config(T_BOARD_HSDK_4XD)) | |
322 | return; | |
323 | ||
324 | if (env_common.csm_location.val == NO_CCM) { | |
325 | write_aux_reg(ARC_AUX_CSM_ENABLE, 0); | |
326 | } else { | |
327 | /* | |
328 | * CSM base address is 256kByte aligned but we allow to map | |
329 | * CSM only to aperture start (256MByte aligned) | |
330 | * The field in CREG_CSM_BASE is in 17:2 bits itself so we need | |
331 | * to shift it. | |
332 | */ | |
333 | u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2; | |
334 | ||
335 | write_aux_reg(ARC_AUX_CSM_ENABLE, 1); | |
336 | writel(csm_base, (void __iomem *)CREG_CSM_BASE); | |
337 | } | |
338 | } | |
339 | ||
ada8affd EP |
340 | static void init_master_icache(void) |
341 | { | |
342 | if (icache_status()) { | |
343 | /* I$ is enabled - we need to disable it */ | |
344 | if (!env_common.icache.val) | |
345 | icache_disable(); | |
346 | } else { | |
347 | /* I$ is disabled - we need to enable it */ | |
348 | if (env_common.icache.val) { | |
349 | icache_enable(); | |
350 | ||
351 | /* invalidate I$ right after enable */ | |
352 | invalidate_icache_all(); | |
353 | } | |
354 | } | |
355 | } | |
356 | ||
357 | static void init_master_dcache(void) | |
358 | { | |
359 | if (dcache_status()) { | |
360 | /* D$ is enabled - we need to disable it */ | |
361 | if (!env_common.dcache.val) | |
362 | dcache_disable(); | |
363 | } else { | |
364 | /* D$ is disabled - we need to enable it */ | |
365 | if (env_common.dcache.val) | |
366 | dcache_enable(); | |
367 | ||
368 | /* TODO: probably we need ti invalidate D$ right after enable */ | |
369 | } | |
370 | } | |
371 | ||
372 | static int cleanup_before_go(void) | |
373 | { | |
374 | disable_interrupts(); | |
375 | sync_n_cleanup_cache_all(); | |
67482f57 AB |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
ada8affd EP |
380 | void slave_cpu_set_boot_addr(u32 addr) |
381 | { | |
382 | /* All cores have reset vector pointing to 0 */ | |
383 | writel(addr, (void __iomem *)RESET_VECTOR_ADDR); | |
4e782b59 | 384 | |
ada8affd EP |
385 | /* Make sure other cores see written value in memory */ |
386 | sync_n_cleanup_cache_all(); | |
387 | } | |
388 | ||
389 | static inline void halt_this_cpu(void) | |
67482f57 | 390 | { |
ada8affd EP |
391 | __builtin_arc_flag(1); |
392 | } | |
67482f57 | 393 | |
4b4da7ff | 394 | static u32 get_masked_cpu_ctart_reg(void) |
ada8affd EP |
395 | { |
396 | int cmd = readl((void __iomem *)CREG_CPU_START); | |
397 | ||
4b4da7ff EP |
398 | /* |
399 | * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity | |
400 | * and HSDK-4xD require active low polarity of cpu_start pulse. | |
401 | */ | |
402 | cmd &= ~CREG_CPU_START_POL; | |
403 | ||
404 | cmd &= ~CREG_CPU_START_MASK; | |
405 | ||
406 | return cmd; | |
407 | } | |
408 | ||
409 | static void smp_kick_cpu_x(u32 cpu_id) | |
410 | { | |
411 | int cmd; | |
412 | ||
ada8affd EP |
413 | if (cpu_id > NR_CPUS) |
414 | return; | |
415 | ||
4b4da7ff | 416 | cmd = get_masked_cpu_ctart_reg(); |
ada8affd EP |
417 | cmd |= (1 << cpu_id); |
418 | writel(cmd, (void __iomem *)CREG_CPU_START); | |
419 | } | |
420 | ||
421 | static u32 prepare_cpu_ctart_reg(void) | |
422 | { | |
4b4da7ff | 423 | return get_masked_cpu_ctart_reg() | env_common.core_mask.val; |
ada8affd EP |
424 | } |
425 | ||
426 | /* slave CPU entry for configuration */ | |
427 | __attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void) | |
428 | { | |
429 | __asm__ __volatile__( | |
430 | "ld.di r8, [%0]\n" | |
431 | "mov %%sp, r8\n" | |
432 | "mov %%fp, %%sp\n" | |
433 | : /* no output */ | |
434 | : "r" (&cross_cpu_data.stack_ptr)); | |
435 | ||
436 | invalidate_icache_all(); | |
437 | ||
438 | arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1); | |
439 | init_slave_cpu_func(CPU_ID_GET()); | |
440 | ||
441 | arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY); | |
442 | arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2); | |
443 | ||
444 | /* Halt the processor until the master kick us again */ | |
445 | halt_this_cpu(); | |
446 | ||
447 | /* | |
448 | * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2 | |
449 | * cores but we leave them for gebug purposes. | |
450 | */ | |
451 | __builtin_arc_nop(); | |
452 | __builtin_arc_nop(); | |
453 | __builtin_arc_nop(); | |
454 | ||
455 | arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3); | |
456 | ||
457 | /* get the updated entry - invalidate i$ */ | |
458 | invalidate_icache_all(); | |
459 | ||
460 | arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4); | |
461 | ||
462 | /* Run our program */ | |
463 | ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))(); | |
464 | ||
465 | /* This bootstage is unreachable as we don't return from app we launch */ | |
466 | arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5); | |
467 | ||
468 | /* Something went terribly wrong */ | |
469 | while (true) | |
470 | halt_this_cpu(); | |
471 | } | |
472 | ||
473 | static void clear_cross_cpu_data(void) | |
474 | { | |
475 | arc_write_uncached_32(&cross_cpu_data.ready_flag, 0); | |
476 | arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0); | |
477 | ||
478 | for (u32 i = 0; i < NR_CPUS; i++) | |
479 | arc_write_uncached_32(&cross_cpu_data.status[i], 0); | |
480 | } | |
481 | ||
482 | static noinline void do_init_slave_cpu(u32 cpu_id) | |
483 | { | |
484 | /* attempts number for check clave CPU ready_flag */ | |
485 | u32 attempts = 100; | |
486 | u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id)); | |
487 | ||
488 | if (cpu_id >= NR_CPUS) | |
489 | return; | |
490 | ||
491 | arc_write_uncached_32(&cross_cpu_data.ready_flag, 0); | |
492 | ||
493 | /* Use global unique place for each slave cpu stack */ | |
494 | arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr); | |
495 | ||
496 | debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack); | |
497 | debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr); | |
498 | slave_cpu_set_boot_addr((u32)hsdk_core_init_f); | |
499 | ||
500 | smp_kick_cpu_x(cpu_id); | |
501 | ||
502 | debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id, | |
503 | arc_read_uncached_32(&cross_cpu_data.ready_flag)); | |
504 | ||
505 | while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--) | |
506 | mdelay(10); | |
507 | ||
508 | /* Just to be sure that slave cpu is halted after it set ready_flag */ | |
509 | mdelay(20); | |
510 | ||
511 | /* | |
512 | * Only print error here if we reach timeout as there is no option to | |
513 | * halt slave cpu (or check that slave cpu is halted) | |
514 | */ | |
515 | if (!attempts) | |
516 | pr_err("CPU %u is not responding after init!\n", cpu_id); | |
517 | ||
518 | /* Check current stage of slave cpu */ | |
519 | if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2) | |
520 | pr_err("CPU %u status is unexpected: %d\n", cpu_id, | |
521 | arc_read_uncached_32(&cross_cpu_data.status[cpu_id])); | |
522 | ||
523 | debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id, | |
524 | arc_read_uncached_32(&cross_cpu_data.ready_flag)); | |
525 | debug("CPU %u: status: %d [after timeout]\n", cpu_id, | |
526 | arc_read_uncached_32(&cross_cpu_data.status[cpu_id])); | |
527 | } | |
528 | ||
529 | static void do_init_slave_cpus(void) | |
530 | { | |
531 | clear_cross_cpu_data(); | |
532 | sync_cross_cpu_data(); | |
533 | ||
534 | debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data); | |
535 | ||
536 | for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++) | |
537 | if (is_cpu_used(i)) | |
538 | do_init_slave_cpu(i); | |
539 | } | |
540 | ||
541 | static void do_init_master_cpu(void) | |
542 | { | |
543 | /* | |
544 | * Setup master caches even if master isn't used as we want to use | |
545 | * same cache configuration on all running CPUs | |
546 | */ | |
547 | init_master_icache(); | |
548 | init_master_dcache(); | |
549 | } | |
550 | ||
551 | enum hsdk_axi_masters { | |
552 | M_HS_CORE = 0, | |
553 | M_HS_RTT, | |
554 | M_AXI_TUN, | |
555 | M_HDMI_VIDEO, | |
556 | M_HDMI_AUDIO, | |
557 | M_USB_HOST, | |
558 | M_ETHERNET, | |
559 | M_SDIO, | |
560 | M_GPU, | |
561 | M_DMAC_0, | |
562 | M_DMAC_1, | |
563 | M_DVFS | |
564 | }; | |
565 | ||
566 | #define UPDATE_VAL 1 | |
567 | ||
568 | /* | |
569 | * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1 | |
570 | * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210 | |
571 | * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
572 | * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210 | |
573 | * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
574 | * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
575 | * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98 | |
576 | * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98 | |
577 | * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98 | |
578 | * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
579 | * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
580 | * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
581 | * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000 | |
582 | * | |
583 | * Please read ARC HS Development IC Specification, section 17.2 for more | |
584 | * information about apertures configuration. | |
1be82afa | 585 | * NOTE: we intentionally modify default settings in U-Boot. Default settings |
ada8affd EP |
586 | * are specified in "Table 111 CREG Address Decoder register reset values". |
587 | */ | |
588 | ||
589 | #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m))) | |
590 | #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004)) | |
591 | #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008)) | |
592 | #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C)) | |
593 | #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014)) | |
594 | ||
595 | #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010)) | |
596 | ||
597 | #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180)) | |
598 | #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194)) | |
599 | ||
600 | void init_memory_bridge(void) | |
601 | { | |
602 | u32 reg; | |
603 | ||
604 | /* | |
605 | * M_HS_CORE has one unic register - BOOT. | |
606 | * We need to clean boot mirror (BOOT[1:0]) bits in them. | |
607 | */ | |
608 | reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3); | |
609 | writel(reg, CREG_AXI_M_HS_CORE_BOOT); | |
610 | writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE)); | |
611 | writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE)); | |
612 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE)); | |
613 | writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE)); | |
614 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE)); | |
615 | ||
616 | writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); | |
617 | writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); | |
618 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); | |
619 | writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); | |
620 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); | |
621 | ||
622 | writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN)); | |
623 | writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN)); | |
624 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN)); | |
625 | writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN)); | |
626 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN)); | |
627 | ||
628 | writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO)); | |
629 | writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO)); | |
630 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO)); | |
631 | writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO)); | |
632 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO)); | |
633 | ||
634 | writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO)); | |
635 | writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO)); | |
636 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO)); | |
637 | writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO)); | |
638 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO)); | |
639 | ||
640 | writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST)); | |
641 | writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST)); | |
642 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST)); | |
643 | writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST)); | |
644 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST)); | |
645 | ||
646 | writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET)); | |
647 | writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET)); | |
648 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET)); | |
649 | writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET)); | |
650 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET)); | |
651 | ||
652 | writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO)); | |
653 | writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO)); | |
654 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO)); | |
655 | writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO)); | |
656 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO)); | |
657 | ||
658 | writel(0x77777777, CREG_AXI_M_SLV0(M_GPU)); | |
659 | writel(0x77777777, CREG_AXI_M_SLV1(M_GPU)); | |
660 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU)); | |
661 | writel(0x76543210, CREG_AXI_M_OFT1(M_GPU)); | |
662 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU)); | |
663 | ||
664 | writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); | |
665 | writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0)); | |
666 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); | |
667 | writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0)); | |
668 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); | |
669 | ||
670 | writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); | |
671 | writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1)); | |
672 | writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); | |
673 | writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1)); | |
674 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); | |
675 | ||
676 | writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS)); | |
677 | writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS)); | |
678 | writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS)); | |
679 | writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS)); | |
680 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS)); | |
681 | ||
682 | writel(0x00000000, CREG_PAE); | |
683 | writel(UPDATE_VAL, CREG_PAE_UPDT); | |
684 | } | |
685 | ||
32ac4ee6 EP |
686 | /* |
687 | * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command: | |
688 | * - we shrink IOC region. | |
689 | * - we configure HS CORE SLV1 aperture depending on haps_apb_location | |
690 | * environment variable. | |
691 | * | |
692 | * As we've already configured AXI bridge in init_memory_bridge we don't | |
693 | * do full configuration here but reconfigure changed part. | |
694 | * | |
695 | * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1 | |
696 | * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210 [haps_apb_location = 0] | |
697 | * 0 HS (CBU) 0x11111111 0x61111111 0xFEDCBA98 0x06543210 [haps_apb_location = 1] | |
698 | * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
699 | * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210 | |
700 | * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
701 | * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
702 | * 5 USB-HOST 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98 | |
703 | * 6 ETHERNET 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98 | |
704 | * 7 SDIO 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98 | |
705 | * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
706 | * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
707 | * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210 | |
708 | * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000 | |
709 | */ | |
710 | void tweak_memory_bridge_cfg(void) | |
711 | { | |
712 | /* | |
713 | * Only HSDK-4xD requre additional AXI bridge tweaking depending on | |
714 | * haps_apb_location environment variable | |
715 | */ | |
716 | if (!is_board_match_config(T_BOARD_HSDK_4XD)) | |
717 | return; | |
718 | ||
719 | if (env_common.haps_apb.val) { | |
720 | writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE)); | |
721 | writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE)); | |
722 | } else { | |
723 | writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE)); | |
724 | writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE)); | |
725 | } | |
726 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE)); | |
727 | ||
728 | writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST)); | |
729 | writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST)); | |
730 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST)); | |
731 | ||
732 | writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));; | |
733 | writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET)); | |
734 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET)); | |
735 | ||
736 | writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO)); | |
737 | writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO)); | |
738 | writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO)); | |
739 | } | |
740 | ||
ada8affd EP |
741 | static void setup_clocks(void) |
742 | { | |
743 | ulong rate; | |
744 | ||
745 | /* Setup CPU clock */ | |
746 | if (env_common.cpu_freq.set) { | |
747 | rate = env_common.cpu_freq.val; | |
748 | soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ); | |
67482f57 AB |
749 | } |
750 | ||
ada8affd EP |
751 | /* Setup TUN clock */ |
752 | if (env_common.tun_freq.set) { | |
753 | rate = env_common.tun_freq.val; | |
754 | if (rate) | |
755 | soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ); | |
756 | else | |
757 | soc_clk_ctl("tun-clk", NULL, CLK_OFF); | |
758 | } | |
759 | ||
760 | if (env_common.axi_freq.set) { | |
761 | rate = env_common.axi_freq.val; | |
762 | soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ); | |
763 | } | |
764 | } | |
765 | ||
766 | static void do_init_cluster(void) | |
767 | { | |
4e782b59 | 768 | /* |
ada8affd EP |
769 | * A multi-core ARC HS configuration always includes only one |
770 | * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the | |
771 | * cores. | |
4e782b59 | 772 | */ |
ada8affd | 773 | init_cluster_nvlim(); |
6917a9db | 774 | init_cluster_csm(); |
1d897d1a | 775 | init_cluster_slc(); |
32ac4ee6 | 776 | tweak_memory_bridge_cfg(); |
ada8affd | 777 | } |
4e782b59 | 778 | |
ada8affd EP |
779 | static int check_master_cpu_id(void) |
780 | { | |
781 | if (CPU_ID_GET() == MASTER_CPU_ID) | |
782 | return 0; | |
67482f57 | 783 | |
ada8affd EP |
784 | pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET()); |
785 | ||
786 | return -ENOENT; | |
787 | } | |
788 | ||
789 | static noinline int prepare_cpus(void) | |
790 | { | |
791 | int ret; | |
792 | ||
793 | ret = check_master_cpu_id(); | |
794 | if (ret) | |
795 | return ret; | |
796 | ||
797 | ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used); | |
798 | if (ret) | |
799 | return ret; | |
800 | ||
801 | printf("CPU start mask is %#x\n", env_common.core_mask.val); | |
802 | ||
803 | do_init_slave_cpus(); | |
804 | do_init_master_cpu(); | |
805 | do_init_cluster(); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static int hsdk_go_run(u32 cpu_start_reg) | |
811 | { | |
812 | /* Cleanup caches, disable interrupts */ | |
813 | cleanup_before_go(); | |
814 | ||
815 | if (env_common.halt_on_boot) | |
816 | halt_this_cpu(); | |
817 | ||
818 | /* | |
819 | * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2 | |
820 | * cores but we leave them for gebug purposes. | |
821 | */ | |
822 | __builtin_arc_nop(); | |
823 | __builtin_arc_nop(); | |
824 | __builtin_arc_nop(); | |
825 | ||
826 | /* Kick chosen slave CPUs */ | |
827 | writel(cpu_start_reg, (void __iomem *)CREG_CPU_START); | |
828 | ||
829 | if (is_cpu_used(MASTER_CPU_ID)) | |
830 | ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))(); | |
831 | else | |
832 | halt_this_cpu(); | |
833 | ||
834 | pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET()); | |
835 | ||
836 | /* | |
837 | * We will never return after executing our program if master cpu used | |
838 | * otherwise halt master cpu manually. | |
839 | */ | |
840 | while (true) | |
841 | halt_this_cpu(); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
d9d7c20b | 846 | int board_prep_linux(struct bootm_headers *images) |
ada8affd EP |
847 | { |
848 | int ret, ofst; | |
849 | char mask[15]; | |
850 | ||
851 | ret = envs_read_validate_common(env_map_mask); | |
852 | if (ret) | |
853 | return ret; | |
854 | ||
855 | /* Rollback to default values */ | |
856 | if (!env_common.core_mask.set) { | |
857 | env_common.core_mask.val = ALL_CPU_MASK; | |
858 | env_common.core_mask.set = true; | |
859 | } | |
860 | ||
861 | printf("CPU start mask is %#x\n", env_common.core_mask.val); | |
862 | ||
863 | if (!is_cpu_used(MASTER_CPU_ID)) | |
864 | pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n"); | |
865 | ||
866 | /* | |
867 | * If we want to launch linux on all CPUs we don't need to patch | |
868 | * linux DTB as it is default configuration | |
869 | */ | |
870 | if (env_common.core_mask.val == ALL_CPU_MASK) | |
871 | return 0; | |
872 | ||
0c303f9a | 873 | if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !images->ft_len) { |
ada8affd EP |
874 | pr_err("WARN: core_mask setup will work properly only with external DTB!\n"); |
875 | return 0; | |
876 | } | |
877 | ||
878 | /* patch '/possible-cpus' property according to cpu mask */ | |
879 | ofst = fdt_path_offset(images->ft_addr, "/"); | |
880 | sprintf(mask, "%s%s%s%s", | |
881 | is_cpu_used(0) ? "0," : "", | |
882 | is_cpu_used(1) ? "1," : "", | |
883 | is_cpu_used(2) ? "2," : "", | |
884 | is_cpu_used(3) ? "3," : ""); | |
885 | ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask); | |
886 | /* | |
887 | * If we failed to patch '/possible-cpus' property we don't need break | |
888 | * linux loading process: kernel will handle it but linux will print | |
889 | * warning like "Timeout: CPU1 FAILED to comeup !!!". | |
890 | * So warn here about error, but return 0 like no error had occurred. | |
891 | */ | |
892 | if (ret) | |
893 | pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n", | |
894 | ret); | |
67482f57 AB |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
f665c14f EP |
899 | void board_jump_and_run(ulong entry, int zero, int arch, uint params) |
900 | { | |
901 | void (*kernel_entry)(int zero, int arch, uint params); | |
ada8affd | 902 | u32 cpu_start_reg; |
f665c14f EP |
903 | |
904 | kernel_entry = (void (*)(int, int, uint))entry; | |
905 | ||
ada8affd EP |
906 | /* Prepare CREG_CPU_START for kicking chosen CPUs */ |
907 | cpu_start_reg = prepare_cpu_ctart_reg(); | |
908 | ||
909 | /* In case of run without hsdk_init */ | |
910 | slave_cpu_set_boot_addr(entry); | |
911 | ||
912 | /* In case of run with hsdk_init */ | |
913 | for (u32 i = 0; i < NR_CPUS; i++) { | |
914 | env_core.entry[i].val = entry; | |
915 | env_core.entry[i].set = true; | |
916 | } | |
917 | /* sync cross_cpu struct as we updated core-entry variables */ | |
918 | sync_cross_cpu_data(); | |
919 | ||
920 | /* Kick chosen slave CPUs */ | |
921 | writel(cpu_start_reg, (void __iomem *)CREG_CPU_START); | |
922 | ||
923 | if (is_cpu_used(0)) | |
924 | kernel_entry(zero, arch, params); | |
f665c14f EP |
925 | } |
926 | ||
ada8affd EP |
927 | static int hsdk_go_prepare_and_run(void) |
928 | { | |
929 | /* Prepare CREG_CPU_START for kicking chosen CPUs */ | |
930 | u32 reg = prepare_cpu_ctart_reg(); | |
931 | ||
932 | if (env_common.halt_on_boot) | |
933 | printf("CPU will halt before application start, start application with debugger.\n"); | |
67482f57 | 934 | |
ada8affd EP |
935 | return hsdk_go_run(reg); |
936 | } | |
937 | ||
09140113 SG |
938 | static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc, |
939 | char *const argv[]) | |
67482f57 | 940 | { |
ada8affd | 941 | int ret; |
67482f57 | 942 | |
f0f84efe | 943 | if (board_mismatch()) { |
1be82afa | 944 | printf("ERR: U-Boot is not configured for this board!\n"); |
f0f84efe EP |
945 | return CMD_RET_FAILURE; |
946 | } | |
947 | ||
ada8affd EP |
948 | /* |
949 | * Check for 'halt' parameter. 'halt' = enter halt-mode just before | |
950 | * starting the application; can be used for debug. | |
951 | */ | |
952 | if (argc > 1) { | |
953 | env_common.halt_on_boot = !strcmp(argv[1], "halt"); | |
954 | if (!env_common.halt_on_boot) { | |
955 | pr_err("Unrecognised parameter: \'%s\'\n", argv[1]); | |
956 | return CMD_RET_FAILURE; | |
957 | } | |
958 | } | |
959 | ||
960 | ret = check_master_cpu_id(); | |
961 | if (ret) | |
962 | return ret; | |
963 | ||
964 | ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used); | |
965 | if (ret) | |
966 | return ret; | |
967 | ||
968 | /* sync cross_cpu struct as we updated core-entry variables */ | |
969 | sync_cross_cpu_data(); | |
970 | ||
971 | ret = hsdk_go_prepare_and_run(); | |
972 | ||
973 | return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; | |
974 | } | |
975 | ||
976 | U_BOOT_CMD( | |
977 | hsdk_go, 3, 0, do_hsdk_go, | |
978 | "Synopsys HSDK specific command", | |
979 | " - Boot stand-alone application on HSDK\n" | |
980 | "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n" | |
981 | ); | |
982 | ||
25998aed EP |
983 | /* |
984 | * We may simply use static variable here to store init status, but we also want | |
1be82afa | 985 | * to avoid the situation when we reload U-Boot via MDB after previous |
25998aed EP |
986 | * init is done but HW reset (board reset) isn't done. So let's store the |
987 | * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will | |
1be82afa | 988 | * survive after U-Boot is reloaded via MDB. |
25998aed EP |
989 | */ |
990 | #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY) | |
991 | /* must be equal to INIT_MARKER_REGISTER reset value */ | |
992 | #define INIT_MARKER_PENDING 0 | |
993 | ||
994 | static bool init_marker_get(void) | |
995 | { | |
996 | return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING; | |
997 | } | |
998 | ||
999 | static void init_mark_done(void) | |
1000 | { | |
1001 | writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER); | |
1002 | } | |
1003 | ||
09140113 SG |
1004 | static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc, |
1005 | char *const argv[]) | |
ada8affd | 1006 | { |
ada8affd EP |
1007 | int ret; |
1008 | ||
f0f84efe | 1009 | if (board_mismatch()) { |
1be82afa | 1010 | printf("ERR: U-Boot is not configured for this board!\n"); |
f0f84efe EP |
1011 | return CMD_RET_FAILURE; |
1012 | } | |
1013 | ||
ada8affd | 1014 | /* hsdk_init can be run only once */ |
25998aed | 1015 | if (init_marker_get()) { |
ada8affd EP |
1016 | printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n"); |
1017 | return CMD_RET_FAILURE; | |
1018 | } | |
1019 | ||
1020 | ret = prepare_cpus(); | |
1021 | if (!ret) | |
25998aed | 1022 | init_mark_done(); |
ada8affd EP |
1023 | |
1024 | return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; | |
1025 | } | |
1026 | ||
1027 | U_BOOT_CMD( | |
1028 | hsdk_init, 1, 0, do_hsdk_init, | |
1029 | "Synopsys HSDK specific command", | |
1030 | "- Init HSDK HW\n" | |
1031 | ); | |
1032 | ||
09140113 | 1033 | static int do_hsdk_clock_set(struct cmd_tbl *cmdtp, int flag, int argc, |
ada8affd EP |
1034 | char *const argv[]) |
1035 | { | |
1036 | int ret = 0; | |
1037 | ||
1038 | /* Strip off leading subcommand argument */ | |
1039 | argc--; | |
1040 | argv++; | |
1041 | ||
1042 | envs_cleanup_common(env_map_clock); | |
1043 | ||
1044 | if (!argc) { | |
1045 | printf("Set clocks to values specified in environment\n"); | |
1046 | ret = envs_read_common(env_map_clock); | |
1047 | } else { | |
1048 | printf("Set clocks to values specified in args\n"); | |
1049 | ret = args_envs_enumerate(env_map_clock, 2, argc, argv); | |
1050 | } | |
1051 | ||
1052 | if (ret) | |
1053 | return CMD_RET_FAILURE; | |
1054 | ||
1055 | ret = envs_validate_common(env_map_clock); | |
1056 | if (ret) | |
1057 | return CMD_RET_FAILURE; | |
1058 | ||
1059 | /* Setup clock tree HW */ | |
1060 | setup_clocks(); | |
1061 | ||
1062 | return CMD_RET_SUCCESS; | |
1063 | } | |
1064 | ||
09140113 | 1065 | static int do_hsdk_clock_get(struct cmd_tbl *cmdtp, int flag, int argc, |
ada8affd EP |
1066 | char *const argv[]) |
1067 | { | |
1068 | ulong rate; | |
1069 | ||
1070 | if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ)) | |
1071 | return CMD_RET_FAILURE; | |
1072 | ||
1073 | if (env_set_ulong("cpu_freq", rate)) | |
1074 | return CMD_RET_FAILURE; | |
1075 | ||
1076 | if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ)) | |
1077 | return CMD_RET_FAILURE; | |
1078 | ||
1079 | if (env_set_ulong("tun_freq", rate)) | |
1080 | return CMD_RET_FAILURE; | |
1081 | ||
1082 | if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ)) | |
1083 | return CMD_RET_FAILURE; | |
1084 | ||
1085 | if (env_set_ulong("axi_freq", rate)) | |
1086 | return CMD_RET_FAILURE; | |
1087 | ||
1088 | printf("Clock values are saved to environment\n"); | |
1089 | ||
1090 | return CMD_RET_SUCCESS; | |
1091 | } | |
1092 | ||
09140113 | 1093 | static int do_hsdk_clock_print(struct cmd_tbl *cmdtp, int flag, int argc, |
ada8affd EP |
1094 | char *const argv[]) |
1095 | { | |
1096 | /* Main clocks */ | |
1097 | soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1098 | soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1099 | soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1100 | soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1101 | ||
1102 | return CMD_RET_SUCCESS; | |
1103 | } | |
1104 | ||
09140113 | 1105 | static int do_hsdk_clock_print_all(struct cmd_tbl *cmdtp, int flag, int argc, |
ada8affd EP |
1106 | char *const argv[]) |
1107 | { | |
1108 | /* | |
1109 | * NOTE: as of today we don't use some peripherals like HDMI / EBI | |
1110 | * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll", | |
1111 | * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully | |
1112 | * functional and we can print their clocks if it is required | |
1113 | */ | |
1114 | ||
1115 | /* CPU clock domain */ | |
1116 | soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ); | |
1117 | soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1118 | printf("\n"); | |
1119 | ||
1120 | /* SYS clock domain */ | |
1121 | soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ); | |
1122 | soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1123 | soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1124 | soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1125 | soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1126 | soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ); | |
b84aa4cc EP |
1127 | if (is_board_match_runtime(T_BOARD_HSDK_4XD)) |
1128 | soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); | |
ada8affd | 1129 | soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ); |
da34c6b7 EP |
1130 | if (is_board_match_runtime(T_BOARD_HSDK)) { |
1131 | soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1132 | soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1133 | } | |
ada8affd EP |
1134 | soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ); |
1135 | soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1136 | soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1137 | soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1138 | soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1139 | /* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */ | |
1140 | soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1141 | printf("\n"); | |
1142 | ||
1143 | /* DDR clock domain */ | |
1144 | soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1145 | printf("\n"); | |
1146 | ||
1147 | /* HDMI clock domain */ | |
b84aa4cc EP |
1148 | if (is_board_match_runtime(T_BOARD_HSDK_4XD)) { |
1149 | soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); | |
1150 | soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1151 | printf("\n"); | |
1152 | } | |
ada8affd EP |
1153 | |
1154 | /* TUN clock domain */ | |
1155 | soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ); | |
1156 | soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1157 | soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ); | |
1158 | soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ); | |
d4ee5c39 EP |
1159 | if (is_board_match_runtime(T_BOARD_HSDK_4XD)) |
1160 | soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ); | |
ada8affd EP |
1161 | printf("\n"); |
1162 | ||
1163 | return CMD_RET_SUCCESS; | |
1164 | } | |
1165 | ||
09140113 | 1166 | struct cmd_tbl cmd_hsdk_clock[] = { |
ada8affd EP |
1167 | U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""), |
1168 | U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""), | |
1169 | U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""), | |
1170 | U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""), | |
1171 | }; | |
1172 | ||
09140113 SG |
1173 | static int do_hsdk_clock(struct cmd_tbl *cmdtp, int flag, int argc, |
1174 | char *const argv[]) | |
ada8affd | 1175 | { |
09140113 | 1176 | struct cmd_tbl *c; |
ada8affd EP |
1177 | |
1178 | if (argc < 2) | |
1179 | return CMD_RET_USAGE; | |
1180 | ||
1181 | /* Strip off leading 'hsdk_clock' command argument */ | |
1182 | argc--; | |
1183 | argv++; | |
1184 | ||
1185 | c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock)); | |
1186 | if (!c) | |
1187 | return CMD_RET_USAGE; | |
1188 | ||
1189 | return c->cmd(cmdtp, flag, argc, argv); | |
1190 | } | |
1191 | ||
1192 | U_BOOT_CMD( | |
1193 | hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock, | |
1194 | "Synopsys HSDK specific clock command", | |
1195 | "set - Set clock to values specified in environment / command line arguments\n" | |
1196 | "hsdk_clock get - Save clock values to environment\n" | |
1197 | "hsdk_clock print - Print main clock values to console\n" | |
1198 | "hsdk_clock print_all - Print all clock values to console\n" | |
1199 | ); | |
1200 | ||
1201 | /* init calls */ | |
1202 | int board_early_init_f(void) | |
1203 | { | |
1204 | /* | |
1205 | * Setup AXI apertures unconditionally as we want to have DDR | |
1206 | * in 0x00000000 region when we are kicking slave cpus. | |
1207 | */ | |
1208 | init_memory_bridge(); | |
1209 | ||
54858311 EP |
1210 | /* |
1211 | * Switch SDIO external ciu clock divider from default div-by-8 to | |
1212 | * minimum possible div-by-2. | |
1213 | */ | |
1214 | writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT); | |
1215 | ||
ada8affd EP |
1216 | return 0; |
1217 | } | |
1218 | ||
1219 | int board_early_init_r(void) | |
1220 | { | |
1221 | /* | |
1222 | * TODO: Init USB here to be able read environment from USB MSD. | |
1223 | * It can be done with usb_init() call. We can't do it right now | |
1224 | * due to brocken USB IP SW reset and lack of USB IP HW reset in | |
1225 | * linux kernel (if we init USB here we will break USB in linux) | |
1226 | */ | |
1227 | ||
1228 | /* | |
1229 | * Flush all d$ as we want to use uncached area with st.di / ld.di | |
1230 | * instructions and we don't want to have any dirty line in L1d$ or SL$ | |
1231 | * in this area. It is enough to flush all d$ once here as we access to | |
1232 | * uncached area with regular st (non .di) instruction only when we copy | |
1233 | * data during u-boot relocation. | |
1234 | */ | |
67482f57 | 1235 | flush_dcache_all(); |
ada8affd EP |
1236 | |
1237 | printf("Relocation Offset is: %08lx\n", gd->reloc_off); | |
1238 | ||
1239 | return 0; | |
67482f57 AB |
1240 | } |
1241 | ||
ada8affd | 1242 | int board_late_init(void) |
67482f57 | 1243 | { |
ada8affd EP |
1244 | /* |
1245 | * Populate environment with clock frequency values - | |
1246 | * run hsdk_clock get callback without uboot command run. | |
1247 | */ | |
1248 | do_hsdk_clock_get(NULL, 0, 0, NULL); | |
67482f57 | 1249 | |
ada8affd EP |
1250 | return 0; |
1251 | } | |
67482f57 | 1252 | |
6ef705b1 AB |
1253 | int checkboard(void) |
1254 | { | |
a8eb9b26 EP |
1255 | u32 reg; |
1256 | ||
f0f84efe EP |
1257 | printf("Board: Synopsys %s\n", board_name(get_board_type_runtime())); |
1258 | ||
1259 | if (board_mismatch()) | |
1be82afa | 1260 | printf("WARN: U-Boot is configured NOT for this board but for %s!\n", |
f0f84efe EP |
1261 | board_name(get_board_type_config())); |
1262 | ||
a8eb9b26 | 1263 | reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE; |
1be82afa | 1264 | printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled"); |
a8eb9b26 | 1265 | |
6ef705b1 AB |
1266 | return 0; |
1267 | }; |