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f4863a7a WD |
1 | /* |
2 | * VR4131 PCIU support code for TANBAC Evaluation board TB0229. | |
3 | * | |
4 | * (C) Masami Komiya <mkomiya@sonare.it> 2004 | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2, or (at | |
9 | * your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <common.h> | |
13 | #include <pci.h> | |
14 | #include <asm/addrspace.h> | |
15 | ||
7daf2ebe SK |
16 | #define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00) |
17 | #define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04) | |
18 | #define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08) | |
19 | #define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c) | |
20 | #define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10) | |
21 | #define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14) | |
22 | #define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18) | |
23 | #define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c) | |
24 | #define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24) | |
25 | #define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28) | |
26 | #define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c) | |
27 | #define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30) | |
28 | #define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34) | |
29 | #define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38) | |
30 | #define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c) | |
31 | #define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60) | |
32 | #define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) | |
33 | #define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) | |
34 | #define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) | |
35 | #define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) | |
36 | #define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) | |
37 | #define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) | |
38 | #define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) | |
39 | #define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) | |
40 | #define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) | |
41 | #define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10) | |
42 | #define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14) | |
43 | #define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18) | |
f4863a7a WD |
44 | |
45 | /*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ | |
46 | /*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ | |
47 | /*#define VR4122_PCI_HOST_BASE 0xa0000000 */ | |
48 | ||
49 | volatile unsigned int *pciconfigaddr; | |
50 | volatile unsigned int *pciconfigdata; | |
51 | ||
52 | #define PCI_ACCESS_READ 0 | |
53 | #define PCI_ACCESS_WRITE 1 | |
54 | ||
55 | /* | |
56 | * Access PCI Configuration Register for VR4131 | |
57 | */ | |
58 | ||
59 | static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg, | |
60 | u32 * data) | |
61 | { | |
62 | u32 bus; | |
63 | u32 device; | |
64 | ||
65 | bus = ((dev & 0xff0000) >> 16); | |
66 | device = ((dev & 0xf800) >> 11); | |
67 | ||
68 | if (bus == 0) { | |
69 | /* Type 0 Configuration */ | |
70 | *VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc)); | |
71 | } else { | |
72 | /* Type 1 Configuration */ | |
73 | *VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1); | |
74 | } | |
75 | ||
76 | if (access_type == PCI_ACCESS_WRITE) { | |
77 | *VR4131_PCICONFDREG = *data; | |
78 | } else { | |
79 | *data = *VR4131_PCICONFDREG; | |
80 | } | |
81 | ||
82 | return (0); | |
83 | } | |
84 | ||
85 | static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val) | |
86 | { | |
87 | u32 data; | |
88 | ||
89 | if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) | |
90 | return -1; | |
91 | ||
92 | *val = (data >> ((reg & 3) << 3)) & 0xff; | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | ||
98 | static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val) | |
99 | { | |
100 | u32 data; | |
101 | ||
102 | if (reg & 1) | |
103 | return -1; | |
104 | ||
105 | if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) | |
106 | return -1; | |
107 | ||
108 | *val = (data >> ((reg & 3) << 3)) & 0xffff; | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | ||
114 | static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg, | |
115 | u32 * val) | |
116 | { | |
117 | u32 data = 0; | |
118 | ||
119 | if (reg & 3) | |
120 | return -1; | |
121 | ||
122 | if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) | |
123 | return -1; | |
124 | ||
125 | *val = data; | |
126 | ||
127 | return (0); | |
128 | } | |
129 | ||
130 | static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val) | |
131 | { | |
132 | u32 data = 0; | |
133 | ||
134 | if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) | |
135 | return -1; | |
136 | ||
137 | data = (data & ~(0xff << ((reg & 3) << 3))) | (val << | |
138 | ((reg & 3) << 3)); | |
139 | ||
140 | if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) | |
141 | return -1; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | ||
147 | static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val) | |
148 | { | |
149 | u32 data = 0; | |
150 | ||
151 | if (reg & 1) | |
152 | return -1; | |
153 | ||
154 | if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) | |
155 | return -1; | |
156 | ||
157 | data = (data & ~(0xffff << ((reg & 3) << 3))) | (val << | |
158 | ((reg & 3) << 3)); | |
159 | ||
160 | if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) | |
161 | return -1; | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val) | |
167 | { | |
168 | u32 data; | |
169 | ||
170 | if (reg & 3) { | |
171 | return -1; | |
172 | } | |
173 | ||
174 | data = val; | |
175 | ||
176 | if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) | |
177 | return -1; | |
178 | ||
179 | return (0); | |
180 | } | |
181 | ||
182 | ||
183 | /* | |
184 | * Initialize VR4131 PCIU | |
185 | */ | |
186 | ||
187 | vr4131_pciu_init () | |
188 | { | |
189 | /* PCI clock */ | |
190 | *VR4131_PCICLKSELREG = 0x00000002; | |
191 | ||
192 | /* PCI memory and I/O space */ | |
193 | *VR4131_PCIMMAW1REG = 0x100F9010; | |
194 | *VR4131_PCIMMAW2REG = 0x140FD014; | |
195 | *VR4131_PCIMIOAWREG = 0x160FD000; | |
196 | ||
197 | /* Target memory window */ | |
198 | *VR4131_PCITAW1REG = 0x00081000; /* 64MB */ | |
199 | *VR4131_PCITAW2REG = 0x00000000; | |
200 | ||
201 | *VR4131_MAILBAREG = 0UL; | |
202 | *VR4131_PCIMBA1REG = 0UL; | |
203 | ||
204 | *VR4131_PCITRDYREG = 0x00008004; | |
205 | ||
206 | *VR4131_PCIENREG = 0x00000004; /* PCI enable */ | |
207 | *VR4131_COMMANDREG = 0x02000007; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Initialize Module | |
212 | */ | |
213 | ||
214 | void init_vr4131_pci (struct pci_controller *hose) | |
215 | { | |
216 | hose->first_busno = 0; | |
217 | hose->last_busno = 0xff; | |
218 | ||
219 | vr4131_pciu_init (); /* Initialize VR4131 PCIU */ | |
220 | ||
221 | /* PCI memory space #1 */ | |
222 | pci_set_region (hose->regions + 0, | |
223 | 0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM); | |
224 | ||
225 | /* PCI memory space #2 */ | |
226 | pci_set_region (hose->regions + 1, | |
227 | 0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM); | |
228 | ||
229 | ||
230 | /* PCI I/O space */ | |
231 | pci_set_region (hose->regions + 2, | |
232 | 0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO); | |
233 | ||
234 | /* System memory space */ | |
235 | pci_set_region (hose->regions + 3, | |
236 | 0x00000000, | |
237 | 0x80000000, | |
238 | 0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY); | |
239 | ||
240 | hose->region_count = 4; | |
241 | ||
242 | hose->read_byte = vr4131_pci_read_config_byte; | |
243 | hose->read_word = vr4131_pci_read_config_word; | |
244 | hose->read_dword = vr4131_pci_read_config_dword; | |
245 | hose->write_byte = vr4131_pci_write_config_byte; | |
246 | hose->write_word = vr4131_pci_write_config_word; | |
247 | hose->write_dword = vr4131_pci_write_config_dword; | |
248 | ||
249 | pci_register_hose (hose); | |
250 | ||
251 | hose->last_busno = pci_hose_scan (hose); | |
252 | ||
253 | return; | |
254 | } |