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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1541d7a6 VM |
2 | /* |
3 | * Copyright (C) 2017 NXP Semiconductors | |
1541d7a6 VM |
4 | */ |
5 | ||
5255932f | 6 | #include <init.h> |
90526e9f | 7 | #include <net.h> |
1541d7a6 VM |
8 | #include <asm/arch/clock.h> |
9 | #include <asm/arch/crm_regs.h> | |
10 | #include <asm/arch/imx-regs.h> | |
11 | #include <asm/arch/mx7-pins.h> | |
12 | #include <asm/arch/sys_proto.h> | |
13 | #include <asm/gpio.h> | |
552a848e SB |
14 | #include <asm/mach-imx/iomux-v3.h> |
15 | #include <asm/mach-imx/mxc_i2c.h> | |
1541d7a6 VM |
16 | #include <asm/io.h> |
17 | #include <common.h> | |
1541d7a6 VM |
18 | #include <i2c.h> |
19 | #include <miiphy.h> | |
1541d7a6 VM |
20 | #include <power/pmic.h> |
21 | #include <power/pfuze3000_pmic.h> | |
22 | #include "../../freescale/common/pfuze.h" | |
23 | ||
24 | DECLARE_GLOBAL_DATA_PTR; | |
25 | ||
26 | #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ | |
27 | PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) | |
28 | ||
1541d7a6 VM |
29 | #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
30 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) | |
31 | ||
32 | #ifdef CONFIG_SYS_I2C_MXC | |
33 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | |
9e3c0174 | 34 | |
1541d7a6 VM |
35 | /* I2C4 for PMIC */ |
36 | static struct i2c_pads_info i2c_pad_info4 = { | |
37 | .scl = { | |
38 | .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, | |
39 | .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, | |
40 | .gp = IMX_GPIO_NR(6, 16), | |
41 | }, | |
42 | .sda = { | |
43 | .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, | |
44 | .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, | |
45 | .gp = IMX_GPIO_NR(6, 17), | |
46 | }, | |
47 | }; | |
48 | #endif | |
49 | ||
50 | int dram_init(void) | |
51 | { | |
d5b7177f | 52 | gd->ram_size = imx_ddr_size(); |
1541d7a6 | 53 | |
1d3b852e JN |
54 | /* Subtract the defined OPTEE runtime firmware length */ |
55 | #ifdef CONFIG_OPTEE_TZDRAM_SIZE | |
56 | gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE; | |
57 | #endif | |
58 | ||
1541d7a6 VM |
59 | return 0; |
60 | } | |
61 | ||
62 | #ifdef CONFIG_POWER | |
63 | #define I2C_PMIC 3 | |
64 | int power_init_board(void) | |
65 | { | |
66 | struct pmic *p; | |
67 | int ret; | |
68 | unsigned int reg, rev_id; | |
69 | ||
70 | ret = power_pfuze3000_init(I2C_PMIC); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | p = pmic_get("PFUZE3000"); | |
75 | ret = pmic_probe(p); | |
c72a2370 JN |
76 | if (ret) { |
77 | printf("Warning: Cannot find PMIC PFUZE3000\n"); | |
78 | printf("\tPower consumption is not optimized.\n"); | |
79 | return 0; | |
80 | } | |
1541d7a6 VM |
81 | |
82 | pmic_reg_read(p, PFUZE3000_DEVICEID, ®); | |
83 | pmic_reg_read(p, PFUZE3000_REVID, &rev_id); | |
84 | printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); | |
85 | ||
86 | /* disable Low Power Mode during standby mode */ | |
87 | pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); | |
88 | reg |= 0x1; | |
89 | pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); | |
90 | ||
91 | /* SW1A/1B mode set to APS/APS */ | |
92 | reg = 0x8; | |
93 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); | |
94 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); | |
95 | ||
96 | /* SW1A/1B standby voltage set to 1.025V */ | |
97 | reg = 0xd; | |
98 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); | |
99 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); | |
100 | ||
101 | /* decrease SW1B normal voltage to 0.975V */ | |
102 | pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); | |
103 | reg &= ~0x1f; | |
104 | reg |= PFUZE3000_SW1AB_SETP(975); | |
105 | pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); | |
106 | ||
107 | return 0; | |
108 | } | |
109 | #endif | |
110 | ||
111 | static iomux_v3_cfg_t const wdog_pads[] = { | |
112 | MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
113 | }; | |
114 | ||
115 | static iomux_v3_cfg_t const uart5_pads[] = { | |
116 | MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
117 | MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
118 | }; | |
119 | ||
1541d7a6 | 120 | #ifdef CONFIG_FEC_MXC |
1541d7a6 VM |
121 | static int setup_fec(void) |
122 | { | |
123 | struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs | |
124 | = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
125 | ||
126 | /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */ | |
127 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], | |
128 | (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | | |
129 | IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); | |
130 | ||
8590786a | 131 | return set_clk_enet(ENET_125MHZ); |
1541d7a6 VM |
132 | } |
133 | ||
134 | int board_phy_config(struct phy_device *phydev) | |
135 | { | |
136 | unsigned short val; | |
137 | ||
138 | /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ | |
139 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); | |
140 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); | |
141 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); | |
142 | ||
143 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); | |
144 | val &= 0xffe7; | |
145 | val |= 0x18; | |
146 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); | |
147 | ||
148 | /* introduce tx clock delay */ | |
149 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); | |
150 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); | |
151 | val |= 0x0100; | |
152 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); | |
153 | ||
154 | if (phydev->drv->config) | |
155 | phydev->drv->config(phydev); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | #endif | |
160 | ||
161 | static void setup_iomux_uart(void) | |
162 | { | |
163 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); | |
164 | } | |
165 | ||
1541d7a6 VM |
166 | int board_early_init_f(void) |
167 | { | |
168 | setup_iomux_uart(); | |
169 | ||
170 | #ifdef CONFIG_SYS_I2C_MXC | |
171 | setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); | |
172 | #endif | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
d89f0a88 | 177 | #ifdef CONFIG_DM_VIDEO |
9e3c0174 FE |
178 | void setup_lcd(void) |
179 | { | |
d5f3a470 JO |
180 | gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness"); |
181 | gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable"); | |
9e3c0174 FE |
182 | /* Set Brightness to high */ |
183 | gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); | |
184 | /* Set LCD enable to high */ | |
185 | gpio_direction_output(IMX_GPIO_NR(1, 6) , 1); | |
186 | } | |
187 | #endif | |
188 | ||
1541d7a6 VM |
189 | int board_init(void) |
190 | { | |
191 | /* address of boot parameters */ | |
192 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
193 | ||
d89f0a88 | 194 | #ifdef CONFIG_DM_VIDEO |
9e3c0174 FE |
195 | setup_lcd(); |
196 | #endif | |
1541d7a6 VM |
197 | #ifdef CONFIG_FEC_MXC |
198 | setup_fec(); | |
199 | #endif | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | int board_late_init(void) | |
205 | { | |
206 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; | |
207 | ||
208 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); | |
209 | ||
210 | set_wdog_reset(wdog); | |
211 | ||
212 | /* | |
213 | * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), | |
214 | * since we use PMIC_PWRON to reset the board. | |
215 | */ | |
216 | clrsetbits_le16(&wdog->wcr, 0, 0x10); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | int checkboard(void) | |
222 | { | |
223 | puts("Board: i.MX7D PICOSOM\n"); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
780e31e9 FE |
228 | static iomux_v3_cfg_t const usb_otg2_pads[] = { |
229 | MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), | |
230 | }; | |
231 | ||
232 | int board_ehci_hcd_init(int port) | |
233 | { | |
234 | switch (port) { | |
235 | case 0: | |
236 | break; | |
237 | case 1: | |
238 | imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, | |
239 | ARRAY_SIZE(usb_otg2_pads)); | |
240 | break; | |
241 | default: | |
242 | return -EINVAL; | |
243 | } | |
244 | return 0; | |
245 | } | |
246 |