[thirdparty/u-boot.git] / board / technologic / ts4800 / ts4800.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2015 Savoir-faire Linux Inc.
 *
 * Derived from MX51EVK code by
 *   Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
#include <mmc.h>
#include <input.h>
#include <fsl_esdhc_imx.h>
#include <mc13892.h>

#include <malloc.h>
#include <netdev.h>
#include <phy.h>
#include "ts4800.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC2_BASE_ADDR},
};
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

u32 get_board_rev(void)
{
	u32 rev = get_cpu_rev();
	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
		rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
	return rev;
}

#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		MX51_PAD_UART1_RXD__UART1_RXD,
		MX51_PAD_UART1_TXD__UART1_TXD,
		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
				PAD_CTL_HYS |
				PAD_CTL_PUS_22K_UP |
				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
		MX51_PAD_EIM_EB3__FEC_RDATA1,
		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
		MX51_PAD_EIM_CS3__FEC_RDATA3,
		MX51_PAD_NANDF_CS2__FEC_TX_ER,
		MX51_PAD_EIM_CS5__FEC_CRS,
		MX51_PAD_EIM_CS4__FEC_RX_ER,
		/* PAD used on TS4800 */
		MX51_PAD_DI2_PIN2__FEC_MDC,
		MX51_PAD_DISP2_DAT14__FEC_RDAT0,
		MX51_PAD_DISP2_DAT10__FEC_COL,
		MX51_PAD_DISP2_DAT11__FEC_RXCLK,
		MX51_PAD_DISP2_DAT15__FEC_TDAT0,
		MX51_PAD_DISP2_DAT6__FEC_TDAT1,
		MX51_PAD_DISP2_DAT7__FEC_TDAT2,
		MX51_PAD_DISP2_DAT8__FEC_TDAT3,
		MX51_PAD_DISP2_DAT9__FEC_TX_EN,
		MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
		MX51_PAD_DISP2_DAT12__FEC_RX_DV,
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
						NO_PAD_CTRL));
	gpio_direction_input(IMX_GPIO_NR(1, 0));
	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
						NO_PAD_CTRL));
	gpio_direction_input(IMX_GPIO_NR(1, 6));

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
	else
		ret = !gpio_get_value(IMX_GPIO_NR(1, 6));

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
	};

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));

	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

/*
 * Read the MAC address from FEC's registers PALR PAUR.
 * User is supposed to configure these registers when MAC address is known
 * from another source (fuse), but on TS4800, MAC address is not fused and
 * the bootrom configure these registers on startup.
 */
static int fec_get_mac_from_register(uint32_t base_addr)
{
	unsigned char ethaddr[6];
	u32 reg_mac[2];
	int i;

	reg_mac[0] = in_be32(base_addr + 0xE4);
	reg_mac[1] = in_be32(base_addr + 0xE8);

	for(i = 0; i < 6; i++)
		ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;

	if (is_valid_ethaddr(ethaddr)) {
		eth_env_set_enetaddr("ethaddr", ethaddr);
		return 0;
	}

	return -1;
}

#define TS4800_GPIO_FEC_PHY_RES         IMX_GPIO_NR(2, 14)
int board_eth_init(bd_t *bd)
{
	int dev_id = -1;
	int phy_id = 0xFF;
	uint32_t addr = IMX_FEC_BASE;

	uint32_t base_mii;
	struct mii_dev *bus = NULL;
	struct phy_device *phydev = NULL;
	int ret;

	/* reset FEC phy */
	imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
	gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
	mdelay(1);
	gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
	mdelay(1);

	base_mii = addr;
	debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
	bus = fec_get_miibus(base_mii, dev_id);
	if (!bus)
		return -ENOMEM;

	phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
	if (!phydev) {
		free(bus);
		return -ENOMEM;
	}

	if (fec_get_mac_from_register(addr))
		printf("eth_init: failed to get MAC address\n");

	ret = fec_probe(bd, dev_id, addr, bus, phydev);
	if (ret) {
		free(phydev);
		free(bus);
	}

	return ret;
}

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int checkboard(void)
{
	puts("Board: TS4800\n");

	return 0;
}

void hw_watchdog_reset(void)
{
	struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
	/* feed the watchdog for another 10s */
	writew(0x2, &wtd->feed);
}

void hw_watchdog_init(void)
{
	return;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9ee16897 LQ	2	/*
	3	* (C) Copyright 2015 Savoir-faire Linux Inc.
	4	*
	5	* Derived from MX51EVK code by
	6	* Freescale Semiconductor, Inc.
9ee16897 LQ	7	*/
	8
	9	#include <common.h>
9b4a205f	10	#include <init.h>
90526e9f	11	#include <net.h>
9ee16897 LQ	12	#include <asm/io.h>
	13	#include <asm/gpio.h>
	14	#include <asm/arch/imx-regs.h>
	15	#include <asm/arch/iomux-mx51.h>
9fb625ce	16	#include <env.h>
1221ce45	17	#include <linux/errno.h>
9ee16897 LQ	18	#include <asm/arch/sys_proto.h>
	19	#include <asm/arch/crm_regs.h>
	20	#include <asm/arch/clock.h>
552a848e	21	#include <asm/mach-imx/mx5_video.h>
9ee16897	22	#include <mmc.h>
7594c51a	23	#include <input.h>
e37ac717	24	#include <fsl_esdhc_imx.h>
9ee16897 LQ	25	#include <mc13892.h>
9ee16897 LQ	26
f3488bb3 DR	27	#include <malloc.h>
	28	#include <netdev.h>
	29	#include <phy.h>
9ee16897 LQ	30	#include "ts4800.h"
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
e37ac717	34	#ifdef CONFIG_FSL_ESDHC_IMX
9ee16897 LQ	35	struct fsl_esdhc_cfg esdhc_cfg[2] = {
	36	{MMC_SDHC1_BASE_ADDR},
	37	{MMC_SDHC2_BASE_ADDR},
	38	};
	39	#endif
	40
	41	int dram_init(void)
	42	{
	43	/* dram_init must store complete ramsize in gd->ram_size */
	44	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	45	PHYS_SDRAM_1_SIZE);
	46	return 0;
	47	}
	48
	49	u32 get_board_rev(void)
	50	{
	51	u32 rev = get_cpu_rev();
	52	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
	53	rev \|= BOARD_REV_2_0 << BOARD_VER_OFFSET;
	54	return rev;
	55	}
	56
	57	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_DSE_HIGH)
	58
	59	static void setup_iomux_uart(void)
	60	{
	61	static const iomux_v3_cfg_t uart_pads[] = {
	62	MX51_PAD_UART1_RXD__UART1_RXD,
	63	MX51_PAD_UART1_TXD__UART1_TXD,
	64	NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
	65	NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
	66	};
	67
	68	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	69	}
	70
f3488bb3 DR	71	static void setup_iomux_fec(void)
	72	{
	73	static const iomux_v3_cfg_t fec_pads[] = {
	74	NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
	75	PAD_CTL_HYS \|
	76	PAD_CTL_PUS_22K_UP \|
	77	PAD_CTL_DSE_HIGH \| PAD_CTL_SRE_FAST),
	78	MX51_PAD_EIM_EB3__FEC_RDATA1,
	79	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
	80	MX51_PAD_EIM_CS3__FEC_RDATA3,
	81	MX51_PAD_NANDF_CS2__FEC_TX_ER,
	82	MX51_PAD_EIM_CS5__FEC_CRS,
	83	MX51_PAD_EIM_CS4__FEC_RX_ER,
	84	/* PAD used on TS4800 */
	85	MX51_PAD_DI2_PIN2__FEC_MDC,
	86	MX51_PAD_DISP2_DAT14__FEC_RDAT0,
	87	MX51_PAD_DISP2_DAT10__FEC_COL,
	88	MX51_PAD_DISP2_DAT11__FEC_RXCLK,
	89	MX51_PAD_DISP2_DAT15__FEC_TDAT0,
	90	MX51_PAD_DISP2_DAT6__FEC_TDAT1,
	91	MX51_PAD_DISP2_DAT7__FEC_TDAT2,
	92	MX51_PAD_DISP2_DAT8__FEC_TDAT3,
	93	MX51_PAD_DISP2_DAT9__FEC_TX_EN,
	94	MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
	95	MX51_PAD_DISP2_DAT12__FEC_RX_DV,
	96	};
	97
	98	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	99	}
	100
e37ac717	101	#ifdef CONFIG_FSL_ESDHC_IMX
9ee16897 LQ	102	int board_mmc_getcd(struct mmc *mmc)
	103	{
	104	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	105	int ret;
	106
	107	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
	108	NO_PAD_CTRL));
	109	gpio_direction_input(IMX_GPIO_NR(1, 0));
	110	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
	111	NO_PAD_CTRL));
	112	gpio_direction_input(IMX_GPIO_NR(1, 6));
	113
	114	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
	115	ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
	116	else
	117	ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
	118
	119	return ret;
	120	}
	121
	122	int board_mmc_init(bd_t *bis)
	123	{
	124	static const iomux_v3_cfg_t sd1_pads[] = {
	125	NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX \|
	126	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	127	NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX \|
	128	PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	129	NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX \|
	130	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	131	NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX \|
	132	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	133	NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX \|
	134	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	135	NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX \|
	136	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SRE_FAST),
	137	NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
	138	NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
	139	};
	140
	141	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	142
	143	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
	144
	145	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
	146	}
	147	#endif
	148
	149	int board_early_init_f(void)
	150	{
	151	setup_iomux_uart();
f3488bb3	152	setup_iomux_fec();
9ee16897 LQ	153
	154	return 0;
	155	}
	156
	157	int board_init(void)
	158	{
	159	/* address of boot parameters */
	160	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	161
	162	return 0;
	163	}
	164
f3488bb3 DR	165	/*
	166	* Read the MAC address from FEC's registers PALR PAUR.
	167	* User is supposed to configure these registers when MAC address is known
	168	* from another source (fuse), but on TS4800, MAC address is not fused and
	169	* the bootrom configure these registers on startup.
	170	*/
	171	static int fec_get_mac_from_register(uint32_t base_addr)
	172	{
	173	unsigned char ethaddr[6];
	174	u32 reg_mac[2];
	175	int i;
	176
	177	reg_mac[0] = in_be32(base_addr + 0xE4);
	178	reg_mac[1] = in_be32(base_addr + 0xE8);
	179
	180	for(i = 0; i < 6; i++)
	181	ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
	182
	183	if (is_valid_ethaddr(ethaddr)) {
fd1e959e	184	eth_env_set_enetaddr("ethaddr", ethaddr);
f3488bb3 DR	185	return 0;
	186	}
	187
	188	return -1;
	189	}
	190
	191	#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
	192	int board_eth_init(bd_t *bd)
	193	{
	194	int dev_id = -1;
	195	int phy_id = 0xFF;
	196	uint32_t addr = IMX_FEC_BASE;
	197
	198	uint32_t base_mii;
	199	struct mii_dev *bus = NULL;
	200	struct phy_device *phydev = NULL;
	201	int ret;
	202
	203	/* reset FEC phy */
	204	imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
	205	gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
	206	mdelay(1);
	207	gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
	208	mdelay(1);
	209
	210	base_mii = addr;
	211	debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
	212	bus = fec_get_miibus(base_mii, dev_id);
	213	if (!bus)
	214	return -ENOMEM;
	215
	216	phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
	217	if (!phydev) {
	218	free(bus);
	219	return -ENOMEM;
	220	}
	221
	222	if (fec_get_mac_from_register(addr))
	223	printf("eth_init: failed to get MAC address\n");
	224
	225	ret = fec_probe(bd, dev_id, addr, bus, phydev);
	226	if (ret) {
	227	free(phydev);
	228	free(bus);
	229	}
	230
	231	return ret;
	232	}
	233
9ee16897 LQ	234	/*
	235	* Do not overwrite the console
	236	* Use always serial for U-Boot console
	237	*/
	238	int overwrite_console(void)
	239	{
	240	return 1;
	241	}
	242
	243	int checkboard(void)
	244	{
	245	puts("Board: TS4800\n");
	246
	247	return 0;
	248	}
	249
	250	void hw_watchdog_reset(void)
	251	{
	252	struct ts4800_wtd_regs wtd = (struct ts4800_wtd_regs ) (TS4800_SYSCON_BASE + 0xE);
	253	/* feed the watchdog for another 10s */
	254	writew(0x2, &wtd->feed);
	255	}
	256
	257	void hw_watchdog_init(void)
	258	{
	259	return;
	260	}