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e363426e PK |
1 | /* |
2 | * board.h | |
3 | * | |
4 | * TI AM335x boards information header | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
e363426e PK |
9 | */ |
10 | ||
11 | #ifndef _BOARD_H_ | |
12 | #define _BOARD_H_ | |
13 | ||
8c17cbdf JS |
14 | /** |
15 | * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and | |
16 | * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame | |
17 | * Synchronization Lost errors. The values are the biggest that work | |
18 | * reliably with offered video modes and the memory subsystem on the | |
19 | * boards. These register have are briefly documented in "7.3.3.5.2 | |
20 | * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and | |
21 | * REG_COS_COUNT_2 do not have any effect on current versions of | |
22 | * AM335x. | |
23 | */ | |
24 | #define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414 | |
25 | #define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d | |
26 | ||
770e68c0 NM |
27 | static inline int board_is_bone(void) |
28 | { | |
29 | return board_ti_is("A335BONE"); | |
30 | } | |
e363426e | 31 | |
770e68c0 | 32 | static inline int board_is_bone_lt(void) |
ace4275e | 33 | { |
770e68c0 | 34 | return board_ti_is("A335BNLT"); |
ace4275e TR |
35 | } |
36 | ||
770e68c0 | 37 | static inline int board_is_bbg1(void) |
ace4275e | 38 | { |
770e68c0 | 39 | return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4); |
ace4275e TR |
40 | } |
41 | ||
9f7923c7 LV |
42 | static inline int board_is_beaglebonex(void) |
43 | { | |
44 | return board_is_bone() || board_is_bone_lt() || board_is_bbg1(); | |
45 | } | |
46 | ||
770e68c0 | 47 | static inline int board_is_evm_sk(void) |
ace4275e | 48 | { |
770e68c0 | 49 | return board_ti_is("A335X_SK"); |
ace4275e TR |
50 | } |
51 | ||
770e68c0 | 52 | static inline int board_is_idk(void) |
ace4275e | 53 | { |
770e68c0 | 54 | return !strncmp(board_ti_get_config(), "SKU#02", 6); |
ace4275e TR |
55 | } |
56 | ||
770e68c0 | 57 | static inline int board_is_gp_evm(void) |
ace4275e | 58 | { |
770e68c0 | 59 | return board_ti_is("A33515BB"); |
ace4275e TR |
60 | } |
61 | ||
770e68c0 | 62 | static inline int board_is_evm_15_or_later(void) |
ace4275e | 63 | { |
770e68c0 NM |
64 | return (board_is_gp_evm() && |
65 | strncmp("1.5", board_ti_get_rev(), 3) <= 0); | |
ace4275e TR |
66 | } |
67 | ||
a9643324 LV |
68 | static inline int board_is_icev2(void) |
69 | { | |
70 | return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1); | |
71 | } | |
72 | ||
e363426e PK |
73 | /* |
74 | * We have three pin mux functions that must exist. We must be able to enable | |
75 | * uart0, for initial output and i2c0 to read the main EEPROM. We then have a | |
76 | * main pinmux function that can be overridden to enable all other pinmux that | |
77 | * is required on the board. | |
78 | */ | |
79 | void enable_uart0_pin_mux(void); | |
6422b70b AB |
80 | void enable_uart1_pin_mux(void); |
81 | void enable_uart2_pin_mux(void); | |
82 | void enable_uart3_pin_mux(void); | |
83 | void enable_uart4_pin_mux(void); | |
84 | void enable_uart5_pin_mux(void); | |
e363426e | 85 | void enable_i2c0_pin_mux(void); |
770e68c0 | 86 | void enable_board_pin_mux(void); |
e363426e | 87 | #endif |