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1e4ad74b FB |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com | |
3 | * | |
4 | * Author: Felipe Balbi <balbi@ti.com> | |
5 | * | |
6 | * Based on board/ti/dra7xx/evm.c | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <palmas.h> | |
13 | #include <sata.h> | |
14 | #include <usb.h> | |
15 | #include <asm/omap_common.h> | |
17c29873 | 16 | #include <asm/omap_sec_common.h> |
1e4ad74b | 17 | #include <asm/emif.h> |
334bbb38 LV |
18 | #include <asm/gpio.h> |
19 | #include <asm/arch/gpio.h> | |
1e4ad74b | 20 | #include <asm/arch/clock.h> |
f91e0c4c | 21 | #include <asm/arch/dra7xx_iodelay.h> |
1e4ad74b FB |
22 | #include <asm/arch/sys_proto.h> |
23 | #include <asm/arch/mmc_host_def.h> | |
24 | #include <asm/arch/sata.h> | |
25 | #include <asm/arch/gpio.h> | |
7c379aaa | 26 | #include <asm/arch/omap.h> |
1e4ad74b | 27 | #include <environment.h> |
7c379aaa KVA |
28 | #include <usb.h> |
29 | #include <linux/usb/gadget.h> | |
30 | #include <dwc3-uboot.h> | |
31 | #include <dwc3-omap-uboot.h> | |
32 | #include <ti-usb-phy-uboot.h> | |
1e4ad74b | 33 | |
212f96f6 | 34 | #include "../common/board_detect.h" |
1e4ad74b FB |
35 | #include "mux_data.h" |
36 | ||
212f96f6 | 37 | #define board_is_x15() board_ti_is("BBRDX15_") |
f7f9f6be LV |
38 | #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \ |
39 | (strncmp("B.10", board_ti_get_rev(), 3) <= 0)) | |
212f96f6 | 40 | #define board_is_am572x_evm() board_ti_is("AM572PM_") |
bf43ce6c NM |
41 | #define board_is_am572x_evm_reva3() \ |
42 | (board_ti_is("AM572PM_") && \ | |
43 | (strncmp("A.30", board_ti_get_rev(), 3) <= 0)) | |
c020d355 | 44 | #define board_is_am572x_idk() board_ti_is("AM572IDK") |
4d8397c6 | 45 | #define board_is_am571x_idk() board_ti_is("AM571IDK") |
212f96f6 | 46 | |
1e4ad74b FB |
47 | #ifdef CONFIG_DRIVER_TI_CPSW |
48 | #include <cpsw.h> | |
49 | #endif | |
50 | ||
51 | DECLARE_GLOBAL_DATA_PTR; | |
52 | ||
37611052 | 53 | #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22) |
334bbb38 LV |
54 | /* GPIO 7_11 */ |
55 | #define GPIO_DDR_VTT_EN 203 | |
56 | ||
fcb18524 NM |
57 | /* Touch screen controller to identify the LCD */ |
58 | #define OSD_TS_FT_BUS_ADDRESS 0 | |
59 | #define OSD_TS_FT_CHIP_ADDRESS 0x38 | |
60 | #define OSD_TS_FT_REG_ID 0xA3 | |
61 | /* | |
62 | * Touchscreen IDs for various OSD panels | |
63 | * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf | |
64 | */ | |
65 | /* Used on newer osd101t2587 Panels */ | |
66 | #define OSD_TS_FT_ID_5x46 0x54 | |
67 | /* Used on older osd101t2045 Panels */ | |
68 | #define OSD_TS_FT_ID_5606 0x08 | |
69 | ||
212f96f6 KS |
70 | #define SYSINFO_BOARD_NAME_MAX_LEN 45 |
71 | ||
385d3632 K |
72 | #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB |
73 | #define TPS65903X_PAD2_POWERHOLD_MASK 0x20 | |
74 | ||
1e4ad74b | 75 | const struct omap_sysinfo sysinfo = { |
212f96f6 | 76 | "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" |
1e4ad74b FB |
77 | }; |
78 | ||
79 | static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { | |
80 | .dmm_lisa_map_3 = 0x80740300, | |
81 | .is_ma_present = 0x1 | |
82 | }; | |
83 | ||
4d8397c6 SK |
84 | static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { |
85 | .dmm_lisa_map_3 = 0x80640100, | |
86 | .is_ma_present = 0x1 | |
87 | }; | |
88 | ||
1e4ad74b FB |
89 | void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) |
90 | { | |
4d8397c6 SK |
91 | if (board_is_am571x_idk()) |
92 | *dmm_lisa_regs = &am571x_idk_lisa_regs; | |
93 | else | |
94 | *dmm_lisa_regs = &beagle_x15_lisa_regs; | |
1e4ad74b FB |
95 | } |
96 | ||
97 | static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { | |
eafd4644 K |
98 | .sdram_config_init = 0x61851b32, |
99 | .sdram_config = 0x61851b32, | |
100 | .sdram_config2 = 0x08000000, | |
101 | .ref_ctrl = 0x000040F1, | |
102 | .ref_ctrl_final = 0x00001035, | |
103 | .sdram_tim1 = 0xcccf36ab, | |
104 | .sdram_tim2 = 0x308f7fda, | |
105 | .sdram_tim3 = 0x409f88a8, | |
106 | .read_idle_ctrl = 0x00050000, | |
107 | .zq_config = 0x5007190b, | |
108 | .temp_alert_config = 0x00000000, | |
109 | .emif_ddr_phy_ctlr_1_init = 0x0024400b, | |
110 | .emif_ddr_phy_ctlr_1 = 0x0e24400b, | |
111 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
112 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
113 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
114 | .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, | |
115 | .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, | |
116 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
117 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
118 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
119 | .emif_rd_wr_exec_thresh = 0x00000305 | |
1e4ad74b FB |
120 | }; |
121 | ||
6213db78 | 122 | /* Ext phy ctrl regs 1-35 */ |
1e4ad74b | 123 | static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { |
6213db78 | 124 | 0x10040100, |
11e2b043 LV |
125 | 0x00910091, |
126 | 0x00950095, | |
127 | 0x009B009B, | |
128 | 0x009E009E, | |
129 | 0x00980098, | |
1e4ad74b | 130 | 0x00340034, |
1e4ad74b | 131 | 0x00350035, |
11e2b043 LV |
132 | 0x00340034, |
133 | 0x00310031, | |
134 | 0x00340034, | |
135 | 0x007F007F, | |
136 | 0x007F007F, | |
137 | 0x007F007F, | |
138 | 0x007F007F, | |
139 | 0x007F007F, | |
140 | 0x00480048, | |
141 | 0x004A004A, | |
142 | 0x00520052, | |
143 | 0x00550055, | |
144 | 0x00500050, | |
1e4ad74b FB |
145 | 0x00000000, |
146 | 0x00600020, | |
6213db78 | 147 | 0x40011080, |
1e4ad74b | 148 | 0x08102040, |
11e2b043 LV |
149 | 0x0, |
150 | 0x0, | |
151 | 0x0, | |
152 | 0x0, | |
153 | 0x0, | |
496edffd LV |
154 | 0x0, |
155 | 0x0, | |
156 | 0x0, | |
157 | 0x0, | |
158 | 0x0 | |
1e4ad74b FB |
159 | }; |
160 | ||
161 | static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { | |
eafd4644 K |
162 | .sdram_config_init = 0x61851b32, |
163 | .sdram_config = 0x61851b32, | |
164 | .sdram_config2 = 0x08000000, | |
165 | .ref_ctrl = 0x000040F1, | |
166 | .ref_ctrl_final = 0x00001035, | |
167 | .sdram_tim1 = 0xcccf36b3, | |
168 | .sdram_tim2 = 0x308f7fda, | |
169 | .sdram_tim3 = 0x407f88a8, | |
170 | .read_idle_ctrl = 0x00050000, | |
171 | .zq_config = 0x5007190b, | |
172 | .temp_alert_config = 0x00000000, | |
173 | .emif_ddr_phy_ctlr_1_init = 0x0024400b, | |
174 | .emif_ddr_phy_ctlr_1 = 0x0e24400b, | |
175 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
176 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
177 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
178 | .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, | |
179 | .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, | |
180 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
181 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
182 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
183 | .emif_rd_wr_exec_thresh = 0x00000305 | |
1e4ad74b FB |
184 | }; |
185 | ||
186 | static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { | |
6213db78 | 187 | 0x10040100, |
11e2b043 LV |
188 | 0x00910091, |
189 | 0x00950095, | |
190 | 0x009B009B, | |
191 | 0x009E009E, | |
192 | 0x00980098, | |
193 | 0x00340034, | |
1e4ad74b | 194 | 0x00350035, |
11e2b043 LV |
195 | 0x00340034, |
196 | 0x00310031, | |
197 | 0x00340034, | |
198 | 0x007F007F, | |
199 | 0x007F007F, | |
200 | 0x007F007F, | |
201 | 0x007F007F, | |
202 | 0x007F007F, | |
203 | 0x00480048, | |
204 | 0x004A004A, | |
205 | 0x00520052, | |
206 | 0x00550055, | |
207 | 0x00500050, | |
1e4ad74b FB |
208 | 0x00000000, |
209 | 0x00600020, | |
6213db78 | 210 | 0x40011080, |
1e4ad74b | 211 | 0x08102040, |
11e2b043 LV |
212 | 0x0, |
213 | 0x0, | |
214 | 0x0, | |
215 | 0x0, | |
216 | 0x0, | |
496edffd LV |
217 | 0x0, |
218 | 0x0, | |
219 | 0x0, | |
220 | 0x0, | |
221 | 0x0 | |
1e4ad74b FB |
222 | }; |
223 | ||
224 | void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) | |
225 | { | |
226 | switch (emif_nr) { | |
227 | case 1: | |
228 | *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; | |
229 | break; | |
230 | case 2: | |
231 | *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; | |
232 | break; | |
233 | } | |
234 | } | |
235 | ||
236 | void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) | |
237 | { | |
238 | switch (emif_nr) { | |
239 | case 1: | |
240 | *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; | |
241 | *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); | |
242 | break; | |
243 | case 2: | |
244 | *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; | |
245 | *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); | |
246 | break; | |
247 | } | |
248 | } | |
249 | ||
250 | struct vcores_data beagle_x15_volts = { | |
beb71279 LV |
251 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
252 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, | |
1e4ad74b FB |
253 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
254 | .mpu.addr = TPS659038_REG_ADDR_SMPS12, | |
255 | .mpu.pmic = &tps659038, | |
eafd4644 | 256 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
1e4ad74b | 257 | |
beb71279 LV |
258 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
259 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, | |
260 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, | |
261 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | |
262 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, | |
263 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, | |
1e4ad74b FB |
264 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
265 | .eve.addr = TPS659038_REG_ADDR_SMPS45, | |
266 | .eve.pmic = &tps659038, | |
e52e334e | 267 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, |
1e4ad74b | 268 | |
beb71279 LV |
269 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
270 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | |
271 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | |
272 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | |
273 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | |
274 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | |
1e4ad74b FB |
275 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
276 | .gpu.addr = TPS659038_REG_ADDR_SMPS45, | |
277 | .gpu.pmic = &tps659038, | |
e52e334e | 278 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, |
1e4ad74b | 279 | |
beb71279 LV |
280 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
281 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, | |
1e4ad74b FB |
282 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
283 | .core.addr = TPS659038_REG_ADDR_SMPS6, | |
284 | .core.pmic = &tps659038, | |
285 | ||
beb71279 LV |
286 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
287 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, | |
288 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, | |
289 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, | |
290 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, | |
291 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, | |
1e4ad74b FB |
292 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
293 | .iva.addr = TPS659038_REG_ADDR_SMPS45, | |
294 | .iva.pmic = &tps659038, | |
e52e334e | 295 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, |
1e4ad74b FB |
296 | }; |
297 | ||
d60198da | 298 | struct vcores_data am572x_idk_volts = { |
beb71279 LV |
299 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
300 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, | |
d60198da K |
301 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
302 | .mpu.addr = TPS659038_REG_ADDR_SMPS12, | |
303 | .mpu.pmic = &tps659038, | |
304 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, | |
305 | ||
beb71279 LV |
306 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
307 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, | |
308 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, | |
309 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | |
310 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, | |
311 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, | |
d60198da K |
312 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
313 | .eve.addr = TPS659038_REG_ADDR_SMPS45, | |
314 | .eve.pmic = &tps659038, | |
315 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, | |
316 | ||
beb71279 LV |
317 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
318 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | |
319 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | |
320 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | |
321 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | |
322 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | |
d60198da K |
323 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
324 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, | |
325 | .gpu.pmic = &tps659038, | |
326 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, | |
327 | ||
beb71279 LV |
328 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
329 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, | |
d60198da K |
330 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
331 | .core.addr = TPS659038_REG_ADDR_SMPS7, | |
332 | .core.pmic = &tps659038, | |
333 | ||
beb71279 LV |
334 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
335 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, | |
336 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, | |
337 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, | |
338 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, | |
339 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, | |
d60198da K |
340 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
341 | .iva.addr = TPS659038_REG_ADDR_SMPS8, | |
342 | .iva.pmic = &tps659038, | |
343 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, | |
344 | }; | |
345 | ||
beb71279 LV |
346 | int get_voltrail_opp(int rail_offset) |
347 | { | |
348 | int opp; | |
349 | ||
350 | switch (rail_offset) { | |
351 | case VOLT_MPU: | |
352 | opp = DRA7_MPU_OPP; | |
353 | break; | |
354 | case VOLT_CORE: | |
355 | opp = DRA7_CORE_OPP; | |
356 | break; | |
357 | case VOLT_GPU: | |
358 | opp = DRA7_GPU_OPP; | |
359 | break; | |
360 | case VOLT_EVE: | |
361 | opp = DRA7_DSPEVE_OPP; | |
362 | break; | |
363 | case VOLT_IVA: | |
364 | opp = DRA7_IVA_OPP; | |
365 | break; | |
366 | default: | |
367 | opp = OPP_NOM; | |
368 | } | |
369 | ||
370 | return opp; | |
371 | } | |
372 | ||
373 | ||
212f96f6 KS |
374 | #ifdef CONFIG_SPL_BUILD |
375 | /* No env to setup for SPL */ | |
376 | static inline void setup_board_eeprom_env(void) { } | |
377 | ||
378 | /* Override function to read eeprom information */ | |
379 | void do_board_detect(void) | |
380 | { | |
381 | int rc; | |
382 | ||
383 | rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, | |
384 | CONFIG_EEPROM_CHIP_ADDRESS); | |
385 | if (rc) | |
386 | printf("ti_i2c_eeprom_init failed %d\n", rc); | |
387 | } | |
388 | ||
389 | #else /* CONFIG_SPL_BUILD */ | |
390 | ||
391 | /* Override function to read eeprom information: actual i2c read done by SPL*/ | |
392 | void do_board_detect(void) | |
393 | { | |
394 | char *bname = NULL; | |
395 | int rc; | |
396 | ||
397 | rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, | |
398 | CONFIG_EEPROM_CHIP_ADDRESS); | |
399 | if (rc) | |
400 | printf("ti_i2c_eeprom_init failed %d\n", rc); | |
401 | ||
402 | if (board_is_x15()) | |
403 | bname = "BeagleBoard X15"; | |
404 | else if (board_is_am572x_evm()) | |
405 | bname = "AM572x EVM"; | |
c020d355 SK |
406 | else if (board_is_am572x_idk()) |
407 | bname = "AM572x IDK"; | |
4d8397c6 SK |
408 | else if (board_is_am571x_idk()) |
409 | bname = "AM571x IDK"; | |
212f96f6 KS |
410 | |
411 | if (bname) | |
412 | snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, | |
413 | "Board: %s REV %s\n", bname, board_ti_get_rev()); | |
414 | } | |
415 | ||
416 | static void setup_board_eeprom_env(void) | |
417 | { | |
418 | char *name = "beagle_x15"; | |
419 | int rc; | |
420 | ||
421 | rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, | |
422 | CONFIG_EEPROM_CHIP_ADDRESS); | |
423 | if (rc) | |
424 | goto invalid_eeprom; | |
425 | ||
bf43ce6c | 426 | if (board_is_x15()) { |
f7f9f6be LV |
427 | if (board_is_x15_revb1()) |
428 | name = "beagle_x15_revb1"; | |
429 | else | |
430 | name = "beagle_x15"; | |
bf43ce6c NM |
431 | } else if (board_is_am572x_evm()) { |
432 | if (board_is_am572x_evm_reva3()) | |
433 | name = "am57xx_evm_reva3"; | |
434 | else | |
435 | name = "am57xx_evm"; | |
436 | } else if (board_is_am572x_idk()) { | |
c020d355 | 437 | name = "am572x_idk"; |
4d8397c6 SK |
438 | } else if (board_is_am571x_idk()) { |
439 | name = "am571x_idk"; | |
bf43ce6c | 440 | } else { |
212f96f6 KS |
441 | printf("Unidentified board claims %s in eeprom header\n", |
442 | board_ti_get_name()); | |
bf43ce6c | 443 | } |
212f96f6 KS |
444 | |
445 | invalid_eeprom: | |
446 | set_board_info_env(name); | |
447 | } | |
448 | ||
449 | #endif /* CONFIG_SPL_BUILD */ | |
450 | ||
d60198da K |
451 | void vcores_init(void) |
452 | { | |
453 | if (board_is_am572x_idk()) | |
454 | *omap_vcores = &am572x_idk_volts; | |
455 | else | |
456 | *omap_vcores = &beagle_x15_volts; | |
457 | } | |
458 | ||
1e4ad74b FB |
459 | void hw_data_init(void) |
460 | { | |
461 | *prcm = &dra7xx_prcm; | |
462 | *dplls_data = &dra7xx_dplls; | |
1e4ad74b FB |
463 | *ctrl = &dra7xx_ctrl; |
464 | } | |
465 | ||
37611052 RQ |
466 | bool am571x_idk_needs_lcd(void) |
467 | { | |
468 | bool needs_lcd; | |
469 | ||
470 | gpio_request(GPIO_ETH_LCD, "nLCD_Detect"); | |
471 | if (gpio_get_value(GPIO_ETH_LCD)) | |
472 | needs_lcd = false; | |
473 | else | |
474 | needs_lcd = true; | |
475 | ||
476 | gpio_free(GPIO_ETH_LCD); | |
477 | ||
478 | return needs_lcd; | |
479 | } | |
480 | ||
1e4ad74b FB |
481 | int board_init(void) |
482 | { | |
483 | gpmc_init(); | |
484 | gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
fcb18524 | 489 | void am57x_idk_lcd_detect(void) |
1e4ad74b | 490 | { |
fcb18524 NM |
491 | int r = -ENODEV; |
492 | char *idk_lcd = "no"; | |
493 | uint8_t buf = 0; | |
494 | ||
495 | /* Only valid for IDKs */ | |
496 | if (board_is_x15() || board_is_am572x_evm()) | |
497 | return; | |
498 | ||
499 | /* Only AM571x IDK has gpio control detect.. so check that */ | |
500 | if (board_is_am571x_idk() && !am571x_idk_needs_lcd()) | |
501 | goto out; | |
502 | ||
503 | r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS); | |
504 | if (r) { | |
505 | printf("%s: Failed to set bus address to %d: %d\n", | |
506 | __func__, OSD_TS_FT_BUS_ADDRESS, r); | |
507 | goto out; | |
508 | } | |
509 | r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS); | |
510 | if (r) { | |
511 | /* AM572x IDK has no explicit settings for optional LCD kit */ | |
512 | if (board_is_am571x_idk()) { | |
513 | printf("%s: Touch screen detect failed: %d!\n", | |
514 | __func__, r); | |
515 | } | |
516 | goto out; | |
517 | } | |
518 | ||
519 | /* Read FT ID */ | |
520 | r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1); | |
521 | if (r) { | |
522 | printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n", | |
523 | __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, | |
524 | OSD_TS_FT_REG_ID, r); | |
525 | goto out; | |
526 | } | |
37611052 | 527 | |
fcb18524 NM |
528 | switch (buf) { |
529 | case OSD_TS_FT_ID_5606: | |
530 | idk_lcd = "osd101t2045"; | |
531 | break; | |
532 | case OSD_TS_FT_ID_5x46: | |
533 | idk_lcd = "osd101t2587"; | |
534 | break; | |
535 | default: | |
536 | printf("%s: Unidentifed Touch screen ID 0x%02x\n", | |
537 | __func__, buf); | |
538 | /* we will let default be "no lcd" */ | |
539 | } | |
540 | out: | |
541 | setenv("idk_lcd", idk_lcd); | |
542 | return; | |
543 | } | |
544 | ||
545 | int board_late_init(void) | |
546 | { | |
212f96f6 | 547 | setup_board_eeprom_env(); |
385d3632 | 548 | u8 val; |
212f96f6 | 549 | |
1e4ad74b FB |
550 | /* |
551 | * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds | |
552 | * This is the POWERHOLD-in-Low behavior. | |
553 | */ | |
554 | palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); | |
82cca5a6 LV |
555 | |
556 | /* | |
557 | * Default FIT boot on HS devices. Non FIT images are not allowed | |
558 | * on HS devices. | |
559 | */ | |
560 | if (get_device_type() == HS_DEVICE) | |
561 | setenv("boot_fit", "1"); | |
562 | ||
385d3632 K |
563 | /* |
564 | * Set the GPIO7 Pad to POWERHOLD. This has higher priority | |
565 | * over DEV_CTRL.DEV_ON bit. This can be reset in case of | |
566 | * PMIC Power off. So to be on the safer side set it back | |
567 | * to POWERHOLD mode irrespective of the current state. | |
568 | */ | |
569 | palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, | |
570 | &val); | |
571 | val = val | TPS65903X_PAD2_POWERHOLD_MASK; | |
572 | palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, | |
573 | val); | |
574 | ||
7a2af751 SP |
575 | omap_die_id_serial(); |
576 | ||
fcb18524 | 577 | am57x_idk_lcd_detect(); |
37611052 RQ |
578 | |
579 | #if !defined(CONFIG_SPL_BUILD) | |
580 | board_ti_set_ethaddr(2); | |
581 | #endif | |
582 | ||
1e4ad74b FB |
583 | return 0; |
584 | } | |
585 | ||
3ef56e61 | 586 | void set_muxconf_regs(void) |
1e4ad74b FB |
587 | { |
588 | do_set_mux32((*ctrl)->control_padconf_core_base, | |
f91e0c4c | 589 | early_padconf, ARRAY_SIZE(early_padconf)); |
1e4ad74b FB |
590 | } |
591 | ||
f91e0c4c LV |
592 | #ifdef CONFIG_IODELAY_RECALIBRATION |
593 | void recalibrate_iodelay(void) | |
594 | { | |
c020d355 SK |
595 | const struct pad_conf_entry *pconf; |
596 | const struct iodelay_cfg_entry *iod; | |
597 | int pconf_sz, iod_sz; | |
89a38953 | 598 | int ret; |
c020d355 SK |
599 | |
600 | if (board_is_am572x_idk()) { | |
601 | pconf = core_padconf_array_essential_am572x_idk; | |
602 | pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); | |
603 | iod = iodelay_cfg_array_am572x_idk; | |
604 | iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); | |
4d8397c6 SK |
605 | } else if (board_is_am571x_idk()) { |
606 | pconf = core_padconf_array_essential_am571x_idk; | |
607 | pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); | |
608 | iod = iodelay_cfg_array_am571x_idk; | |
609 | iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk); | |
c020d355 SK |
610 | } else { |
611 | /* Common for X15/GPEVM */ | |
612 | pconf = core_padconf_array_essential_x15; | |
613 | pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); | |
89a38953 NM |
614 | /* There never was an SR1.0 X15.. So.. */ |
615 | if (omap_revision() == DRA752_ES1_1) { | |
616 | iod = iodelay_cfg_array_x15_sr1_1; | |
617 | iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1); | |
618 | } else { | |
619 | /* Since full production should switch to SR2.0 */ | |
620 | iod = iodelay_cfg_array_x15_sr2_0; | |
621 | iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0); | |
622 | } | |
c020d355 SK |
623 | } |
624 | ||
89a38953 NM |
625 | /* Setup I/O isolation */ |
626 | ret = __recalibrate_iodelay_start(); | |
627 | if (ret) | |
628 | goto err; | |
629 | ||
630 | /* Do the muxing here */ | |
631 | do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); | |
632 | ||
633 | /* Now do the weird minor deltas that should be safe */ | |
634 | if (board_is_x15() || board_is_am572x_evm()) { | |
635 | if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) { | |
636 | pconf = core_padconf_array_delta_x15_sr2_0; | |
637 | pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0); | |
638 | } else { | |
639 | pconf = core_padconf_array_delta_x15_sr1_1; | |
640 | pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1); | |
641 | } | |
642 | do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); | |
643 | } | |
644 | ||
37611052 RQ |
645 | if (board_is_am571x_idk()) { |
646 | if (am571x_idk_needs_lcd()) { | |
647 | pconf = core_padconf_array_vout_am571x_idk; | |
648 | pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); | |
649 | } else { | |
650 | pconf = core_padconf_array_icss1eth_am571x_idk; | |
651 | pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); | |
652 | } | |
653 | do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); | |
654 | } | |
655 | ||
89a38953 NM |
656 | /* Setup IOdelay configuration */ |
657 | ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); | |
658 | err: | |
659 | /* Closeup.. remove isolation */ | |
660 | __recalibrate_iodelay_end(ret); | |
f91e0c4c LV |
661 | } |
662 | #endif | |
663 | ||
d5abcf94 | 664 | #if defined(CONFIG_GENERIC_MMC) |
1e4ad74b FB |
665 | int board_mmc_init(bd_t *bis) |
666 | { | |
667 | omap_mmc_init(0, 0, 0, -1, -1); | |
668 | omap_mmc_init(1, 0, 0, -1, -1); | |
669 | return 0; | |
670 | } | |
671 | #endif | |
672 | ||
673 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) | |
674 | int spl_start_uboot(void) | |
675 | { | |
676 | /* break into full u-boot on 'c' */ | |
677 | if (serial_tstc() && serial_getc() == 'c') | |
678 | return 1; | |
679 | ||
680 | #ifdef CONFIG_SPL_ENV_SUPPORT | |
681 | env_init(); | |
682 | env_relocate_spec(); | |
683 | if (getenv_yesno("boot_os") != 1) | |
684 | return 1; | |
685 | #endif | |
686 | ||
687 | return 0; | |
688 | } | |
689 | #endif | |
690 | ||
7c379aaa | 691 | #ifdef CONFIG_USB_DWC3 |
7c379aaa KVA |
692 | static struct dwc3_device usb_otg_ss2 = { |
693 | .maximum_speed = USB_SPEED_HIGH, | |
694 | .base = DRA7_USB_OTG_SS2_BASE, | |
695 | .tx_fifo_resize = false, | |
696 | .index = 1, | |
697 | }; | |
698 | ||
699 | static struct dwc3_omap_device usb_otg_ss2_glue = { | |
700 | .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, | |
701 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | |
702 | .index = 1, | |
703 | }; | |
704 | ||
705 | static struct ti_usb_phy_device usb_phy2_device = { | |
706 | .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, | |
707 | .index = 1, | |
708 | }; | |
709 | ||
55efadde RQ |
710 | int usb_gadget_handle_interrupts(int index) |
711 | { | |
712 | u32 status; | |
713 | ||
714 | status = dwc3_omap_uboot_interrupt_status(index); | |
715 | if (status) | |
716 | dwc3_uboot_handle_interrupt(index); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | #endif /* CONFIG_USB_DWC3 */ | |
721 | ||
722 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) | |
7c379aaa KVA |
723 | int board_usb_init(int index, enum usb_init_type init) |
724 | { | |
6f1af1e3 | 725 | enable_usb_clocks(index); |
7c379aaa KVA |
726 | switch (index) { |
727 | case 0: | |
728 | if (init == USB_INIT_DEVICE) { | |
729 | printf("port %d can't be used as device\n", index); | |
6f1af1e3 | 730 | disable_usb_clocks(index); |
7c379aaa | 731 | return -EINVAL; |
7c379aaa | 732 | } |
7c379aaa KVA |
733 | break; |
734 | case 1: | |
735 | if (init == USB_INIT_DEVICE) { | |
55efadde | 736 | #ifdef CONFIG_USB_DWC3 |
7c379aaa KVA |
737 | usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; |
738 | usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | |
55efadde RQ |
739 | ti_usb_phy_uboot_init(&usb_phy2_device); |
740 | dwc3_omap_uboot_init(&usb_otg_ss2_glue); | |
741 | dwc3_uboot_init(&usb_otg_ss2); | |
742 | #endif | |
7c379aaa KVA |
743 | } else { |
744 | printf("port %d can't be used as host\n", index); | |
6f1af1e3 | 745 | disable_usb_clocks(index); |
7c379aaa KVA |
746 | return -EINVAL; |
747 | } | |
748 | ||
7c379aaa KVA |
749 | break; |
750 | default: | |
751 | printf("Invalid Controller Index\n"); | |
752 | } | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | int board_usb_cleanup(int index, enum usb_init_type init) | |
758 | { | |
55efadde | 759 | #ifdef CONFIG_USB_DWC3 |
7c379aaa KVA |
760 | switch (index) { |
761 | case 0: | |
762 | case 1: | |
55efadde RQ |
763 | if (init == USB_INIT_DEVICE) { |
764 | ti_usb_phy_uboot_exit(index); | |
765 | dwc3_uboot_exit(index); | |
766 | dwc3_omap_uboot_exit(index); | |
767 | } | |
7c379aaa KVA |
768 | break; |
769 | default: | |
770 | printf("Invalid Controller Index\n"); | |
771 | } | |
55efadde | 772 | #endif |
6f1af1e3 | 773 | disable_usb_clocks(index); |
7c379aaa KVA |
774 | return 0; |
775 | } | |
55efadde | 776 | #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ |
7c379aaa | 777 | |
1e4ad74b FB |
778 | #ifdef CONFIG_DRIVER_TI_CPSW |
779 | ||
780 | /* Delay value to add to calibrated value */ | |
781 | #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) | |
782 | #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) | |
783 | #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) | |
784 | #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) | |
785 | #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) | |
786 | #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) | |
787 | #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) | |
788 | #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) | |
789 | #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) | |
790 | #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) | |
791 | ||
792 | static void cpsw_control(int enabled) | |
793 | { | |
794 | /* VTP can be added here */ | |
795 | } | |
796 | ||
797 | static struct cpsw_slave_data cpsw_slaves[] = { | |
798 | { | |
799 | .slave_reg_ofs = 0x208, | |
800 | .sliver_reg_ofs = 0xd80, | |
801 | .phy_addr = 1, | |
802 | }, | |
803 | { | |
804 | .slave_reg_ofs = 0x308, | |
805 | .sliver_reg_ofs = 0xdc0, | |
806 | .phy_addr = 2, | |
807 | }, | |
808 | }; | |
809 | ||
810 | static struct cpsw_platform_data cpsw_data = { | |
811 | .mdio_base = CPSW_MDIO_BASE, | |
812 | .cpsw_base = CPSW_BASE, | |
813 | .mdio_div = 0xff, | |
814 | .channels = 8, | |
815 | .cpdma_reg_ofs = 0x800, | |
816 | .slaves = 1, | |
817 | .slave_data = cpsw_slaves, | |
818 | .ale_reg_ofs = 0xd00, | |
819 | .ale_entries = 1024, | |
820 | .host_port_reg_ofs = 0x108, | |
821 | .hw_stats_reg_ofs = 0x900, | |
822 | .bd_ram_ofs = 0x2000, | |
823 | .mac_control = (1 << 5), | |
824 | .control = cpsw_control, | |
825 | .host_port_num = 0, | |
826 | .version = CPSW_CTRL_VERSION_2, | |
827 | }; | |
828 | ||
92667e89 RQ |
829 | static u64 mac_to_u64(u8 mac[6]) |
830 | { | |
831 | int i; | |
832 | u64 addr = 0; | |
833 | ||
834 | for (i = 0; i < 6; i++) { | |
835 | addr <<= 8; | |
836 | addr |= mac[i]; | |
837 | } | |
838 | ||
839 | return addr; | |
840 | } | |
841 | ||
842 | static void u64_to_mac(u64 addr, u8 mac[6]) | |
843 | { | |
844 | mac[5] = addr; | |
845 | mac[4] = addr >> 8; | |
846 | mac[3] = addr >> 16; | |
847 | mac[2] = addr >> 24; | |
848 | mac[1] = addr >> 32; | |
849 | mac[0] = addr >> 40; | |
850 | } | |
851 | ||
1e4ad74b FB |
852 | int board_eth_init(bd_t *bis) |
853 | { | |
854 | int ret; | |
855 | uint8_t mac_addr[6]; | |
856 | uint32_t mac_hi, mac_lo; | |
857 | uint32_t ctrl_val; | |
92667e89 RQ |
858 | int i; |
859 | u64 mac1, mac2; | |
860 | u8 mac_addr1[6], mac_addr2[6]; | |
861 | int num_macs; | |
1e4ad74b FB |
862 | |
863 | /* try reading mac address from efuse */ | |
864 | mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); | |
865 | mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); | |
866 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; | |
867 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
868 | mac_addr[2] = mac_hi & 0xFF; | |
869 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; | |
870 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; | |
871 | mac_addr[5] = mac_lo & 0xFF; | |
872 | ||
873 | if (!getenv("ethaddr")) { | |
874 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); | |
875 | ||
0adb5b76 | 876 | if (is_valid_ethaddr(mac_addr)) |
1e4ad74b FB |
877 | eth_setenv_enetaddr("ethaddr", mac_addr); |
878 | } | |
879 | ||
880 | mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); | |
881 | mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); | |
882 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; | |
883 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
884 | mac_addr[2] = mac_hi & 0xFF; | |
885 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; | |
886 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; | |
887 | mac_addr[5] = mac_lo & 0xFF; | |
888 | ||
889 | if (!getenv("eth1addr")) { | |
0adb5b76 | 890 | if (is_valid_ethaddr(mac_addr)) |
1e4ad74b FB |
891 | eth_setenv_enetaddr("eth1addr", mac_addr); |
892 | } | |
893 | ||
894 | ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); | |
895 | ctrl_val |= 0x22; | |
896 | writel(ctrl_val, (*ctrl)->control_core_control_io1); | |
897 | ||
4d8397c6 SK |
898 | /* The phy address for the AM57xx IDK are different than x15 */ |
899 | if (board_is_am572x_idk() || board_is_am571x_idk()) { | |
c020d355 SK |
900 | cpsw_data.slave_data[0].phy_addr = 0; |
901 | cpsw_data.slave_data[1].phy_addr = 1; | |
902 | } | |
903 | ||
1e4ad74b FB |
904 | ret = cpsw_register(&cpsw_data); |
905 | if (ret < 0) | |
906 | printf("Error %d registering CPSW switch\n", ret); | |
907 | ||
92667e89 RQ |
908 | /* |
909 | * Export any Ethernet MAC addresses from EEPROM. | |
910 | * On AM57xx the 2 MAC addresses define the address range | |
911 | */ | |
912 | board_ti_get_eth_mac_addr(0, mac_addr1); | |
913 | board_ti_get_eth_mac_addr(1, mac_addr2); | |
914 | ||
915 | if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { | |
916 | mac1 = mac_to_u64(mac_addr1); | |
917 | mac2 = mac_to_u64(mac_addr2); | |
918 | ||
919 | /* must contain an address range */ | |
920 | num_macs = mac2 - mac1 + 1; | |
921 | /* <= 50 to protect against user programming error */ | |
922 | if (num_macs > 0 && num_macs <= 50) { | |
923 | for (i = 0; i < num_macs; i++) { | |
924 | u64_to_mac(mac1 + i, mac_addr); | |
925 | if (is_valid_ethaddr(mac_addr)) { | |
926 | eth_setenv_enetaddr_by_index("eth", | |
927 | i + 2, | |
928 | mac_addr); | |
929 | } | |
930 | } | |
931 | } | |
932 | } | |
933 | ||
1e4ad74b FB |
934 | return ret; |
935 | } | |
936 | #endif | |
334bbb38 LV |
937 | |
938 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
939 | /* VTT regulator enable */ | |
940 | static inline void vtt_regulator_enable(void) | |
941 | { | |
942 | if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) | |
943 | return; | |
944 | ||
945 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); | |
946 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); | |
947 | } | |
948 | ||
949 | int board_early_init_f(void) | |
950 | { | |
951 | vtt_regulator_enable(); | |
952 | return 0; | |
953 | } | |
954 | #endif | |
62a09f05 DA |
955 | |
956 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
957 | int ft_board_setup(void *blob, bd_t *bd) | |
958 | { | |
959 | ft_cpu_setup(blob, bd); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | #endif | |
7a0ea589 LV |
964 | |
965 | #ifdef CONFIG_SPL_LOAD_FIT | |
966 | int board_fit_config_name_match(const char *name) | |
967 | { | |
f7f9f6be LV |
968 | if (board_is_x15()) { |
969 | if (board_is_x15_revb1()) { | |
970 | if (!strcmp(name, "am57xx-beagle-x15-revb1")) | |
971 | return 0; | |
972 | } else if (!strcmp(name, "am57xx-beagle-x15")) { | |
973 | return 0; | |
974 | } | |
975 | } else if (board_is_am572x_evm() && | |
976 | !strcmp(name, "am57xx-beagle-x15")) { | |
7a0ea589 | 977 | return 0; |
f7f9f6be | 978 | } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) { |
332dddc6 | 979 | return 0; |
45e7f7e7 SP |
980 | } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) { |
981 | return 0; | |
f7f9f6be LV |
982 | } |
983 | ||
984 | return -1; | |
7a0ea589 LV |
985 | } |
986 | #endif | |
17c29873 AD |
987 | |
988 | #ifdef CONFIG_TI_SECURE_DEVICE | |
989 | void board_fit_image_post_process(void **p_image, size_t *p_size) | |
990 | { | |
991 | secure_boot_verify_image(p_image, p_size); | |
992 | } | |
1b597ada AD |
993 | |
994 | void board_tee_image_process(ulong tee_image, size_t tee_size) | |
995 | { | |
996 | secure_tee_install((u32)tee_image); | |
997 | } | |
998 | ||
999 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); | |
17c29873 | 1000 | #endif |