[people/ms/u-boot.git] / board / ti / beagle_x15 / board.c

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
 *
 * Author: Felipe Balbi <balbi@ti.com>
 *
 * Based on board/ti/dra7xx/evm.c
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <usb.h>
#include <asm/omap_common.h>
#include <asm/emif.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
#include <environment.h>

#include "mux_data.h"

#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: BeagleBoard x15\n"
};

static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
	.dmm_lisa_map_3 = 0x80740300,
	.is_ma_present  = 0x1
};

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
	*dmm_lisa_regs = &beagle_x15_lisa_regs;
}

static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
	.sdram_config_init	= 0x61851b32,
	.sdram_config		= 0x61851b32,
	.sdram_config2		= 0x00000000,
	.ref_ctrl		= 0x000040F1,
	.ref_ctrl_final		= 0x00001035,
	.sdram_tim1		= 0xceef266b,
	.sdram_tim2		= 0x328f7fda,
	.sdram_tim3		= 0x027f88a8,
	.read_idle_ctrl		= 0x00050001,
	.zq_config		= 0x0007190b,
	.temp_alert_config	= 0x00000000,
	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
	.emif_ddr_phy_ctlr_1	= 0x0e24400a,
	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl	= 0x00000000,
	.emif_rd_wr_lvl_ctl	= 0x00000000,
	.emif_rd_wr_exec_thresh	= 0x00000305
};

static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
	0x00800080,
	0x00360036,
	0x00340034,
	0x00360036,
	0x00350035,
	0x00350035,

	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,

	0x00430043,
	0x003e003e,
	0x004a004a,
	0x00470047,
	0x00400040,

	0x00000000,
	0x00600020,
	0x40010080,
	0x08102040,

	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040
};

static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
	.sdram_config_init	= 0x61851b32,
	.sdram_config		= 0x61851b32,
	.sdram_config2		= 0x00000000,
	.ref_ctrl		= 0x000040F1,
	.ref_ctrl_final		= 0x00001035,
	.sdram_tim1		= 0xceef266b,
	.sdram_tim2		= 0x328f7fda,
	.sdram_tim3		= 0x027f88a8,
	.read_idle_ctrl		= 0x00050001,
	.zq_config		= 0x0007190b,
	.temp_alert_config	= 0x00000000,
	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
	.emif_ddr_phy_ctlr_1	= 0x0e24400a,
	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl	= 0x00000000,
	.emif_rd_wr_lvl_ctl	= 0x00000000,
	.emif_rd_wr_exec_thresh	= 0x00000305
};

static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
	0x00800080,
	0x00370037,
	0x00390039,
	0x00360036,
	0x00370037,
	0x00350035,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x00540054,
	0x00540054,
	0x004e004e,
	0x004c004c,
	0x00400040,

	0x00000000,
	0x00600020,
	0x40010080,
	0x08102040,

	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040
};

void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
	switch (emif_nr) {
	case 1:
		*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
		break;
	case 2:
		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
		break;
	}
}

void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
	switch (emif_nr) {
	case 1:
		*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
		*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
		break;
	case 2:
		*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
		*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
		break;
	}
}

struct vcores_data beagle_x15_volts = {
	.mpu.value		= VDD_MPU_DRA752,
	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU_NOM,
	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
	.mpu.pmic		= &tps659038,

	.eve.value		= VDD_EVE_DRA752,
	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
	.eve.pmic		= &tps659038,

	.gpu.value		= VDD_GPU_DRA752,
	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_NOM,
	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
	.gpu.pmic		= &tps659038,

	.core.value		= VDD_CORE_DRA752,
	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.core.addr		= TPS659038_REG_ADDR_SMPS6,
	.core.pmic		= &tps659038,

	.iva.value		= VDD_IVA_DRA752,
	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA_NOM,
	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
	.iva.pmic		= &tps659038,
};

void hw_data_init(void)
{
	*prcm = &dra7xx_prcm;
	*dplls_data = &dra7xx_dplls;
	*omap_vcores = &beagle_x15_volts;
	*ctrl = &dra7xx_ctrl;
}

int board_init(void)
{
	gpmc_init();
	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);

	return 0;
}

int board_late_init(void)
{
	init_sata(0);
	/*
	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
	 * This is the POWERHOLD-in-Low behavior.
	 */
	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
	return 0;
}

static void do_set_mux32(u32 base,
			 struct pad_conf_entry const *array, int size)
{
	int i;
	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;

	for (i = 0; i < size; i++, pad++)
		writel(pad->val, base + pad->offset);
}

void set_muxconf_regs_essential(void)
{
	do_set_mux32((*ctrl)->control_padconf_core_base,
		     core_padconf_array_essential,
		     sizeof(core_padconf_array_essential) /
		     sizeof(struct pad_conf_entry));
}

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	if (getenv_yesno("boot_os") != 1)
		return 1;
#endif

	return 0;
}
#endif

#ifdef CONFIG_DRIVER_TI_CPSW

/* Delay value to add to calibrated value */
#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)

static void cpsw_control(int enabled)
{
	/* VTP can be added here */
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 1,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 2,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int ret;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	uint32_t ctrl_val;

	/* try reading mac address from efuse */
	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("eth1addr")) {
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("eth1addr", mac_addr);
	}

	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	ctrl_val |= 0x22;
	writel(ctrl_val, (*ctrl)->control_core_control_io1);

	ret = cpsw_register(&cpsw_data);
	if (ret < 0)
		printf("Error %d registering CPSW switch\n", ret);

	return ret;
}
#endif
Commit	Line	Data
1e4ad74b FB	1	/*
	2	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
	3	*
	4	* Author: Felipe Balbi <balbi@ti.com>
	5	*
	6	* Based on board/ti/dra7xx/evm.c
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <palmas.h>
	13	#include <sata.h>
	14	#include <usb.h>
	15	#include <asm/omap_common.h>
	16	#include <asm/emif.h>
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/sys_proto.h>
	19	#include <asm/arch/mmc_host_def.h>
	20	#include <asm/arch/sata.h>
	21	#include <asm/arch/gpio.h>
	22	#include <environment.h>
	23
	24	#include "mux_data.h"
	25
	26	#ifdef CONFIG_DRIVER_TI_CPSW
	27	#include <cpsw.h>
	28	#endif
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	const struct omap_sysinfo sysinfo = {
	33	"Board: BeagleBoard x15\n"
	34	};
	35
	36	static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
	37	.dmm_lisa_map_3 = 0x80740300,
	38	.is_ma_present = 0x1
	39	};
	40
	41	void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	42	{
	43	*dmm_lisa_regs = &beagle_x15_lisa_regs;
	44	}
	45
	46	static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
	47	.sdram_config_init = 0x61851b32,
	48	.sdram_config = 0x61851b32,
	49	.sdram_config2 = 0x00000000,
802bb57a LV	50	.ref_ctrl = 0x000040F1,
802bb57a LV	51	.ref_ctrl_final = 0x00001035,
1e4ad74b FB	52	.sdram_tim1 = 0xceef266b,
	53	.sdram_tim2 = 0x328f7fda,
	54	.sdram_tim3 = 0x027f88a8,
	55	.read_idle_ctrl = 0x00050001,
	56	.zq_config = 0x0007190b,
	57	.temp_alert_config = 0x00000000,
	58	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
	59	.emif_ddr_phy_ctlr_1 = 0x0e24400a,
	60	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	61	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
	62	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
	63	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
	64	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
	65	.emif_rd_wr_lvl_rmp_win = 0x00000000,
	66	.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
	67	.emif_rd_wr_lvl_ctl = 0x00000000,
	68	.emif_rd_wr_exec_thresh = 0x00000305
	69	};
	70
	71	static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
	72	0x00800080,
	73	0x00360036,
	74	0x00340034,
	75	0x00360036,
	76	0x00350035,
	77	0x00350035,
	78
	79	0x01ff01ff,
	80	0x01ff01ff,
	81	0x01ff01ff,
	82	0x01ff01ff,
	83	0x01ff01ff,
	84
	85	0x00430043,
	86	0x003e003e,
	87	0x004a004a,
	88	0x00470047,
	89	0x00400040,
	90
	91	0x00000000,
	92	0x00600020,
	93	0x40010080,
	94	0x08102040,
	95
	96	0x00400040,
	97	0x00400040,
	98	0x00400040,
	99	0x00400040,
	100	0x00400040
	101	};
	102
	103	static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
	104	.sdram_config_init = 0x61851b32,
	105	.sdram_config = 0x61851b32,
	106	.sdram_config2 = 0x00000000,
802bb57a LV	107	.ref_ctrl = 0x000040F1,
802bb57a LV	108	.ref_ctrl_final = 0x00001035,
1e4ad74b FB	109	.sdram_tim1 = 0xceef266b,
	110	.sdram_tim2 = 0x328f7fda,
	111	.sdram_tim3 = 0x027f88a8,
	112	.read_idle_ctrl = 0x00050001,
	113	.zq_config = 0x0007190b,
	114	.temp_alert_config = 0x00000000,
	115	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
	116	.emif_ddr_phy_ctlr_1 = 0x0e24400a,
	117	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	118	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
	119	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
	120	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
	121	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
	122	.emif_rd_wr_lvl_rmp_win = 0x00000000,
	123	.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
	124	.emif_rd_wr_lvl_ctl = 0x00000000,
	125	.emif_rd_wr_exec_thresh = 0x00000305
	126	};
	127
	128	static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
	129	0x00800080,
	130	0x00370037,
	131	0x00390039,
	132	0x00360036,
	133	0x00370037,
	134	0x00350035,
	135	0x01ff01ff,
	136	0x01ff01ff,
	137	0x01ff01ff,
	138	0x01ff01ff,
	139	0x01ff01ff,
	140	0x00540054,
	141	0x00540054,
	142	0x004e004e,
	143	0x004c004c,
	144	0x00400040,
	145
	146	0x00000000,
	147	0x00600020,
	148	0x40010080,
	149	0x08102040,
	150
	151	0x00400040,
	152	0x00400040,
	153	0x00400040,
	154	0x00400040,
	155	0x00400040
	156	};
	157
	158	void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	159	{
	160	switch (emif_nr) {
	161	case 1:
	162	*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
	163	break;
	164	case 2:
	165	*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
	166	break;
	167	}
	168	}
	169
	170	void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 *regs, u32 size)
	171	{
	172	switch (emif_nr) {
173	case 1:
174	*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
175	*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
176	break;
177	case 2:
178	*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
179	*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
180	break;
181	}
182	}
183
184	struct vcores_data beagle_x15_volts = {
185	.mpu.value = VDD_MPU_DRA752,
186	.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
187	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
188	.mpu.addr = TPS659038_REG_ADDR_SMPS12,
189	.mpu.pmic = &tps659038,
190
191	.eve.value = VDD_EVE_DRA752,
192	.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
193	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
194	.eve.addr = TPS659038_REG_ADDR_SMPS45,
195	.eve.pmic = &tps659038,
196
197	.gpu.value = VDD_GPU_DRA752,
198	.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
199	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
200	.gpu.addr = TPS659038_REG_ADDR_SMPS45,
201	.gpu.pmic = &tps659038,
202
203	.core.value = VDD_CORE_DRA752,
204	.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
205	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
206	.core.addr = TPS659038_REG_ADDR_SMPS6,
207	.core.pmic = &tps659038,
208
209	.iva.value = VDD_IVA_DRA752,
210	.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
211	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
212	.iva.addr = TPS659038_REG_ADDR_SMPS45,
213	.iva.pmic = &tps659038,
214	};
215
216	void hw_data_init(void)
217	{
218	*prcm = &dra7xx_prcm;
219	*dplls_data = &dra7xx_dplls;
220	*omap_vcores = &beagle_x15_volts;
221	*ctrl = &dra7xx_ctrl;
222	}
223
224	int board_init(void)
225	{
226	gpmc_init();
227	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
228
229	return 0;
230	}
231
232	int board_late_init(void)
233	{
234	init_sata(0);
235	/*
236	* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
237	* This is the POWERHOLD-in-Low behavior.
238	*/
239	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
240	return 0;
241	}
242
243	static void do_set_mux32(u32 base,
244	struct pad_conf_entry const *array, int size)
245	{
246	int i;
247	struct pad_conf_entry pad = (struct pad_conf_entry )array;
248
249	for (i = 0; i < size; i++, pad++)
250	writel(pad->val, base + pad->offset);
251	}
252
253	void set_muxconf_regs_essential(void)
254	{
255	do_set_mux32((*ctrl)->control_padconf_core_base,
256	core_padconf_array_essential,
257	sizeof(core_padconf_array_essential) /
258	sizeof(struct pad_conf_entry));
259	}
260
261	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
262	int board_mmc_init(bd_t *bis)
263	{
264	omap_mmc_init(0, 0, 0, -1, -1);
265	omap_mmc_init(1, 0, 0, -1, -1);
266	return 0;
267	}
268	#endif
269
270	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
271	int spl_start_uboot(void)
272	{
273	/* break into full u-boot on 'c' */
274	if (serial_tstc() && serial_getc() == 'c')
275	return 1;
276
277	#ifdef CONFIG_SPL_ENV_SUPPORT
278	env_init();
279	env_relocate_spec();
280	if (getenv_yesno("boot_os") != 1)
281	return 1;
282	#endif
283
284	return 0;
285	}
286	#endif
287
288	#ifdef CONFIG_DRIVER_TI_CPSW
289
290	/* Delay value to add to calibrated value */
291	#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
292	#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
293	#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
294	#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
295	#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
296	#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
297	#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
298	#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
299	#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
300	#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
301
302	static void cpsw_control(int enabled)
303	{
304	/* VTP can be added here */
305	}
306
307	static struct cpsw_slave_data cpsw_slaves[] = {
308	{
309	.slave_reg_ofs = 0x208,
310	.sliver_reg_ofs = 0xd80,
311	.phy_addr = 1,
312	},
313	{
314	.slave_reg_ofs = 0x308,
315	.sliver_reg_ofs = 0xdc0,
316	.phy_addr = 2,
317	},
318	};
319
320	static struct cpsw_platform_data cpsw_data = {
321	.mdio_base = CPSW_MDIO_BASE,
322	.cpsw_base = CPSW_BASE,
323	.mdio_div = 0xff,
324	.channels = 8,
325	.cpdma_reg_ofs = 0x800,
326	.slaves = 1,
327	.slave_data = cpsw_slaves,
328	.ale_reg_ofs = 0xd00,
329	.ale_entries = 1024,
330	.host_port_reg_ofs = 0x108,
331	.hw_stats_reg_ofs = 0x900,
332	.bd_ram_ofs = 0x2000,
333	.mac_control = (1 << 5),
334	.control = cpsw_control,
335	.host_port_num = 0,
336	.version = CPSW_CTRL_VERSION_2,
337	};
338
339	int board_eth_init(bd_t *bis)
340	{
341	int ret;
342	uint8_t mac_addr[6];
343	uint32_t mac_hi, mac_lo;
344	uint32_t ctrl_val;
345
346	/* try reading mac address from efuse */
347	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
348	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
349	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
350	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
351	mac_addr[2] = mac_hi & 0xFF;
352	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
353	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
354	mac_addr[5] = mac_lo & 0xFF;
355
356	if (!getenv("ethaddr")) {
357	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
358
0adb5b76	359	if (is_valid_ethaddr(mac_addr))
1e4ad74b FB	360	eth_setenv_enetaddr("ethaddr", mac_addr);
	361	}
	362
	363	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	364	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	365	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	366	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	367	mac_addr[2] = mac_hi & 0xFF;
	368	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	369	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	370	mac_addr[5] = mac_lo & 0xFF;
	371
	372	if (!getenv("eth1addr")) {
0adb5b76	373	if (is_valid_ethaddr(mac_addr))
1e4ad74b FB	374	eth_setenv_enetaddr("eth1addr", mac_addr);
	375	}
	376
	377	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	378	ctrl_val \|= 0x22;
	379	writel(ctrl_val, (*ctrl)->control_core_control_io1);
	380
	381	ret = cpsw_register(&cpsw_data);
	382	if (ret < 0)
	383	printf("Error %d registering CPSW switch\n", ret);
	384
	385	return ret;
	386	}
	387	#endif