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687054a7 LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated, <www.ti.com> | |
4 | * | |
5 | * Lokesh Vutla <lokeshvutla@ti.com> | |
6 | * | |
7 | * Based on previous work by: | |
8 | * Aneesh V <aneesh@ti.com> | |
9 | * Steve Sakoman <steve@sakoman.com> | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
687054a7 LV |
12 | */ |
13 | #include <common.h> | |
cb199102 | 14 | #include <palmas.h> |
e9024ef2 | 15 | #include <sata.h> |
25afe55d | 16 | #include <linux/string.h> |
7b922523 | 17 | #include <asm/gpio.h> |
a17188c1 KVA |
18 | #include <usb.h> |
19 | #include <linux/usb/gadget.h> | |
17c29873 AD |
20 | #include <asm/omap_common.h> |
21 | #include <asm/omap_sec_common.h> | |
7b922523 | 22 | #include <asm/arch/gpio.h> |
706dd348 | 23 | #include <asm/arch/dra7xx_iodelay.h> |
a7638833 | 24 | #include <asm/emif.h> |
687054a7 LV |
25 | #include <asm/arch/sys_proto.h> |
26 | #include <asm/arch/mmc_host_def.h> | |
21914ee6 | 27 | #include <asm/arch/sata.h> |
79b079f3 | 28 | #include <environment.h> |
a17188c1 KVA |
29 | #include <dwc3-uboot.h> |
30 | #include <dwc3-omap-uboot.h> | |
31 | #include <ti-usb-phy-uboot.h> | |
39fbac91 | 32 | #include <miiphy.h> |
687054a7 LV |
33 | |
34 | #include "mux_data.h" | |
25afe55d LV |
35 | #include "../common/board_detect.h" |
36 | ||
37 | #define board_is_dra74x_evm() board_ti_is("5777xCPU") | |
6b1c14bb | 38 | #define board_is_dra72x_evm() board_ti_is("DRA72x-T") |
463dd225 | 39 | #define board_is_dra71x_evm() board_ti_is("DRA79x,D") |
1053a769 M |
40 | #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ |
41 | (strncmp("H", board_ti_get_rev(), 1) <= 0)) | |
42 | #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ | |
43 | (strncmp("C", board_ti_get_rev(), 1) <= 0)) | |
c4a2736c LV |
44 | #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ |
45 | board_ti_get_emif2_size() | |
687054a7 | 46 | |
b1e26e3b M |
47 | #ifdef CONFIG_DRIVER_TI_CPSW |
48 | #include <cpsw.h> | |
49 | #endif | |
50 | ||
687054a7 LV |
51 | DECLARE_GLOBAL_DATA_PTR; |
52 | ||
7b922523 LV |
53 | /* GPIO 7_11 */ |
54 | #define GPIO_DDR_VTT_EN 203 | |
55 | ||
25afe55d LV |
56 | #define SYSINFO_BOARD_NAME_MAX_LEN 37 |
57 | ||
687054a7 | 58 | const struct omap_sysinfo sysinfo = { |
25afe55d | 59 | "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" |
687054a7 LV |
60 | }; |
61 | ||
a7638833 LV |
62 | static const struct emif_regs emif1_ddr3_532_mhz_1cs = { |
63 | .sdram_config_init = 0x61851ab2, | |
64 | .sdram_config = 0x61851ab2, | |
65 | .sdram_config2 = 0x08000000, | |
66 | .ref_ctrl = 0x000040F1, | |
67 | .ref_ctrl_final = 0x00001035, | |
68 | .sdram_tim1 = 0xCCCF36B3, | |
69 | .sdram_tim2 = 0x308F7FDA, | |
70 | .sdram_tim3 = 0x427F88A8, | |
71 | .read_idle_ctrl = 0x00050000, | |
72 | .zq_config = 0x0007190B, | |
73 | .temp_alert_config = 0x00000000, | |
74 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, | |
75 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, | |
76 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
77 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
78 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
79 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, | |
80 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, | |
81 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
82 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
83 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
84 | .emif_rd_wr_exec_thresh = 0x00000305 | |
85 | }; | |
86 | ||
87 | static const struct emif_regs emif2_ddr3_532_mhz_1cs = { | |
88 | .sdram_config_init = 0x61851B32, | |
89 | .sdram_config = 0x61851B32, | |
90 | .sdram_config2 = 0x08000000, | |
91 | .ref_ctrl = 0x000040F1, | |
92 | .ref_ctrl_final = 0x00001035, | |
93 | .sdram_tim1 = 0xCCCF36B3, | |
94 | .sdram_tim2 = 0x308F7FDA, | |
95 | .sdram_tim3 = 0x427F88A8, | |
96 | .read_idle_ctrl = 0x00050000, | |
97 | .zq_config = 0x0007190B, | |
98 | .temp_alert_config = 0x00000000, | |
99 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, | |
100 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, | |
101 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
102 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
103 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
104 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, | |
105 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, | |
106 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
107 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
108 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
109 | .emif_rd_wr_exec_thresh = 0x00000305 | |
110 | }; | |
111 | ||
112 | static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { | |
113 | .sdram_config_init = 0x61862B32, | |
114 | .sdram_config = 0x61862B32, | |
115 | .sdram_config2 = 0x08000000, | |
116 | .ref_ctrl = 0x0000514C, | |
117 | .ref_ctrl_final = 0x0000144A, | |
118 | .sdram_tim1 = 0xD113781C, | |
119 | .sdram_tim2 = 0x30717FE3, | |
120 | .sdram_tim3 = 0x409F86A8, | |
121 | .read_idle_ctrl = 0x00050000, | |
122 | .zq_config = 0x5007190B, | |
123 | .temp_alert_config = 0x00000000, | |
124 | .emif_ddr_phy_ctlr_1_init = 0x0024400D, | |
125 | .emif_ddr_phy_ctlr_1 = 0x0E24400D, | |
126 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
127 | .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, | |
128 | .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, | |
129 | .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, | |
130 | .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, | |
131 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
132 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
133 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
134 | .emif_rd_wr_exec_thresh = 0x00000305 | |
135 | }; | |
136 | ||
6b1c14bb RB |
137 | const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { |
138 | .sdram_config_init = 0x61862BB2, | |
139 | .sdram_config = 0x61862BB2, | |
140 | .sdram_config2 = 0x00000000, | |
141 | .ref_ctrl = 0x0000514D, | |
142 | .ref_ctrl_final = 0x0000144A, | |
143 | .sdram_tim1 = 0xD1137824, | |
144 | .sdram_tim2 = 0x30B37FE3, | |
145 | .sdram_tim3 = 0x409F8AD8, | |
146 | .read_idle_ctrl = 0x00050000, | |
147 | .zq_config = 0x5007190B, | |
148 | .temp_alert_config = 0x00000000, | |
149 | .emif_ddr_phy_ctlr_1_init = 0x0824400E, | |
150 | .emif_ddr_phy_ctlr_1 = 0x0E24400E, | |
151 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, | |
152 | .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, | |
153 | .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, | |
154 | .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, | |
155 | .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, | |
156 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
157 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
158 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
159 | .emif_rd_wr_exec_thresh = 0x00000305 | |
160 | }; | |
161 | ||
c4a2736c LV |
162 | const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { |
163 | .sdram_config_init = 0x61851ab2, | |
164 | .sdram_config = 0x61851ab2, | |
165 | .sdram_config2 = 0x08000000, | |
166 | .ref_ctrl = 0x000040F1, | |
167 | .ref_ctrl_final = 0x00001035, | |
168 | .sdram_tim1 = 0xCCCF36B3, | |
169 | .sdram_tim2 = 0x30BF7FDA, | |
170 | .sdram_tim3 = 0x427F8BA8, | |
171 | .read_idle_ctrl = 0x00050000, | |
172 | .zq_config = 0x0007190B, | |
173 | .temp_alert_config = 0x00000000, | |
174 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, | |
175 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, | |
176 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
177 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
178 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
179 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, | |
180 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, | |
181 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
182 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
183 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
184 | .emif_rd_wr_exec_thresh = 0x00000305 | |
185 | }; | |
186 | ||
187 | const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { | |
188 | .sdram_config_init = 0x61851B32, | |
189 | .sdram_config = 0x61851B32, | |
190 | .sdram_config2 = 0x08000000, | |
191 | .ref_ctrl = 0x000040F1, | |
192 | .ref_ctrl_final = 0x00001035, | |
193 | .sdram_tim1 = 0xCCCF36B3, | |
194 | .sdram_tim2 = 0x308F7FDA, | |
195 | .sdram_tim3 = 0x427F88A8, | |
196 | .read_idle_ctrl = 0x00050000, | |
197 | .zq_config = 0x0007190B, | |
198 | .temp_alert_config = 0x00000000, | |
199 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, | |
200 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, | |
201 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, | |
202 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, | |
203 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, | |
204 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, | |
205 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, | |
206 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | |
207 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |
208 | .emif_rd_wr_lvl_ctl = 0x00000000, | |
209 | .emif_rd_wr_exec_thresh = 0x00000305 | |
210 | }; | |
211 | ||
a7638833 LV |
212 | void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) |
213 | { | |
c4a2736c LV |
214 | u64 ram_size; |
215 | ||
216 | ram_size = board_ti_get_emif_size(); | |
217 | ||
a7638833 LV |
218 | switch (omap_revision()) { |
219 | case DRA752_ES1_0: | |
220 | case DRA752_ES1_1: | |
221 | case DRA752_ES2_0: | |
222 | switch (emif_nr) { | |
223 | case 1: | |
c4a2736c LV |
224 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
225 | *regs = &emif1_ddr3_532_mhz_1cs_2G; | |
226 | else | |
227 | *regs = &emif1_ddr3_532_mhz_1cs; | |
a7638833 LV |
228 | break; |
229 | case 2: | |
c4a2736c LV |
230 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
231 | *regs = &emif2_ddr3_532_mhz_1cs_2G; | |
232 | else | |
233 | *regs = &emif2_ddr3_532_mhz_1cs; | |
a7638833 LV |
234 | break; |
235 | } | |
236 | break; | |
237 | case DRA722_ES1_0: | |
6b1c14bb RB |
238 | case DRA722_ES2_0: |
239 | if (ram_size < CONFIG_MAX_MEM_MAPPED) | |
240 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; | |
241 | else | |
242 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; | |
a7638833 LV |
243 | break; |
244 | default: | |
245 | *regs = &emif1_ddr3_532_mhz_1cs; | |
246 | } | |
247 | } | |
248 | ||
249 | static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { | |
250 | .dmm_lisa_map_0 = 0x0, | |
251 | .dmm_lisa_map_1 = 0x80640300, | |
252 | .dmm_lisa_map_2 = 0xC0500220, | |
253 | .dmm_lisa_map_3 = 0xFF020100, | |
254 | .is_ma_present = 0x1 | |
255 | }; | |
256 | ||
257 | static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { | |
258 | .dmm_lisa_map_0 = 0x0, | |
259 | .dmm_lisa_map_1 = 0x0, | |
260 | .dmm_lisa_map_2 = 0x80600100, | |
261 | .dmm_lisa_map_3 = 0xFF020100, | |
262 | .is_ma_present = 0x1 | |
263 | }; | |
264 | ||
c4a2736c LV |
265 | const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { |
266 | .dmm_lisa_map_0 = 0x0, | |
267 | .dmm_lisa_map_1 = 0x0, | |
268 | .dmm_lisa_map_2 = 0x80740300, | |
269 | .dmm_lisa_map_3 = 0xFF020100, | |
270 | .is_ma_present = 0x1 | |
271 | }; | |
272 | ||
6b1c14bb RB |
273 | /* |
274 | * DRA722 EVM EMIF1 2GB CONFIGURATION | |
275 | * EMIF1 4 devices of 512Mb x 8 Micron | |
276 | */ | |
277 | const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { | |
278 | .dmm_lisa_map_0 = 0x0, | |
279 | .dmm_lisa_map_1 = 0x0, | |
280 | .dmm_lisa_map_2 = 0x80700100, | |
281 | .dmm_lisa_map_3 = 0xFF020100, | |
282 | .is_ma_present = 0x1 | |
283 | }; | |
284 | ||
a7638833 LV |
285 | void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) |
286 | { | |
c4a2736c LV |
287 | u64 ram_size; |
288 | ||
289 | ram_size = board_ti_get_emif_size(); | |
290 | ||
a7638833 LV |
291 | switch (omap_revision()) { |
292 | case DRA752_ES1_0: | |
293 | case DRA752_ES1_1: | |
294 | case DRA752_ES2_0: | |
c4a2736c LV |
295 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
296 | *dmm_lisa_regs = &lisa_map_dra7_2GB; | |
297 | else | |
298 | *dmm_lisa_regs = &lisa_map_dra7_1536MB; | |
a7638833 LV |
299 | break; |
300 | case DRA722_ES1_0: | |
6b1c14bb | 301 | case DRA722_ES2_0: |
a7638833 | 302 | default: |
6b1c14bb RB |
303 | if (ram_size < CONFIG_MAX_MEM_MAPPED) |
304 | *dmm_lisa_regs = &lisa_map_2G_x_2; | |
305 | else | |
306 | *dmm_lisa_regs = &lisa_map_2G_x_4; | |
307 | break; | |
a7638833 LV |
308 | } |
309 | } | |
310 | ||
1428d832 | 311 | struct vcores_data dra752_volts = { |
beb71279 LV |
312 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
313 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, | |
1428d832 K |
314 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
315 | .mpu.addr = TPS659038_REG_ADDR_SMPS12, | |
316 | .mpu.pmic = &tps659038, | |
317 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, | |
318 | ||
beb71279 LV |
319 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
320 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, | |
321 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, | |
322 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | |
323 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, | |
324 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, | |
1428d832 K |
325 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
326 | .eve.addr = TPS659038_REG_ADDR_SMPS45, | |
327 | .eve.pmic = &tps659038, | |
328 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, | |
329 | ||
beb71279 LV |
330 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
331 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | |
332 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | |
333 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | |
334 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | |
335 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | |
1428d832 K |
336 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
337 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, | |
338 | .gpu.pmic = &tps659038, | |
339 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, | |
340 | ||
beb71279 LV |
341 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
342 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, | |
1428d832 K |
343 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
344 | .core.addr = TPS659038_REG_ADDR_SMPS7, | |
345 | .core.pmic = &tps659038, | |
346 | ||
beb71279 LV |
347 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
348 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, | |
349 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, | |
350 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, | |
351 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, | |
352 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, | |
1428d832 K |
353 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
354 | .iva.addr = TPS659038_REG_ADDR_SMPS8, | |
355 | .iva.pmic = &tps659038, | |
356 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, | |
357 | }; | |
358 | ||
359 | struct vcores_data dra722_volts = { | |
beb71279 LV |
360 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
361 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, | |
1428d832 K |
362 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
363 | .mpu.addr = TPS65917_REG_ADDR_SMPS1, | |
364 | .mpu.pmic = &tps659038, | |
365 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, | |
366 | ||
beb71279 LV |
367 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
368 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, | |
1428d832 K |
369 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
370 | .core.addr = TPS65917_REG_ADDR_SMPS2, | |
371 | .core.pmic = &tps659038, | |
372 | ||
373 | /* | |
374 | * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x | |
375 | * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. | |
376 | */ | |
beb71279 LV |
377 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
378 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | |
379 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | |
380 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | |
381 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | |
382 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | |
1428d832 K |
383 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
384 | .gpu.addr = TPS65917_REG_ADDR_SMPS3, | |
385 | .gpu.pmic = &tps659038, | |
386 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, | |
387 | ||
beb71279 LV |
388 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
389 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, | |
390 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, | |
391 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | |
392 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, | |
393 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, | |
1428d832 K |
394 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
395 | .eve.addr = TPS65917_REG_ADDR_SMPS3, | |
396 | .eve.pmic = &tps659038, | |
397 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, | |
398 | ||
beb71279 LV |
399 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
400 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, | |
401 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, | |
402 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, | |
403 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, | |
404 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, | |
1428d832 K |
405 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
406 | .iva.addr = TPS65917_REG_ADDR_SMPS3, | |
407 | .iva.pmic = &tps659038, | |
408 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, | |
409 | }; | |
410 | ||
f56e6350 K |
411 | struct vcores_data dra718_volts = { |
412 | /* | |
413 | * In the case of dra71x GPU MPU and CORE | |
414 | * are all powered up by BUCK0 of LP873X PMIC | |
415 | */ | |
416 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, | |
417 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, | |
418 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | |
419 | .mpu.addr = LP873X_REG_ADDR_BUCK0, | |
420 | .mpu.pmic = &lp8733, | |
421 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, | |
422 | ||
423 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, | |
424 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, | |
425 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, | |
426 | .core.addr = LP873X_REG_ADDR_BUCK0, | |
427 | .core.pmic = &lp8733, | |
428 | ||
429 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | |
430 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | |
431 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | |
432 | .gpu.addr = LP873X_REG_ADDR_BUCK0, | |
433 | .gpu.pmic = &lp8733, | |
434 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, | |
435 | ||
436 | /* | |
437 | * The DSPEVE and IVA rails are grouped on DRA71x-evm | |
438 | * and are powered by BUCK1 of LP873X PMIC | |
439 | */ | |
440 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, | |
441 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | |
442 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, | |
443 | .eve.addr = LP873X_REG_ADDR_BUCK1, | |
444 | .eve.pmic = &lp8733, | |
445 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, | |
446 | ||
447 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, | |
448 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, | |
449 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, | |
450 | .iva.addr = LP873X_REG_ADDR_BUCK1, | |
451 | .iva.pmic = &lp8733, | |
452 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, | |
453 | }; | |
454 | ||
beb71279 LV |
455 | int get_voltrail_opp(int rail_offset) |
456 | { | |
457 | int opp; | |
458 | ||
f56e6350 K |
459 | /* |
460 | * DRA71x supports only OPP_NOM. | |
461 | */ | |
462 | if (board_is_dra71x_evm()) | |
463 | return OPP_NOM; | |
464 | ||
beb71279 LV |
465 | switch (rail_offset) { |
466 | case VOLT_MPU: | |
467 | opp = DRA7_MPU_OPP; | |
468 | break; | |
469 | case VOLT_CORE: | |
470 | opp = DRA7_CORE_OPP; | |
471 | break; | |
472 | case VOLT_GPU: | |
473 | opp = DRA7_GPU_OPP; | |
474 | break; | |
475 | case VOLT_EVE: | |
476 | opp = DRA7_DSPEVE_OPP; | |
477 | break; | |
478 | case VOLT_IVA: | |
479 | opp = DRA7_IVA_OPP; | |
480 | break; | |
481 | default: | |
482 | opp = OPP_NOM; | |
483 | } | |
484 | ||
485 | return opp; | |
486 | } | |
487 | ||
687054a7 LV |
488 | /** |
489 | * @brief board_init | |
490 | * | |
491 | * @return 0 | |
492 | */ | |
493 | int board_init(void) | |
494 | { | |
495 | gpmc_init(); | |
496 | gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
d468b178 LV |
501 | void dram_init_banksize(void) |
502 | { | |
503 | u64 ram_size; | |
504 | ||
505 | ram_size = board_ti_get_emif_size(); | |
506 | ||
507 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
508 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
509 | if (ram_size > CONFIG_MAX_MEM_MAPPED) { | |
510 | gd->bd->bi_dram[1].start = 0x200000000; | |
511 | gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; | |
512 | } | |
513 | } | |
514 | ||
21914ee6 RQ |
515 | int board_late_init(void) |
516 | { | |
4ec3f6e5 | 517 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
25afe55d LV |
518 | char *name = "unknown"; |
519 | ||
df6b506f LV |
520 | if (is_dra72x()) { |
521 | if (board_is_dra72x_revc_or_later()) | |
522 | name = "dra72x-revc"; | |
463dd225 LV |
523 | else if (board_is_dra71x_evm()) |
524 | name = "dra71x"; | |
df6b506f LV |
525 | else |
526 | name = "dra72x"; | |
527 | } else { | |
25afe55d | 528 | name = "dra7xx"; |
df6b506f | 529 | } |
25afe55d LV |
530 | |
531 | set_board_info_env(name); | |
f12467d1 | 532 | |
71c1b58e LV |
533 | /* |
534 | * Default FIT boot on HS devices. Non FIT images are not allowed | |
535 | * on HS devices. | |
536 | */ | |
537 | if (get_device_type() == HS_DEVICE) | |
538 | setenv("boot_fit", "1"); | |
539 | ||
07815eb9 | 540 | omap_die_id_serial(); |
4ec3f6e5 | 541 | #endif |
21914ee6 RQ |
542 | return 0; |
543 | } | |
544 | ||
25afe55d LV |
545 | #ifdef CONFIG_SPL_BUILD |
546 | void do_board_detect(void) | |
547 | { | |
548 | int rc; | |
549 | ||
550 | rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, | |
551 | CONFIG_EEPROM_CHIP_ADDRESS); | |
552 | if (rc) | |
553 | printf("ti_i2c_eeprom_init failed %d\n", rc); | |
554 | } | |
555 | ||
556 | #else | |
557 | ||
558 | void do_board_detect(void) | |
559 | { | |
560 | char *bname = NULL; | |
561 | int rc; | |
562 | ||
563 | rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, | |
564 | CONFIG_EEPROM_CHIP_ADDRESS); | |
565 | if (rc) | |
566 | printf("ti_i2c_eeprom_init failed %d\n", rc); | |
567 | ||
568 | if (board_is_dra74x_evm()) { | |
569 | bname = "DRA74x EVM"; | |
6b1c14bb RB |
570 | } else if (board_is_dra72x_evm()) { |
571 | bname = "DRA72x EVM"; | |
463dd225 LV |
572 | } else if (board_is_dra71x_evm()) { |
573 | bname = "DRA71x EVM"; | |
25afe55d | 574 | } else { |
6b1c14bb | 575 | /* If EEPROM is not populated */ |
25afe55d LV |
576 | if (is_dra72x()) |
577 | bname = "DRA72x EVM"; | |
578 | else | |
579 | bname = "DRA74x EVM"; | |
580 | } | |
581 | ||
582 | if (bname) | |
583 | snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, | |
584 | "Board: %s REV %s\n", bname, board_ti_get_rev()); | |
585 | } | |
586 | #endif /* CONFIG_SPL_BUILD */ | |
587 | ||
1428d832 K |
588 | void vcores_init(void) |
589 | { | |
590 | if (board_is_dra74x_evm()) { | |
591 | *omap_vcores = &dra752_volts; | |
592 | } else if (board_is_dra72x_evm()) { | |
593 | *omap_vcores = &dra722_volts; | |
f56e6350 K |
594 | } else if (board_is_dra71x_evm()) { |
595 | *omap_vcores = &dra718_volts; | |
1428d832 K |
596 | } else { |
597 | /* If EEPROM is not populated */ | |
598 | if (is_dra72x()) | |
599 | *omap_vcores = &dra722_volts; | |
600 | else | |
601 | *omap_vcores = &dra752_volts; | |
602 | } | |
603 | } | |
604 | ||
3ef56e61 | 605 | void set_muxconf_regs(void) |
687054a7 LV |
606 | { |
607 | do_set_mux32((*ctrl)->control_padconf_core_base, | |
706dd348 | 608 | early_padconf, ARRAY_SIZE(early_padconf)); |
687054a7 LV |
609 | } |
610 | ||
706dd348 LV |
611 | #ifdef CONFIG_IODELAY_RECALIBRATION |
612 | void recalibrate_iodelay(void) | |
613 | { | |
8cac1471 | 614 | struct pad_conf_entry const *pads, *delta_pads = NULL; |
03589234 | 615 | struct iodelay_cfg_entry const *iodelay; |
8cac1471 NM |
616 | int npads, niodelays, delta_npads = 0; |
617 | int ret; | |
03589234 NM |
618 | |
619 | switch (omap_revision()) { | |
620 | case DRA722_ES1_0: | |
8cac1471 NM |
621 | case DRA722_ES2_0: |
622 | pads = dra72x_core_padconf_array_common; | |
623 | npads = ARRAY_SIZE(dra72x_core_padconf_array_common); | |
4d748048 LV |
624 | if (board_is_dra71x_evm()) { |
625 | pads = dra71x_core_padconf_array; | |
626 | npads = ARRAY_SIZE(dra71x_core_padconf_array); | |
627 | iodelay = dra71_iodelay_cfg_array; | |
628 | niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); | |
629 | } else if (board_is_dra72x_revc_or_later()) { | |
8cac1471 NM |
630 | delta_pads = dra72x_rgmii_padconf_array_revc; |
631 | delta_npads = | |
632 | ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); | |
633 | iodelay = dra72_iodelay_cfg_array_revc; | |
634 | niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); | |
635 | } else { | |
636 | delta_pads = dra72x_rgmii_padconf_array_revb; | |
637 | delta_npads = | |
638 | ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); | |
639 | iodelay = dra72_iodelay_cfg_array_revb; | |
640 | niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); | |
641 | } | |
03589234 NM |
642 | break; |
643 | case DRA752_ES1_0: | |
644 | case DRA752_ES1_1: | |
645 | pads = dra74x_core_padconf_array; | |
646 | npads = ARRAY_SIZE(dra74x_core_padconf_array); | |
647 | iodelay = dra742_es1_1_iodelay_cfg_array; | |
648 | niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); | |
649 | break; | |
650 | default: | |
651 | case DRA752_ES2_0: | |
652 | pads = dra74x_core_padconf_array; | |
653 | npads = ARRAY_SIZE(dra74x_core_padconf_array); | |
654 | iodelay = dra742_es2_0_iodelay_cfg_array; | |
655 | niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); | |
76cff2b1 NM |
656 | /* Setup port1 and port2 for rgmii with 'no-id' mode */ |
657 | clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | | |
658 | RGMII1_ID_MODE_N_MASK); | |
03589234 | 659 | break; |
27d170af | 660 | } |
8cac1471 NM |
661 | /* Setup I/O isolation */ |
662 | ret = __recalibrate_iodelay_start(); | |
663 | if (ret) | |
664 | goto err; | |
665 | ||
666 | /* Do the muxing here */ | |
667 | do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); | |
668 | ||
669 | /* Now do the weird minor deltas that should be safe */ | |
670 | if (delta_npads) | |
671 | do_set_mux32((*ctrl)->control_padconf_core_base, | |
672 | delta_pads, delta_npads); | |
673 | ||
674 | /* Setup IOdelay configuration */ | |
675 | ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); | |
676 | err: | |
677 | /* Closeup.. remove isolation */ | |
678 | __recalibrate_iodelay_end(ret); | |
706dd348 LV |
679 | } |
680 | #endif | |
681 | ||
d5abcf94 | 682 | #if defined(CONFIG_GENERIC_MMC) |
687054a7 LV |
683 | int board_mmc_init(bd_t *bis) |
684 | { | |
685 | omap_mmc_init(0, 0, 0, -1, -1); | |
686 | omap_mmc_init(1, 0, 0, -1, -1); | |
687 | return 0; | |
688 | } | |
689 | #endif | |
b1e26e3b | 690 | |
a17188c1 KVA |
691 | #ifdef CONFIG_USB_DWC3 |
692 | static struct dwc3_device usb_otg_ss1 = { | |
693 | .maximum_speed = USB_SPEED_SUPER, | |
694 | .base = DRA7_USB_OTG_SS1_BASE, | |
695 | .tx_fifo_resize = false, | |
696 | .index = 0, | |
697 | }; | |
698 | ||
699 | static struct dwc3_omap_device usb_otg_ss1_glue = { | |
700 | .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, | |
701 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | |
a17188c1 KVA |
702 | .index = 0, |
703 | }; | |
704 | ||
705 | static struct ti_usb_phy_device usb_phy1_device = { | |
706 | .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, | |
707 | .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, | |
708 | .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, | |
709 | .index = 0, | |
710 | }; | |
711 | ||
712 | static struct dwc3_device usb_otg_ss2 = { | |
713 | .maximum_speed = USB_SPEED_SUPER, | |
714 | .base = DRA7_USB_OTG_SS2_BASE, | |
715 | .tx_fifo_resize = false, | |
716 | .index = 1, | |
717 | }; | |
718 | ||
719 | static struct dwc3_omap_device usb_otg_ss2_glue = { | |
720 | .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, | |
721 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | |
a17188c1 KVA |
722 | .index = 1, |
723 | }; | |
724 | ||
725 | static struct ti_usb_phy_device usb_phy2_device = { | |
726 | .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, | |
727 | .index = 1, | |
728 | }; | |
729 | ||
730 | int board_usb_init(int index, enum usb_init_type init) | |
731 | { | |
6f1af1e3 | 732 | enable_usb_clocks(index); |
a17188c1 KVA |
733 | switch (index) { |
734 | case 0: | |
735 | if (init == USB_INIT_DEVICE) { | |
736 | usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; | |
737 | usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | |
738 | } else { | |
739 | usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; | |
740 | usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; | |
741 | } | |
742 | ||
743 | ti_usb_phy_uboot_init(&usb_phy1_device); | |
744 | dwc3_omap_uboot_init(&usb_otg_ss1_glue); | |
745 | dwc3_uboot_init(&usb_otg_ss1); | |
746 | break; | |
747 | case 1: | |
748 | if (init == USB_INIT_DEVICE) { | |
749 | usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; | |
750 | usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | |
751 | } else { | |
752 | usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; | |
753 | usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; | |
754 | } | |
755 | ||
756 | ti_usb_phy_uboot_init(&usb_phy2_device); | |
757 | dwc3_omap_uboot_init(&usb_otg_ss2_glue); | |
758 | dwc3_uboot_init(&usb_otg_ss2); | |
759 | break; | |
760 | default: | |
761 | printf("Invalid Controller Index\n"); | |
762 | } | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | int board_usb_cleanup(int index, enum usb_init_type init) | |
768 | { | |
769 | switch (index) { | |
770 | case 0: | |
771 | case 1: | |
772 | ti_usb_phy_uboot_exit(index); | |
773 | dwc3_uboot_exit(index); | |
774 | dwc3_omap_uboot_exit(index); | |
775 | break; | |
776 | default: | |
777 | printf("Invalid Controller Index\n"); | |
778 | } | |
6f1af1e3 | 779 | disable_usb_clocks(index); |
a17188c1 KVA |
780 | return 0; |
781 | } | |
782 | ||
2d48aa69 | 783 | int usb_gadget_handle_interrupts(int index) |
a17188c1 KVA |
784 | { |
785 | u32 status; | |
786 | ||
2d48aa69 | 787 | status = dwc3_omap_uboot_interrupt_status(index); |
a17188c1 | 788 | if (status) |
2d48aa69 | 789 | dwc3_uboot_handle_interrupt(index); |
a17188c1 KVA |
790 | |
791 | return 0; | |
792 | } | |
793 | #endif | |
794 | ||
79b079f3 TR |
795 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) |
796 | int spl_start_uboot(void) | |
797 | { | |
798 | /* break into full u-boot on 'c' */ | |
799 | if (serial_tstc() && serial_getc() == 'c') | |
800 | return 1; | |
801 | ||
802 | #ifdef CONFIG_SPL_ENV_SUPPORT | |
803 | env_init(); | |
804 | env_relocate_spec(); | |
805 | if (getenv_yesno("boot_os") != 1) | |
806 | return 1; | |
807 | #endif | |
808 | ||
809 | return 0; | |
810 | } | |
811 | #endif | |
812 | ||
b1e26e3b | 813 | #ifdef CONFIG_DRIVER_TI_CPSW |
4c8014b9 M |
814 | extern u32 *const omap_si_rev; |
815 | ||
b1e26e3b M |
816 | static void cpsw_control(int enabled) |
817 | { | |
818 | /* VTP can be added here */ | |
819 | ||
820 | return; | |
821 | } | |
822 | ||
823 | static struct cpsw_slave_data cpsw_slaves[] = { | |
824 | { | |
825 | .slave_reg_ofs = 0x208, | |
826 | .sliver_reg_ofs = 0xd80, | |
9c653aad | 827 | .phy_addr = 2, |
b1e26e3b M |
828 | }, |
829 | { | |
830 | .slave_reg_ofs = 0x308, | |
831 | .sliver_reg_ofs = 0xdc0, | |
9c653aad | 832 | .phy_addr = 3, |
b1e26e3b M |
833 | }, |
834 | }; | |
835 | ||
836 | static struct cpsw_platform_data cpsw_data = { | |
837 | .mdio_base = CPSW_MDIO_BASE, | |
838 | .cpsw_base = CPSW_BASE, | |
839 | .mdio_div = 0xff, | |
840 | .channels = 8, | |
841 | .cpdma_reg_ofs = 0x800, | |
4c8014b9 | 842 | .slaves = 2, |
b1e26e3b M |
843 | .slave_data = cpsw_slaves, |
844 | .ale_reg_ofs = 0xd00, | |
845 | .ale_entries = 1024, | |
846 | .host_port_reg_ofs = 0x108, | |
847 | .hw_stats_reg_ofs = 0x900, | |
848 | .bd_ram_ofs = 0x2000, | |
849 | .mac_control = (1 << 5), | |
850 | .control = cpsw_control, | |
851 | .host_port_num = 0, | |
852 | .version = CPSW_CTRL_VERSION_2, | |
853 | }; | |
854 | ||
855 | int board_eth_init(bd_t *bis) | |
856 | { | |
857 | int ret; | |
858 | uint8_t mac_addr[6]; | |
859 | uint32_t mac_hi, mac_lo; | |
860 | uint32_t ctrl_val; | |
b1e26e3b M |
861 | |
862 | /* try reading mac address from efuse */ | |
863 | mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); | |
864 | mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); | |
e0a1d598 | 865 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
b1e26e3b | 866 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
e0a1d598 M |
867 | mac_addr[2] = mac_hi & 0xFF; |
868 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; | |
b1e26e3b | 869 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
e0a1d598 | 870 | mac_addr[5] = mac_lo & 0xFF; |
b1e26e3b M |
871 | |
872 | if (!getenv("ethaddr")) { | |
873 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); | |
874 | ||
0adb5b76 | 875 | if (is_valid_ethaddr(mac_addr)) |
b1e26e3b M |
876 | eth_setenv_enetaddr("ethaddr", mac_addr); |
877 | } | |
8feb37b9 M |
878 | |
879 | mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); | |
880 | mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); | |
881 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; | |
882 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
883 | mac_addr[2] = mac_hi & 0xFF; | |
884 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; | |
885 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; | |
886 | mac_addr[5] = mac_lo & 0xFF; | |
887 | ||
888 | if (!getenv("eth1addr")) { | |
0adb5b76 | 889 | if (is_valid_ethaddr(mac_addr)) |
8feb37b9 M |
890 | eth_setenv_enetaddr("eth1addr", mac_addr); |
891 | } | |
892 | ||
b1e26e3b M |
893 | ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); |
894 | ctrl_val |= 0x22; | |
895 | writel(ctrl_val, (*ctrl)->control_core_control_io1); | |
896 | ||
4c8014b9 M |
897 | if (*omap_si_rev == DRA722_ES1_0) |
898 | cpsw_data.active_slave = 1; | |
899 | ||
39fbac91 DM |
900 | if (board_is_dra72x_revc_or_later()) { |
901 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; | |
902 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; | |
903 | } | |
904 | ||
b1e26e3b M |
905 | ret = cpsw_register(&cpsw_data); |
906 | if (ret < 0) | |
907 | printf("Error %d registering CPSW switch\n", ret); | |
908 | ||
909 | return ret; | |
910 | } | |
911 | #endif | |
7b922523 LV |
912 | |
913 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
914 | /* VTT regulator enable */ | |
915 | static inline void vtt_regulator_enable(void) | |
916 | { | |
917 | if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) | |
918 | return; | |
919 | ||
920 | /* Do not enable VTT for DRA722 */ | |
6b1c14bb | 921 | if (is_dra72x()) |
7b922523 LV |
922 | return; |
923 | ||
924 | /* | |
925 | * EVM Rev G and later use gpio7_11 for DDR3 termination. | |
926 | * This is safe enough to do on older revs. | |
927 | */ | |
928 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); | |
929 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); | |
930 | } | |
931 | ||
932 | int board_early_init_f(void) | |
933 | { | |
934 | vtt_regulator_enable(); | |
935 | return 0; | |
936 | } | |
937 | #endif | |
62a09f05 DA |
938 | |
939 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
940 | int ft_board_setup(void *blob, bd_t *bd) | |
941 | { | |
942 | ft_cpu_setup(blob, bd); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | #endif | |
09da87da LV |
947 | |
948 | #ifdef CONFIG_SPL_LOAD_FIT | |
949 | int board_fit_config_name_match(const char *name) | |
950 | { | |
e8131386 | 951 | if (is_dra72x()) { |
40de70fb LV |
952 | if (board_is_dra71x_evm()) { |
953 | if (!strcmp(name, "dra71-evm")) | |
954 | return 0; | |
955 | }else if(board_is_dra72x_revc_or_later()) { | |
e8131386 M |
956 | if (!strcmp(name, "dra72-evm-revc")) |
957 | return 0; | |
958 | } else if (!strcmp(name, "dra72-evm")) { | |
959 | return 0; | |
960 | } | |
961 | } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { | |
09da87da | 962 | return 0; |
e8131386 M |
963 | } |
964 | ||
965 | return -1; | |
09da87da LV |
966 | } |
967 | #endif | |
17c29873 AD |
968 | |
969 | #ifdef CONFIG_TI_SECURE_DEVICE | |
970 | void board_fit_image_post_process(void **p_image, size_t *p_size) | |
971 | { | |
972 | secure_boot_verify_image(p_image, p_size); | |
973 | } | |
0fcc5207 AD |
974 | |
975 | void board_tee_image_process(ulong tee_image, size_t tee_size) | |
976 | { | |
977 | secure_tee_install((u32)tee_image); | |
978 | } | |
979 | ||
980 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); | |
17c29873 | 981 | #endif |