[people/ms/u-boot.git] / board / ti / evm / evm.c

/*
 * (C) Copyright 2004-2011
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Manikandan Pillai <mani.pillai@ti.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include "evm.h"

#define OMAP3EVM_GPIO_ETH_RST_GEN1		64
#define OMAP3EVM_GPIO_ETH_RST_GEN2		7

DECLARE_GLOBAL_DATA_PTR;

static u32 omap3_evm_version;

u32 get_omap3_evm_rev(void)
{
	return omap3_evm_version;
}

static void omap3_evm_get_revision(void)
{
#if defined(CONFIG_CMD_NET)
	/*
	 * Board revision can be ascertained only by identifying
	 * the Ethernet chipset.
	 */
	unsigned int smsc_id;

	/* Ethernet PHY ID is stored at ID_REV register */
	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
	printf("Read back SMSC id 0x%x\n", smsc_id);

	switch (smsc_id) {
	/* SMSC9115 chipset */
	case 0x01150000:
		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
		break;
	/* SMSC 9220 chipset */
	case 0x92200000:
	default:
		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
       }
#else
#if defined(CONFIG_STATIC_BOARD_REV)
	/*
	 * Look for static defintion of the board revision
	 */
	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
#else
	/*
	 * Fallback to the default above.
	 */
	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
#endif
#endif	/* CONFIG_CMD_NET */
}

#ifdef CONFIG_USB_OMAP3
/*
 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
 */
u8 omap3_evm_need_extvbus(void)
{
	u8 retval = 0;

	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
		retval = 1;

	return retval;
}
#endif

/*
 * Routine: board_init
 * Description: Early hardware init.
 */
int board_init(void)
{
	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	/* board id for Linux */
	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
	/* boot param addr */
	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);

	return 0;
}

#ifdef CONFIG_SPL_BUILD
/*
 * Routine: get_board_mem_timings
 * Description: If we use SPL then there is no x-loader nor config header
 * so we have to setup the DDR timings ourself on the first bank.  This
 * provides the timing values back to the function that configures
 * the memory.
 */
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
	int pop_mfr, pop_id;

	/*
	 * We need to identify what PoP memory is on the board so that
	 * we know what timings to use.  To map the ID values please see
	 * nand_ids.c
	 */
	identify_nand_chip(&pop_mfr, &pop_id);

	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
		/* 256MB DDR */
		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
		timings->ctrla = HYNIX_V_ACTIMA_200;
		timings->ctrlb = HYNIX_V_ACTIMB_200;
	} else {
		/* 128MB DDR */
		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
		timings->ctrla = MICRON_V_ACTIMA_165;
		timings->ctrlb = MICRON_V_ACTIMB_165;
	}
	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
	timings->mr = MICRON_V_MR_165;
}
#endif

/*
 * Routine: misc_init_r
 * Description: Init ethernet (done here so udelay works)
 */
int misc_init_r(void)
{

#ifdef CONFIG_DRIVER_OMAP34XX_I2C
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

#if defined(CONFIG_CMD_NET)
	setup_net_chip();
#endif
	omap3_evm_get_revision();

#if defined(CONFIG_CMD_NET)
	reset_net_chip();
#endif
	dieid_num_r();

	return 0;
}

/*
 * Routine: set_muxconf_regs
 * Description: Setting up the configuration Mux registers specific to the
 *		hardware. Many pins need to be moved from protect to primary
 *		mode.
 */
void set_muxconf_regs(void)
{
	MUX_EVM();
}

#ifdef CONFIG_CMD_NET
/*
 * Routine: setup_net_chip
 * Description: Setting up the configuration GPMC registers specific to the
 *		Ethernet hardware.
 */
static void setup_net_chip(void)
{
	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

	/* Configure GPMC registers */
	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);

	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
		&ctrl_base->gpmc_nadv_ale);
}

/**
 * Reset the ethernet chip.
 */
static void reset_net_chip(void)
{
	int ret;
	int rst_gpio;

	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
	} else {
		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
	}

	ret = gpio_request(rst_gpio, "");
	if (ret < 0) {
		printf("Unable to get GPIO %d\n", rst_gpio);
		return ;
	}

	/* Configure as output */
	gpio_direction_output(rst_gpio, 0);

	/* Send a pulse on the GPIO pin */
	gpio_set_value(rst_gpio, 1);
	udelay(1);
	gpio_set_value(rst_gpio, 0);
	udelay(1);
	gpio_set_value(rst_gpio, 1);
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
#define STR_ENV_ETHADDR	"ethaddr"

	struct eth_device *dev;
	uchar eth_addr[6];

	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);

	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
		dev = eth_get_dev_by_index(0);
		if (dev) {
			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
		} else {
			printf("omap3evm: Couldn't get eth device\n");
			rc = -1;
		}
	}
#endif
	return rc;
}
#endif /* CONFIG_CMD_NET */

#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
	return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
Commit	Line	Data
ad9bc8e5	1	/*
673283f3	2	* (C) Copyright 2004-2011
ad9bc8e5 DB	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Author :
	6	* Manikandan Pillai <mani.pillai@ti.com>
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
ad9bc8e5 DB	13	*/
ad9bc8e5 DB	14	#include <common.h>
736fead8	15	#include <netdev.h>
ad9bc8e5 DB	16	#include <asm/io.h>
	17	#include <asm/arch/mem.h>
	18	#include <asm/arch/mux.h>
	19	#include <asm/arch/sys_proto.h>
dcc4f38b	20	#include <asm/arch/mmc_host_def.h>
84c3b631	21	#include <asm/gpio.h>
ad9bc8e5 DB	22	#include <i2c.h>
ad9bc8e5 DB	23	#include <asm/mach-types.h>
673283f3	24	#include <linux/mtd/nand.h>
ad9bc8e5 DB	25	#include "evm.h"
ad9bc8e5 DB	26
c0682587 S	27	#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
	28	#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
	29
29565326 JR	30	DECLARE_GLOBAL_DATA_PTR;
29565326 JR	31
b606ef41	32	static u32 omap3_evm_version;
b5abf644	33
b606ef41	34	u32 get_omap3_evm_rev(void)
b5abf644 AKG	35	{
	36	return omap3_evm_version;
	37	}
	38
	39	static void omap3_evm_get_revision(void)
	40	{
76ee9a2c SP	41	#if defined(CONFIG_CMD_NET)
	42	/*
	43	* Board revision can be ascertained only by identifying
	44	* the Ethernet chipset.
	45	*/
b5abf644 AKG	46	unsigned int smsc_id;
	47
	48	/* Ethernet PHY ID is stored at ID_REV register */
	49	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
	50	printf("Read back SMSC id 0x%x\n", smsc_id);
	51
	52	switch (smsc_id) {
	53	/* SMSC9115 chipset */
	54	case 0x01150000:
	55	omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
	56	break;
	57	/* SMSC 9220 chipset */
	58	case 0x92200000:
	59	default:
	60	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
	61	}
76ee9a2c SP	62	#else
	63	#if defined(CONFIG_STATIC_BOARD_REV)
	64	/*
	65	* Look for static defintion of the board revision
	66	*/
	67	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
	68	#else
	69	/*
	70	* Fallback to the default above.
	71	*/
	72	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
	73	#endif
	74	#endif /* CONFIG_CMD_NET */
b5abf644 AKG	75	}
b5abf644 AKG	76
63f42400	77	#ifdef CONFIG_USB_OMAP3
944a4894 AKG	78	/*
	79	* MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
	80	*/
	81	u8 omap3_evm_need_extvbus(void)
	82	{
	83	u8 retval = 0;
	84
	85	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
	86	retval = 1;
	87
	88	return retval;
	89	}
63f42400	90	#endif
944a4894	91
58911517	92	/*
ad9bc8e5 DB	93	* Routine: board_init
ad9bc8e5 DB	94	* Description: Early hardware init.
58911517	95	*/
ad9bc8e5 DB	96	int board_init(void)
ad9bc8e5 DB	97	{
ad9bc8e5 DB	98	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	99	/* board id for Linux */
	100	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
	101	/* boot param addr */
	102	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
	103
	104	return 0;
	105	}
	106
673283f3 TR	107	#ifdef CONFIG_SPL_BUILD
	108	/*
	109	* Routine: get_board_mem_timings
	110	* Description: If we use SPL then there is no x-loader nor config header
	111	* so we have to setup the DDR timings ourself on the first bank. This
	112	* provides the timing values back to the function that configures
	113	* the memory.
	114	*/
8c4445d2	115	void get_board_mem_timings(struct board_sdrc_timings *timings)
673283f3 TR	116	{
	117	int pop_mfr, pop_id;
	118
	119	/*
	120	* We need to identify what PoP memory is on the board so that
	121	* we know what timings to use. To map the ID values please see
	122	* nand_ids.c
	123	*/
	124	identify_nand_chip(&pop_mfr, &pop_id);
	125
	126	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
	127	/* 256MB DDR */
8c4445d2 PB	128	timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
	129	timings->ctrla = HYNIX_V_ACTIMA_200;
	130	timings->ctrlb = HYNIX_V_ACTIMB_200;
673283f3 TR	131	} else {
673283f3 TR	132	/* 128MB DDR */
8c4445d2 PB	133	timings->mcfg = MICRON_V_MCFG_165(128 << 20);
	134	timings->ctrla = MICRON_V_ACTIMA_165;
	135	timings->ctrlb = MICRON_V_ACTIMB_165;
673283f3	136	}
8c4445d2 PB	137	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
8c4445d2 PB	138	timings->mr = MICRON_V_MR_165;
673283f3 TR	139	}
	140	#endif
	141
58911517	142	/*
ad9bc8e5 DB	143	* Routine: misc_init_r
ad9bc8e5 DB	144	* Description: Init ethernet (done here so udelay works)
58911517	145	*/
ad9bc8e5 DB	146	int misc_init_r(void)
	147	{
	148
	149	#ifdef CONFIG_DRIVER_OMAP34XX_I2C
	150	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	151	#endif
	152
	153	#if defined(CONFIG_CMD_NET)
	154	setup_net_chip();
	155	#endif
76ee9a2c	156	omap3_evm_get_revision();
ad9bc8e5	157
6921b314 SP	158	#if defined(CONFIG_CMD_NET)
	159	reset_net_chip();
	160	#endif
e6a6a704 DB	161	dieid_num_r();
e6a6a704 DB	162
ad9bc8e5 DB	163	return 0;
	164	}
	165
58911517	166	/*
ad9bc8e5 DB	167	* Routine: set_muxconf_regs
	168	* Description: Setting up the configuration Mux registers specific to the
	169	* hardware. Many pins need to be moved from protect to primary
	170	* mode.
58911517	171	*/
ad9bc8e5 DB	172	void set_muxconf_regs(void)
	173	{
	174	MUX_EVM();
	175	}
	176
5626f336	177	#ifdef CONFIG_CMD_NET
58911517	178	/*
ad9bc8e5 DB	179	* Routine: setup_net_chip
	180	* Description: Setting up the configuration GPMC registers specific to the
	181	* Ethernet hardware.
58911517	182	*/
ad9bc8e5 DB	183	static void setup_net_chip(void)
ad9bc8e5 DB	184	{
97a099ea	185	struct ctrl ctrl_base = (struct ctrl )OMAP34XX_CTRL_BASE;
ad9bc8e5 DB	186
ad9bc8e5 DB	187	/* Configure GPMC registers */
89411352 DB	188	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
	189	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
	190	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
	191	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
	192	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
	193	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
	194	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
ad9bc8e5 DB	195
	196	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
	197	writew(readw(&ctrl_base ->gpmc_nwe) \| 0x0E00, &ctrl_base->gpmc_nwe);
	198	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
	199	writew(readw(&ctrl_base->gpmc_noe) \| 0x0E00, &ctrl_base->gpmc_noe);
	200	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
	201	writew(readw(&ctrl_base->gpmc_nadv_ale) \| 0x0E00,
	202	&ctrl_base->gpmc_nadv_ale);
6921b314 SP	203	}
	204
	205	/**
	206	* Reset the ethernet chip.
	207	*/
	208	static void reset_net_chip(void)
	209	{
c0682587 S	210	int ret;
	211	int rst_gpio;
	212
	213	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
	214	rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
	215	} else {
	216	rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
	217	}
	218
84c3b631	219	ret = gpio_request(rst_gpio, "");
c0682587 S	220	if (ret < 0) {
	221	printf("Unable to get GPIO %d\n", rst_gpio);
	222	return ;
	223	}
	224
	225	/* Configure as output */
84c3b631	226	gpio_direction_output(rst_gpio, 0);
c0682587 S	227
c0682587 S	228	/* Send a pulse on the GPIO pin */
84c3b631	229	gpio_set_value(rst_gpio, 1);
ad9bc8e5	230	udelay(1);
84c3b631	231	gpio_set_value(rst_gpio, 0);
ad9bc8e5	232	udelay(1);
84c3b631	233	gpio_set_value(rst_gpio, 1);
ad9bc8e5	234	}
736fead8 BW	235
	236	int board_eth_init(bd_t *bis)
	237	{
	238	int rc = 0;
	239	#ifdef CONFIG_SMC911X
5e463a24 SP	240	#define STR_ENV_ETHADDR "ethaddr"
	241
	242	struct eth_device *dev;
	243	uchar eth_addr[6];
	244
736fead8	245	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
5e463a24 SP	246
	247	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
	248	dev = eth_get_dev_by_index(0);
	249	if (dev) {
	250	eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
	251	} else {
	252	printf("omap3evm: Couldn't get eth device\n");
	253	rc = -1;
	254	}
	255	}
736fead8 BW	256	#endif
	257	return rc;
	258	}
5626f336	259	#endif /* CONFIG_CMD_NET */
dcc4f38b	260
673283f3	261	#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
dcc4f38b VH	262	int board_mmc_init(bd_t *bis)
dcc4f38b VH	263	{
e3913f56	264	return omap_mmc_init(0, 0, 0, -1, -1);
dcc4f38b VH	265	}
dcc4f38b VH	266	#endif