]>
Commit | Line | Data |
---|---|---|
ad9bc8e5 DB |
1 | /* |
2 | * (C) Copyright 2004-2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Author : | |
6 | * Manikandan Pillai <mani.pillai@ti.com> | |
7 | * | |
8 | * Derived from Beagle Board and 3430 SDP code by | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <khasim@ti.com> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | #include <common.h> | |
736fead8 | 31 | #include <netdev.h> |
ad9bc8e5 DB |
32 | #include <asm/io.h> |
33 | #include <asm/arch/mem.h> | |
34 | #include <asm/arch/mux.h> | |
35 | #include <asm/arch/sys_proto.h> | |
36 | #include <i2c.h> | |
37 | #include <asm/mach-types.h> | |
38 | #include "evm.h" | |
39 | ||
58911517 | 40 | /* |
ad9bc8e5 DB |
41 | * Routine: board_init |
42 | * Description: Early hardware init. | |
58911517 | 43 | */ |
ad9bc8e5 DB |
44 | int board_init(void) |
45 | { | |
46 | DECLARE_GLOBAL_DATA_PTR; | |
47 | ||
48 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ | |
49 | /* board id for Linux */ | |
50 | gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; | |
51 | /* boot param addr */ | |
52 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
58911517 | 57 | /* |
ad9bc8e5 DB |
58 | * Routine: misc_init_r |
59 | * Description: Init ethernet (done here so udelay works) | |
58911517 | 60 | */ |
ad9bc8e5 DB |
61 | int misc_init_r(void) |
62 | { | |
63 | ||
64 | #ifdef CONFIG_DRIVER_OMAP34XX_I2C | |
65 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
66 | #endif | |
67 | ||
68 | #if defined(CONFIG_CMD_NET) | |
69 | setup_net_chip(); | |
70 | #endif | |
71 | ||
e6a6a704 DB |
72 | dieid_num_r(); |
73 | ||
ad9bc8e5 DB |
74 | return 0; |
75 | } | |
76 | ||
58911517 | 77 | /* |
ad9bc8e5 DB |
78 | * Routine: set_muxconf_regs |
79 | * Description: Setting up the configuration Mux registers specific to the | |
80 | * hardware. Many pins need to be moved from protect to primary | |
81 | * mode. | |
58911517 | 82 | */ |
ad9bc8e5 DB |
83 | void set_muxconf_regs(void) |
84 | { | |
85 | MUX_EVM(); | |
86 | } | |
87 | ||
58911517 | 88 | /* |
ad9bc8e5 DB |
89 | * Routine: setup_net_chip |
90 | * Description: Setting up the configuration GPMC registers specific to the | |
91 | * Ethernet hardware. | |
58911517 | 92 | */ |
ad9bc8e5 DB |
93 | static void setup_net_chip(void) |
94 | { | |
97a099ea | 95 | struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; |
97a099ea | 96 | struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
ad9bc8e5 DB |
97 | |
98 | /* Configure GPMC registers */ | |
89411352 DB |
99 | writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); |
100 | writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); | |
101 | writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); | |
102 | writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); | |
103 | writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); | |
104 | writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); | |
105 | writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); | |
ad9bc8e5 DB |
106 | |
107 | /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ | |
108 | writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); | |
109 | /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ | |
110 | writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); | |
111 | /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ | |
112 | writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, | |
113 | &ctrl_base->gpmc_nadv_ale); | |
114 | ||
115 | /* Make GPIO 64 as output pin */ | |
116 | writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); | |
117 | ||
118 | /* Now send a pulse on the GPIO pin */ | |
119 | writel(GPIO0, &gpio3_base->setdataout); | |
120 | udelay(1); | |
121 | writel(GPIO0, &gpio3_base->cleardataout); | |
122 | udelay(1); | |
123 | writel(GPIO0, &gpio3_base->setdataout); | |
124 | } | |
736fead8 BW |
125 | |
126 | int board_eth_init(bd_t *bis) | |
127 | { | |
128 | int rc = 0; | |
129 | #ifdef CONFIG_SMC911X | |
130 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); | |
131 | #endif | |
132 | return rc; | |
133 | } |