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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ad9bc8e5 | 2 | /* |
673283f3 | 3 | * (C) Copyright 2004-2011 |
ad9bc8e5 DB |
4 | * Texas Instruments, <www.ti.com> |
5 | * | |
6 | * Author : | |
7 | * Manikandan Pillai <mani.pillai@ti.com> | |
8 | * | |
9 | * Derived from Beagle Board and 3430 SDP code by | |
10 | * Richard Woodruff <r-woodruff2@ti.com> | |
11 | * Syed Mohammed Khasim <khasim@ti.com> | |
ad9bc8e5 DB |
12 | */ |
13 | #include <common.h> | |
0d43fded DW |
14 | #include <dm.h> |
15 | #include <ns16550.h> | |
736fead8 | 16 | #include <netdev.h> |
ad9bc8e5 DB |
17 | #include <asm/io.h> |
18 | #include <asm/arch/mem.h> | |
19 | #include <asm/arch/mux.h> | |
20 | #include <asm/arch/sys_proto.h> | |
dcc4f38b | 21 | #include <asm/arch/mmc_host_def.h> |
84c3b631 | 22 | #include <asm/gpio.h> |
ad9bc8e5 | 23 | #include <i2c.h> |
aac5450e | 24 | #include <twl4030.h> |
ad9bc8e5 | 25 | #include <asm/mach-types.h> |
0d43fded | 26 | #include <asm/omap_musb.h> |
6ae3900a | 27 | #include <linux/mtd/rawnand.h> |
0d43fded DW |
28 | #include <linux/usb/ch9.h> |
29 | #include <linux/usb/gadget.h> | |
30 | #include <linux/usb/musb.h> | |
ad9bc8e5 DB |
31 | #include "evm.h" |
32 | ||
0d43fded DW |
33 | #ifdef CONFIG_USB_EHCI_HCD |
34 | #include <usb.h> | |
35 | #include <asm/ehci-omap.h> | |
36 | #endif | |
37 | ||
38 | #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 | |
39 | #define OMAP3EVM_GPIO_ETH_RST_GEN2 7 | |
c0682587 | 40 | |
29565326 JR |
41 | DECLARE_GLOBAL_DATA_PTR; |
42 | ||
0d43fded DW |
43 | static const struct ns16550_platdata omap3_evm_serial = { |
44 | .base = OMAP34XX_UART1, | |
45 | .reg_shift = 2, | |
46 | .clock = V_NS16550_CLK, | |
47 | .fcr = UART_FCR_DEFVAL, | |
48 | }; | |
49 | ||
50 | U_BOOT_DEVICE(omap3_evm_uart) = { | |
51 | "ns16550_serial", | |
52 | &omap3_evm_serial | |
53 | }; | |
54 | ||
b606ef41 | 55 | static u32 omap3_evm_version; |
b5abf644 | 56 | |
b606ef41 | 57 | u32 get_omap3_evm_rev(void) |
b5abf644 AKG |
58 | { |
59 | return omap3_evm_version; | |
60 | } | |
61 | ||
62 | static void omap3_evm_get_revision(void) | |
63 | { | |
76ee9a2c SP |
64 | #if defined(CONFIG_CMD_NET) |
65 | /* | |
66 | * Board revision can be ascertained only by identifying | |
67 | * the Ethernet chipset. | |
68 | */ | |
b5abf644 AKG |
69 | unsigned int smsc_id; |
70 | ||
71 | /* Ethernet PHY ID is stored at ID_REV register */ | |
72 | smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; | |
73 | printf("Read back SMSC id 0x%x\n", smsc_id); | |
74 | ||
75 | switch (smsc_id) { | |
76 | /* SMSC9115 chipset */ | |
77 | case 0x01150000: | |
78 | omap3_evm_version = OMAP3EVM_BOARD_GEN_1; | |
79 | break; | |
80 | /* SMSC 9220 chipset */ | |
81 | case 0x92200000: | |
82 | default: | |
83 | omap3_evm_version = OMAP3EVM_BOARD_GEN_2; | |
84 | } | |
0d43fded | 85 | #else /* !CONFIG_CMD_NET */ |
76ee9a2c | 86 | #if defined(CONFIG_STATIC_BOARD_REV) |
0d43fded | 87 | /* Look for static defintion of the board revision */ |
76ee9a2c SP |
88 | omap3_evm_version = CONFIG_STATIC_BOARD_REV; |
89 | #else | |
0d43fded | 90 | /* Fallback to the default above */ |
76ee9a2c | 91 | omap3_evm_version = OMAP3EVM_BOARD_GEN_2; |
0d43fded DW |
92 | #endif /* CONFIG_STATIC_BOARD_REV */ |
93 | #endif /* CONFIG_CMD_NET */ | |
b5abf644 AKG |
94 | } |
95 | ||
0d43fded DW |
96 | #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST) |
97 | /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */ | |
944a4894 AKG |
98 | u8 omap3_evm_need_extvbus(void) |
99 | { | |
100 | u8 retval = 0; | |
101 | ||
102 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | |
103 | retval = 1; | |
104 | ||
105 | return retval; | |
106 | } | |
0d43fded | 107 | #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */ |
944a4894 | 108 | |
58911517 | 109 | /* |
ad9bc8e5 DB |
110 | * Routine: board_init |
111 | * Description: Early hardware init. | |
58911517 | 112 | */ |
ad9bc8e5 DB |
113 | int board_init(void) |
114 | { | |
ad9bc8e5 DB |
115 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
116 | /* board id for Linux */ | |
117 | gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; | |
118 | /* boot param addr */ | |
119 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
c257c96d DW |
124 | #if defined(CONFIG_SPL_OS_BOOT) |
125 | int spl_start_uboot(void) | |
126 | { | |
127 | /* break into full u-boot on 'c' */ | |
128 | if (serial_tstc() && serial_getc() == 'c') | |
129 | return 1; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | #endif /* CONFIG_SPL_OS_BOOT */ | |
134 | ||
0d43fded | 135 | #if defined(CONFIG_SPL_BUILD) |
673283f3 TR |
136 | /* |
137 | * Routine: get_board_mem_timings | |
138 | * Description: If we use SPL then there is no x-loader nor config header | |
139 | * so we have to setup the DDR timings ourself on the first bank. This | |
140 | * provides the timing values back to the function that configures | |
141 | * the memory. | |
142 | */ | |
8c4445d2 | 143 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
673283f3 TR |
144 | { |
145 | int pop_mfr, pop_id; | |
146 | ||
147 | /* | |
148 | * We need to identify what PoP memory is on the board so that | |
149 | * we know what timings to use. To map the ID values please see | |
150 | * nand_ids.c | |
151 | */ | |
152 | identify_nand_chip(&pop_mfr, &pop_id); | |
153 | ||
154 | if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { | |
155 | /* 256MB DDR */ | |
8c4445d2 PB |
156 | timings->mcfg = HYNIX_V_MCFG_200(256 << 20); |
157 | timings->ctrla = HYNIX_V_ACTIMA_200; | |
158 | timings->ctrlb = HYNIX_V_ACTIMB_200; | |
673283f3 TR |
159 | } else { |
160 | /* 128MB DDR */ | |
8c4445d2 PB |
161 | timings->mcfg = MICRON_V_MCFG_165(128 << 20); |
162 | timings->ctrla = MICRON_V_ACTIMA_165; | |
163 | timings->ctrlb = MICRON_V_ACTIMB_165; | |
673283f3 | 164 | } |
8c4445d2 PB |
165 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
166 | timings->mr = MICRON_V_MR_165; | |
673283f3 | 167 | } |
0d43fded DW |
168 | #endif /* CONFIG_SPL_BUILD */ |
169 | ||
170 | #if defined(CONFIG_USB_MUSB_OMAP2PLUS) | |
171 | static struct musb_hdrc_config musb_config = { | |
172 | .multipoint = 1, | |
173 | .dyn_fifo = 1, | |
174 | .num_eps = 16, | |
175 | .ram_bits = 12, | |
176 | }; | |
177 | ||
178 | static struct omap_musb_board_data musb_board_data = { | |
179 | .interface_type = MUSB_INTERFACE_ULPI, | |
180 | }; | |
181 | ||
182 | static struct musb_hdrc_platform_data musb_plat = { | |
183 | #if defined(CONFIG_USB_MUSB_HOST) | |
184 | .mode = MUSB_HOST, | |
185 | #elif defined(CONFIG_USB_MUSB_GADGET) | |
186 | .mode = MUSB_PERIPHERAL, | |
187 | #else | |
188 | #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" | |
189 | #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */ | |
190 | .config = &musb_config, | |
191 | .power = 100, | |
192 | .platform_ops = &omap2430_ops, | |
193 | .board_data = &musb_board_data, | |
194 | }; | |
195 | #endif /* CONFIG_USB_MUSB_OMAP2PLUS */ | |
673283f3 | 196 | |
58911517 | 197 | /* |
ad9bc8e5 DB |
198 | * Routine: misc_init_r |
199 | * Description: Init ethernet (done here so udelay works) | |
58911517 | 200 | */ |
ad9bc8e5 DB |
201 | int misc_init_r(void) |
202 | { | |
0d43fded | 203 | twl4030_power_init(); |
ad9bc8e5 | 204 | |
94d50bed | 205 | #ifdef CONFIG_SYS_I2C_OMAP24XX |
6789e84e | 206 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); |
ad9bc8e5 DB |
207 | #endif |
208 | ||
209 | #if defined(CONFIG_CMD_NET) | |
210 | setup_net_chip(); | |
211 | #endif | |
76ee9a2c | 212 | omap3_evm_get_revision(); |
ad9bc8e5 | 213 | |
6921b314 SP |
214 | #if defined(CONFIG_CMD_NET) |
215 | reset_net_chip(); | |
216 | #endif | |
679f82c3 | 217 | omap_die_id_display(); |
e6a6a704 | 218 | |
0d43fded DW |
219 | #if defined(CONFIG_USB_MUSB_OMAP2PLUS) |
220 | musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); | |
221 | #endif | |
222 | ||
223 | #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) | |
224 | omap_die_id_usbethaddr(); | |
225 | #endif | |
ad9bc8e5 DB |
226 | return 0; |
227 | } | |
228 | ||
58911517 | 229 | /* |
ad9bc8e5 DB |
230 | * Routine: set_muxconf_regs |
231 | * Description: Setting up the configuration Mux registers specific to the | |
232 | * hardware. Many pins need to be moved from protect to primary | |
233 | * mode. | |
58911517 | 234 | */ |
ad9bc8e5 DB |
235 | void set_muxconf_regs(void) |
236 | { | |
237 | MUX_EVM(); | |
238 | } | |
239 | ||
0d43fded | 240 | #if defined(CONFIG_CMD_NET) |
58911517 | 241 | /* |
ad9bc8e5 DB |
242 | * Routine: setup_net_chip |
243 | * Description: Setting up the configuration GPMC registers specific to the | |
244 | * Ethernet hardware. | |
58911517 | 245 | */ |
ad9bc8e5 DB |
246 | static void setup_net_chip(void) |
247 | { | |
97a099ea | 248 | struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
ad9bc8e5 DB |
249 | |
250 | /* Configure GPMC registers */ | |
89411352 DB |
251 | writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); |
252 | writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); | |
253 | writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); | |
254 | writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); | |
255 | writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); | |
256 | writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); | |
257 | writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); | |
ad9bc8e5 DB |
258 | |
259 | /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ | |
260 | writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); | |
261 | /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ | |
262 | writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); | |
263 | /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ | |
264 | writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, | |
265 | &ctrl_base->gpmc_nadv_ale); | |
6921b314 SP |
266 | } |
267 | ||
268 | /** | |
269 | * Reset the ethernet chip. | |
270 | */ | |
271 | static void reset_net_chip(void) | |
272 | { | |
c0682587 S |
273 | int ret; |
274 | int rst_gpio; | |
275 | ||
276 | if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) { | |
277 | rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1; | |
278 | } else { | |
279 | rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; | |
280 | } | |
281 | ||
84c3b631 | 282 | ret = gpio_request(rst_gpio, ""); |
c0682587 S |
283 | if (ret < 0) { |
284 | printf("Unable to get GPIO %d\n", rst_gpio); | |
285 | return ; | |
286 | } | |
287 | ||
288 | /* Configure as output */ | |
84c3b631 | 289 | gpio_direction_output(rst_gpio, 0); |
c0682587 S |
290 | |
291 | /* Send a pulse on the GPIO pin */ | |
84c3b631 | 292 | gpio_set_value(rst_gpio, 1); |
ad9bc8e5 | 293 | udelay(1); |
84c3b631 | 294 | gpio_set_value(rst_gpio, 0); |
ad9bc8e5 | 295 | udelay(1); |
84c3b631 | 296 | gpio_set_value(rst_gpio, 1); |
ad9bc8e5 | 297 | } |
736fead8 BW |
298 | |
299 | int board_eth_init(bd_t *bis) | |
300 | { | |
0d43fded | 301 | #if defined(CONFIG_SMC911X) |
836e67ee DW |
302 | env_set("ethaddr", NULL); |
303 | return smc911x_initialize(0, CONFIG_SMC911X_BASE); | |
304 | #else | |
305 | return 0; | |
306 | #endif | |
736fead8 | 307 | } |
5626f336 | 308 | #endif /* CONFIG_CMD_NET */ |
dcc4f38b | 309 | |
4aa2ba3a | 310 | #if defined(CONFIG_MMC) |
dcc4f38b VH |
311 | int board_mmc_init(bd_t *bis) |
312 | { | |
e3913f56 | 313 | return omap_mmc_init(0, 0, 0, -1, -1); |
dcc4f38b | 314 | } |
aac5450e | 315 | |
aac5450e PK |
316 | void board_mmc_power_init(void) |
317 | { | |
318 | twl4030_power_mmc_init(0); | |
319 | } | |
0d43fded DW |
320 | #endif /* CONFIG_MMC */ |
321 | ||
c257c96d DW |
322 | #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) |
323 | /* Call usb_stop() before starting the kernel */ | |
324 | void show_boot_progress(int val) | |
325 | { | |
326 | if (val == BOOTSTAGE_ID_RUN_OS) | |
327 | usb_stop(); | |
328 | } | |
329 | ||
0d43fded DW |
330 | static struct omap_usbhs_board_data usbhs_bdata = { |
331 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, | |
332 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
333 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED | |
334 | }; | |
335 | ||
336 | int ehci_hcd_init(int index, enum usb_init_type init, | |
337 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
338 | { | |
339 | return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); | |
340 | } | |
341 | ||
342 | int ehci_hcd_stop(int index) | |
343 | { | |
344 | return omap_ehci_hcd_stop(); | |
345 | } | |
346 | #endif /* CONFIG_USB_EHCI_HCD */ | |
347 | ||
348 | #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET) | |
349 | int board_eth_init(bd_t *bis) | |
350 | { | |
351 | return usb_eth_initialize(bis); | |
352 | } | |
353 | #endif /* CONFIG_USB_ETHER */ |