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ad9bc8e5 | 1 | /* |
673283f3 | 2 | * (C) Copyright 2004-2011 |
ad9bc8e5 DB |
3 | * Texas Instruments, <www.ti.com> |
4 | * | |
5 | * Author : | |
6 | * Manikandan Pillai <mani.pillai@ti.com> | |
7 | * | |
8 | * Derived from Beagle Board and 3430 SDP code by | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <khasim@ti.com> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | #include <common.h> | |
736fead8 | 31 | #include <netdev.h> |
ad9bc8e5 DB |
32 | #include <asm/io.h> |
33 | #include <asm/arch/mem.h> | |
34 | #include <asm/arch/mux.h> | |
35 | #include <asm/arch/sys_proto.h> | |
dcc4f38b | 36 | #include <asm/arch/mmc_host_def.h> |
84c3b631 | 37 | #include <asm/gpio.h> |
ad9bc8e5 DB |
38 | #include <i2c.h> |
39 | #include <asm/mach-types.h> | |
673283f3 | 40 | #include <linux/mtd/nand.h> |
ad9bc8e5 DB |
41 | #include "evm.h" |
42 | ||
c0682587 S |
43 | #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 |
44 | #define OMAP3EVM_GPIO_ETH_RST_GEN2 7 | |
45 | ||
29565326 JR |
46 | DECLARE_GLOBAL_DATA_PTR; |
47 | ||
b606ef41 | 48 | static u32 omap3_evm_version; |
b5abf644 | 49 | |
b606ef41 | 50 | u32 get_omap3_evm_rev(void) |
b5abf644 AKG |
51 | { |
52 | return omap3_evm_version; | |
53 | } | |
54 | ||
55 | static void omap3_evm_get_revision(void) | |
56 | { | |
76ee9a2c SP |
57 | #if defined(CONFIG_CMD_NET) |
58 | /* | |
59 | * Board revision can be ascertained only by identifying | |
60 | * the Ethernet chipset. | |
61 | */ | |
b5abf644 AKG |
62 | unsigned int smsc_id; |
63 | ||
64 | /* Ethernet PHY ID is stored at ID_REV register */ | |
65 | smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; | |
66 | printf("Read back SMSC id 0x%x\n", smsc_id); | |
67 | ||
68 | switch (smsc_id) { | |
69 | /* SMSC9115 chipset */ | |
70 | case 0x01150000: | |
71 | omap3_evm_version = OMAP3EVM_BOARD_GEN_1; | |
72 | break; | |
73 | /* SMSC 9220 chipset */ | |
74 | case 0x92200000: | |
75 | default: | |
76 | omap3_evm_version = OMAP3EVM_BOARD_GEN_2; | |
77 | } | |
76ee9a2c SP |
78 | #else |
79 | #if defined(CONFIG_STATIC_BOARD_REV) | |
80 | /* | |
81 | * Look for static defintion of the board revision | |
82 | */ | |
83 | omap3_evm_version = CONFIG_STATIC_BOARD_REV; | |
84 | #else | |
85 | /* | |
86 | * Fallback to the default above. | |
87 | */ | |
88 | omap3_evm_version = OMAP3EVM_BOARD_GEN_2; | |
89 | #endif | |
90 | #endif /* CONFIG_CMD_NET */ | |
b5abf644 AKG |
91 | } |
92 | ||
63f42400 | 93 | #ifdef CONFIG_USB_OMAP3 |
944a4894 AKG |
94 | /* |
95 | * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. | |
96 | */ | |
97 | u8 omap3_evm_need_extvbus(void) | |
98 | { | |
99 | u8 retval = 0; | |
100 | ||
101 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | |
102 | retval = 1; | |
103 | ||
104 | return retval; | |
105 | } | |
63f42400 | 106 | #endif |
944a4894 | 107 | |
58911517 | 108 | /* |
ad9bc8e5 DB |
109 | * Routine: board_init |
110 | * Description: Early hardware init. | |
58911517 | 111 | */ |
ad9bc8e5 DB |
112 | int board_init(void) |
113 | { | |
ad9bc8e5 DB |
114 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
115 | /* board id for Linux */ | |
116 | gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; | |
117 | /* boot param addr */ | |
118 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
673283f3 TR |
123 | #ifdef CONFIG_SPL_BUILD |
124 | /* | |
125 | * Routine: get_board_mem_timings | |
126 | * Description: If we use SPL then there is no x-loader nor config header | |
127 | * so we have to setup the DDR timings ourself on the first bank. This | |
128 | * provides the timing values back to the function that configures | |
129 | * the memory. | |
130 | */ | |
131 | void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, | |
132 | u32 *mr) | |
133 | { | |
134 | int pop_mfr, pop_id; | |
135 | ||
136 | /* | |
137 | * We need to identify what PoP memory is on the board so that | |
138 | * we know what timings to use. To map the ID values please see | |
139 | * nand_ids.c | |
140 | */ | |
141 | identify_nand_chip(&pop_mfr, &pop_id); | |
142 | ||
143 | if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { | |
144 | /* 256MB DDR */ | |
145 | *mcfg = HYNIX_V_MCFG_200(256 << 20); | |
146 | *ctrla = HYNIX_V_ACTIMA_200; | |
147 | *ctrlb = HYNIX_V_ACTIMB_200; | |
148 | } else { | |
149 | /* 128MB DDR */ | |
150 | *mcfg = MICRON_V_MCFG_165(128 << 20); | |
151 | *ctrla = MICRON_V_ACTIMA_165; | |
152 | *ctrlb = MICRON_V_ACTIMB_165; | |
153 | } | |
154 | *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; | |
155 | *mr = MICRON_V_MR_165; | |
156 | } | |
157 | #endif | |
158 | ||
58911517 | 159 | /* |
ad9bc8e5 DB |
160 | * Routine: misc_init_r |
161 | * Description: Init ethernet (done here so udelay works) | |
58911517 | 162 | */ |
ad9bc8e5 DB |
163 | int misc_init_r(void) |
164 | { | |
165 | ||
166 | #ifdef CONFIG_DRIVER_OMAP34XX_I2C | |
167 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
168 | #endif | |
169 | ||
170 | #if defined(CONFIG_CMD_NET) | |
171 | setup_net_chip(); | |
172 | #endif | |
76ee9a2c | 173 | omap3_evm_get_revision(); |
ad9bc8e5 | 174 | |
6921b314 SP |
175 | #if defined(CONFIG_CMD_NET) |
176 | reset_net_chip(); | |
177 | #endif | |
e6a6a704 DB |
178 | dieid_num_r(); |
179 | ||
ad9bc8e5 DB |
180 | return 0; |
181 | } | |
182 | ||
58911517 | 183 | /* |
ad9bc8e5 DB |
184 | * Routine: set_muxconf_regs |
185 | * Description: Setting up the configuration Mux registers specific to the | |
186 | * hardware. Many pins need to be moved from protect to primary | |
187 | * mode. | |
58911517 | 188 | */ |
ad9bc8e5 DB |
189 | void set_muxconf_regs(void) |
190 | { | |
191 | MUX_EVM(); | |
192 | } | |
193 | ||
5626f336 | 194 | #ifdef CONFIG_CMD_NET |
58911517 | 195 | /* |
ad9bc8e5 DB |
196 | * Routine: setup_net_chip |
197 | * Description: Setting up the configuration GPMC registers specific to the | |
198 | * Ethernet hardware. | |
58911517 | 199 | */ |
ad9bc8e5 DB |
200 | static void setup_net_chip(void) |
201 | { | |
97a099ea | 202 | struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
ad9bc8e5 DB |
203 | |
204 | /* Configure GPMC registers */ | |
89411352 DB |
205 | writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); |
206 | writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); | |
207 | writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); | |
208 | writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); | |
209 | writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); | |
210 | writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); | |
211 | writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); | |
ad9bc8e5 DB |
212 | |
213 | /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ | |
214 | writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); | |
215 | /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ | |
216 | writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); | |
217 | /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ | |
218 | writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, | |
219 | &ctrl_base->gpmc_nadv_ale); | |
6921b314 SP |
220 | } |
221 | ||
222 | /** | |
223 | * Reset the ethernet chip. | |
224 | */ | |
225 | static void reset_net_chip(void) | |
226 | { | |
c0682587 S |
227 | int ret; |
228 | int rst_gpio; | |
229 | ||
230 | if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) { | |
231 | rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1; | |
232 | } else { | |
233 | rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; | |
234 | } | |
235 | ||
84c3b631 | 236 | ret = gpio_request(rst_gpio, ""); |
c0682587 S |
237 | if (ret < 0) { |
238 | printf("Unable to get GPIO %d\n", rst_gpio); | |
239 | return ; | |
240 | } | |
241 | ||
242 | /* Configure as output */ | |
84c3b631 | 243 | gpio_direction_output(rst_gpio, 0); |
c0682587 S |
244 | |
245 | /* Send a pulse on the GPIO pin */ | |
84c3b631 | 246 | gpio_set_value(rst_gpio, 1); |
ad9bc8e5 | 247 | udelay(1); |
84c3b631 | 248 | gpio_set_value(rst_gpio, 0); |
ad9bc8e5 | 249 | udelay(1); |
84c3b631 | 250 | gpio_set_value(rst_gpio, 1); |
ad9bc8e5 | 251 | } |
736fead8 BW |
252 | |
253 | int board_eth_init(bd_t *bis) | |
254 | { | |
255 | int rc = 0; | |
256 | #ifdef CONFIG_SMC911X | |
5e463a24 SP |
257 | #define STR_ENV_ETHADDR "ethaddr" |
258 | ||
259 | struct eth_device *dev; | |
260 | uchar eth_addr[6]; | |
261 | ||
736fead8 | 262 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
5e463a24 SP |
263 | |
264 | if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { | |
265 | dev = eth_get_dev_by_index(0); | |
266 | if (dev) { | |
267 | eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); | |
268 | } else { | |
269 | printf("omap3evm: Couldn't get eth device\n"); | |
270 | rc = -1; | |
271 | } | |
272 | } | |
736fead8 BW |
273 | #endif |
274 | return rc; | |
275 | } | |
5626f336 | 276 | #endif /* CONFIG_CMD_NET */ |
dcc4f38b | 277 | |
673283f3 | 278 | #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) |
dcc4f38b VH |
279 | int board_mmc_init(bd_t *bis) |
280 | { | |
bbbc1ae9 | 281 | omap_mmc_init(0, 0, 0); |
dcc4f38b VH |
282 | return 0; |
283 | } | |
284 | #endif |